1#ifndef _ASM_POWERPC_PAGE_64_H
2#define _ASM_POWERPC_PAGE_64_H
3
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16
17
18#define HW_PAGE_SHIFT 12
19#define HW_PAGE_SIZE (ASM_CONST(1) << HW_PAGE_SHIFT)
20#define HW_PAGE_MASK (~(HW_PAGE_SIZE-1))
21
22
23
24
25
26#define PAGE_FACTOR (PAGE_SHIFT - HW_PAGE_SHIFT)
27
28
29#define SID_SHIFT 28
30#define SID_MASK ASM_CONST(0xfffffffff)
31#define ESID_MASK 0xfffffffff0000000UL
32#define GET_ESID(x) (((x) >> SID_SHIFT) & SID_MASK)
33
34
35#define SID_SHIFT_1T 40
36#define SID_MASK_1T 0xffffffUL
37#define ESID_MASK_1T 0xffffff0000000000UL
38#define GET_ESID_1T(x) (((x) >> SID_SHIFT_1T) & SID_MASK_1T)
39
40#ifndef __ASSEMBLY__
41#include <asm/cache.h>
42
43typedef unsigned long pte_basic_t;
44
45static __inline__ void clear_page(void *addr)
46{
47 unsigned long lines, line_size;
48
49 line_size = ppc64_caches.dline_size;
50 lines = ppc64_caches.dlines_per_page;
51
52 __asm__ __volatile__(
53 "mtctr %1 # clear_page\n\
541: dcbz 0,%0\n\
55 add %0,%0,%3\n\
56 bdnz+ 1b"
57 : "=r" (addr)
58 : "r" (lines), "0" (addr), "r" (line_size)
59 : "ctr", "memory");
60}
61
62extern void copy_page(void *to, void *from);
63
64
65extern u64 ppc64_pft_size;
66
67#endif
68
69#ifdef CONFIG_PPC_MM_SLICES
70
71#define SLICE_LOW_SHIFT 28
72#define SLICE_HIGH_SHIFT 40
73
74#define SLICE_LOW_TOP (0x100000000ul)
75#define SLICE_NUM_LOW (SLICE_LOW_TOP >> SLICE_LOW_SHIFT)
76#define SLICE_NUM_HIGH (PGTABLE_RANGE >> SLICE_HIGH_SHIFT)
77
78#define GET_LOW_SLICE_INDEX(addr) ((addr) >> SLICE_LOW_SHIFT)
79#define GET_HIGH_SLICE_INDEX(addr) ((addr) >> SLICE_HIGH_SHIFT)
80
81
82
83
84
85
86
87#define SLICE_MASK_SIZE 8
88
89#ifndef __ASSEMBLY__
90
91struct slice_mask {
92 u16 low_slices;
93 u64 high_slices;
94};
95
96struct mm_struct;
97
98extern unsigned long slice_get_unmapped_area(unsigned long addr,
99 unsigned long len,
100 unsigned long flags,
101 unsigned int psize,
102 int topdown);
103
104extern unsigned int get_slice_psize(struct mm_struct *mm,
105 unsigned long addr);
106
107extern void slice_init_context(struct mm_struct *mm, unsigned int psize);
108extern void slice_set_user_psize(struct mm_struct *mm, unsigned int psize);
109extern void slice_set_range_psize(struct mm_struct *mm, unsigned long start,
110 unsigned long len, unsigned int psize);
111
112#define slice_mm_new_context(mm) ((mm)->context.id == MMU_NO_CONTEXT)
113
114#endif
115#else
116#define slice_init()
117#ifdef CONFIG_PPC_STD_MMU_64
118#define get_slice_psize(mm, addr) ((mm)->context.user_psize)
119#define slice_set_user_psize(mm, psize) \
120do { \
121 (mm)->context.user_psize = (psize); \
122 (mm)->context.sllp = SLB_VSID_USER | mmu_psize_defs[(psize)].sllp; \
123} while (0)
124#else
125#ifdef CONFIG_PPC_64K_PAGES
126#define get_slice_psize(mm, addr) MMU_PAGE_64K
127#else
128#define get_slice_psize(mm, addr) MMU_PAGE_4K
129#endif
130#define slice_set_user_psize(mm, psize) do { BUG(); } while(0)
131#endif
132
133#define slice_set_range_psize(mm, start, len, psize) \
134 slice_set_user_psize((mm), (psize))
135#define slice_mm_new_context(mm) 1
136#endif
137
138#ifdef CONFIG_HUGETLB_PAGE
139
140#ifdef CONFIG_PPC_MM_SLICES
141#define HAVE_ARCH_HUGETLB_UNMAPPED_AREA
142#endif
143
144#endif
145
146#define VM_DATA_DEFAULT_FLAGS \
147 (is_32bit_task() ? \
148 VM_DATA_DEFAULT_FLAGS32 : VM_DATA_DEFAULT_FLAGS64)
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150
151
152
153
154
155
156#define VM_STACK_DEFAULT_FLAGS32 (VM_READ | VM_WRITE | VM_EXEC | \
157 VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
158
159#define VM_STACK_DEFAULT_FLAGS64 (VM_READ | VM_WRITE | \
160 VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
161
162#define VM_STACK_DEFAULT_FLAGS \
163 (is_32bit_task() ? \
164 VM_STACK_DEFAULT_FLAGS32 : VM_STACK_DEFAULT_FLAGS64)
165
166#include <asm-generic/getorder.h>
167
168#endif
169