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12#include <dt-bindings/clock/exynos5410.h>
13
14#include <linux/clk.h>
15#include <linux/clkdev.h>
16#include <linux/clk-provider.h>
17#include <linux/of.h>
18#include <linux/of_address.h>
19
20#include "clk.h"
21
22#define APLL_LOCK 0x0
23#define APLL_CON0 0x100
24#define CPLL_LOCK 0x10020
25#define CPLL_CON0 0x10120
26#define MPLL_LOCK 0x4000
27#define MPLL_CON0 0x4100
28#define BPLL_LOCK 0x20010
29#define BPLL_CON0 0x20110
30#define KPLL_LOCK 0x28000
31#define KPLL_CON0 0x28100
32
33#define SRC_CPU 0x200
34#define DIV_CPU0 0x500
35#define SRC_CPERI1 0x4204
36#define DIV_TOP0 0x10510
37#define DIV_TOP1 0x10514
38#define DIV_FSYS1 0x1054c
39#define DIV_FSYS2 0x10550
40#define DIV_PERIC0 0x10558
41#define SRC_TOP0 0x10210
42#define SRC_TOP1 0x10214
43#define SRC_TOP2 0x10218
44#define SRC_FSYS 0x10244
45#define SRC_PERIC0 0x10250
46#define SRC_MASK_FSYS 0x10340
47#define SRC_MASK_PERIC0 0x10350
48#define GATE_BUS_FSYS0 0x10740
49#define GATE_IP_FSYS 0x10944
50#define GATE_IP_PERIC 0x10950
51#define GATE_IP_PERIS 0x10960
52#define SRC_CDREX 0x20200
53#define SRC_KFC 0x28200
54#define DIV_KFC0 0x28500
55
56
57enum exynos5410_plls {
58 apll, cpll, mpll,
59 bpll, kpll,
60 nr_plls
61};
62
63
64PNAME(apll_p) = { "fin_pll", "fout_apll", };
65PNAME(bpll_p) = { "fin_pll", "fout_bpll", };
66PNAME(cpll_p) = { "fin_pll", "fout_cpll" };
67PNAME(mpll_p) = { "fin_pll", "fout_mpll", };
68PNAME(kpll_p) = { "fin_pll", "fout_kpll", };
69
70PNAME(mout_cpu_p) = { "mout_apll", "sclk_mpll", };
71PNAME(mout_kfc_p) = { "mout_kpll", "sclk_mpll", };
72
73PNAME(mpll_user_p) = { "fin_pll", "sclk_mpll", };
74PNAME(bpll_user_p) = { "fin_pll", "sclk_bpll", };
75PNAME(mpll_bpll_p) = { "sclk_mpll_muxed", "sclk_bpll_muxed", };
76
77PNAME(group2_p) = { "fin_pll", "fin_pll", "none", "none",
78 "none", "none", "sclk_mpll_bpll",
79 "none", "none", "sclk_cpll" };
80
81static struct samsung_mux_clock exynos5410_mux_clks[] __initdata = {
82 MUX(0, "mout_apll", apll_p, SRC_CPU, 0, 1),
83 MUX(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1),
84
85 MUX(0, "mout_kpll", kpll_p, SRC_KFC, 0, 1),
86 MUX(0, "mout_kfc", mout_kfc_p, SRC_KFC, 16, 1),
87
88 MUX(0, "sclk_mpll", mpll_p, SRC_CPERI1, 8, 1),
89 MUX(0, "sclk_mpll_muxed", mpll_user_p, SRC_TOP2, 20, 1),
90
91 MUX(0, "sclk_bpll", bpll_p, SRC_CDREX, 0, 1),
92 MUX(0, "sclk_bpll_muxed", bpll_user_p, SRC_TOP2, 24, 1),
93
94 MUX(0, "sclk_cpll", cpll_p, SRC_TOP2, 8, 1),
95
96 MUX(0, "sclk_mpll_bpll", mpll_bpll_p, SRC_TOP1, 20, 1),
97
98 MUX(0, "mout_mmc0", group2_p, SRC_FSYS, 0, 4),
99 MUX(0, "mout_mmc1", group2_p, SRC_FSYS, 4, 4),
100 MUX(0, "mout_mmc2", group2_p, SRC_FSYS, 8, 4),
101
102 MUX(0, "mout_uart0", group2_p, SRC_PERIC0, 0, 4),
103 MUX(0, "mout_uart1", group2_p, SRC_PERIC0, 4, 4),
104 MUX(0, "mout_uart2", group2_p, SRC_PERIC0, 8, 4),
105
106 MUX(0, "mout_aclk200", mpll_bpll_p, SRC_TOP0, 12, 1),
107 MUX(0, "mout_aclk400", mpll_bpll_p, SRC_TOP0, 20, 1),
108};
109
110static struct samsung_div_clock exynos5410_div_clks[] __initdata = {
111 DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3),
112 DIV(0, "div_arm2", "div_arm", DIV_CPU0, 28, 3),
113
114 DIV(0, "div_acp", "div_arm2", DIV_CPU0, 8, 3),
115 DIV(0, "div_cpud", "div_arm2", DIV_CPU0, 4, 3),
116 DIV(0, "div_atb", "div_arm2", DIV_CPU0, 16, 3),
117 DIV(0, "pclk_dbg", "div_arm2", DIV_CPU0, 20, 3),
118
119 DIV(0, "div_kfc", "mout_kfc", DIV_KFC0, 0, 3),
120 DIV(0, "div_aclk", "div_kfc", DIV_KFC0, 4, 3),
121 DIV(0, "div_pclk", "div_kfc", DIV_KFC0, 20, 3),
122
123 DIV(0, "aclk66_pre", "sclk_mpll_muxed", DIV_TOP1, 24, 3),
124 DIV(0, "aclk66", "aclk66_pre", DIV_TOP0, 0, 3),
125
126 DIV(0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
127 DIV(0, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4),
128 DIV(0, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4),
129
130 DIV_F(0, "div_mmc_pre0", "div_mmc0",
131 DIV_FSYS1, 8, 8, CLK_SET_RATE_PARENT, 0),
132 DIV_F(0, "div_mmc_pre1", "div_mmc1",
133 DIV_FSYS1, 24, 8, CLK_SET_RATE_PARENT, 0),
134 DIV_F(0, "div_mmc_pre2", "div_mmc2",
135 DIV_FSYS2, 8, 8, CLK_SET_RATE_PARENT, 0),
136
137 DIV(0, "div_uart0", "mout_uart0", DIV_PERIC0, 0, 4),
138 DIV(0, "div_uart1", "mout_uart1", DIV_PERIC0, 4, 4),
139 DIV(0, "div_uart2", "mout_uart2", DIV_PERIC0, 8, 4),
140 DIV(0, "div_uart3", "mout_uart3", DIV_PERIC0, 12, 4),
141
142 DIV(0, "aclk200", "mout_aclk200", DIV_TOP0, 12, 3),
143 DIV(0, "aclk400", "mout_aclk400", DIV_TOP0, 24, 3),
144};
145
146static struct samsung_gate_clock exynos5410_gate_clks[] __initdata = {
147 GATE(CLK_MCT, "mct", "aclk66", GATE_IP_PERIS, 18, 0, 0),
148
149 GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc_pre0",
150 SRC_MASK_FSYS, 0, CLK_SET_RATE_PARENT, 0),
151 GATE(CLK_SCLK_MMC1, "sclk_mmc1", "div_mmc_pre1",
152 SRC_MASK_FSYS, 4, CLK_SET_RATE_PARENT, 0),
153 GATE(CLK_SCLK_MMC2, "sclk_mmc2", "div_mmc_pre2",
154 SRC_MASK_FSYS, 8, CLK_SET_RATE_PARENT, 0),
155
156 GATE(CLK_MMC0, "sdmmc0", "aclk200", GATE_BUS_FSYS0, 12, 0, 0),
157 GATE(CLK_MMC1, "sdmmc1", "aclk200", GATE_BUS_FSYS0, 13, 0, 0),
158 GATE(CLK_MMC2, "sdmmc2", "aclk200", GATE_BUS_FSYS0, 14, 0, 0),
159
160 GATE(CLK_UART0, "uart0", "aclk66", GATE_IP_PERIC, 0, 0, 0),
161 GATE(CLK_UART1, "uart1", "aclk66", GATE_IP_PERIC, 1, 0, 0),
162 GATE(CLK_UART2, "uart2", "aclk66", GATE_IP_PERIC, 2, 0, 0),
163
164 GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0",
165 SRC_MASK_PERIC0, 0, CLK_SET_RATE_PARENT, 0),
166 GATE(CLK_SCLK_UART1, "sclk_uart1", "div_uart1",
167 SRC_MASK_PERIC0, 4, CLK_SET_RATE_PARENT, 0),
168 GATE(CLK_SCLK_UART2, "sclk_uart2", "div_uart2",
169 SRC_MASK_PERIC0, 8, CLK_SET_RATE_PARENT, 0),
170};
171
172static struct samsung_pll_clock exynos5410_plls[nr_plls] __initdata = {
173 [apll] = PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK,
174 APLL_CON0, NULL),
175 [cpll] = PLL(pll_35xx, CLK_FOUT_CPLL, "fout_cpll", "fin_pll", CPLL_LOCK,
176 CPLL_CON0, NULL),
177 [mpll] = PLL(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", MPLL_LOCK,
178 MPLL_CON0, NULL),
179 [bpll] = PLL(pll_35xx, CLK_FOUT_BPLL, "fout_bpll", "fin_pll", BPLL_LOCK,
180 BPLL_CON0, NULL),
181 [kpll] = PLL(pll_35xx, CLK_FOUT_KPLL, "fout_kpll", "fin_pll", KPLL_LOCK,
182 KPLL_CON0, NULL),
183};
184
185
186static void __init exynos5410_clk_init(struct device_node *np)
187{
188 struct samsung_clk_provider *ctx;
189 void __iomem *reg_base;
190
191 reg_base = of_iomap(np, 0);
192 if (!reg_base)
193 panic("%s: failed to map registers\n", __func__);
194
195 ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS);
196
197 samsung_clk_register_pll(ctx, exynos5410_plls,
198 ARRAY_SIZE(exynos5410_plls), reg_base);
199
200 samsung_clk_register_mux(ctx, exynos5410_mux_clks,
201 ARRAY_SIZE(exynos5410_mux_clks));
202 samsung_clk_register_div(ctx, exynos5410_div_clks,
203 ARRAY_SIZE(exynos5410_div_clks));
204 samsung_clk_register_gate(ctx, exynos5410_gate_clks,
205 ARRAY_SIZE(exynos5410_gate_clks));
206
207 samsung_clk_of_add_provider(np, ctx);
208
209 pr_debug("Exynos5410: clock setup completed.\n");
210}
211CLK_OF_DECLARE(exynos5410_clk, "samsung,exynos5410-clock", exynos5410_clk_init);
212
