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11#include <linux/clk.h>
12#include <linux/clkdev.h>
13#include <linux/clk-provider.h>
14#include <linux/of.h>
15#include <linux/of_address.h>
16#include <linux/syscore_ops.h>
17
18#include <dt-bindings/clock/s3c2410.h>
19
20#include "clk.h"
21#include "clk-pll.h"
22
23#define LOCKTIME 0x00
24#define MPLLCON 0x04
25#define UPLLCON 0x08
26#define CLKCON 0x0c
27#define CLKSLOW 0x10
28#define CLKDIVN 0x14
29#define CAMDIVN 0x18
30
31
32enum supported_socs {
33 S3C2410,
34 S3C2440,
35 S3C2442,
36};
37
38
39enum s3c2410_plls {
40 mpll, upll,
41};
42
43static void __iomem *reg_base;
44
45#ifdef CONFIG_PM_SLEEP
46static struct samsung_clk_reg_dump *s3c2410_save;
47
48
49
50
51
52static unsigned long s3c2410_clk_regs[] __initdata = {
53 LOCKTIME,
54 MPLLCON,
55 UPLLCON,
56 CLKCON,
57 CLKSLOW,
58 CLKDIVN,
59 CAMDIVN,
60};
61
62static int s3c2410_clk_suspend(void)
63{
64 samsung_clk_save(reg_base, s3c2410_save,
65 ARRAY_SIZE(s3c2410_clk_regs));
66
67 return 0;
68}
69
70static void s3c2410_clk_resume(void)
71{
72 samsung_clk_restore(reg_base, s3c2410_save,
73 ARRAY_SIZE(s3c2410_clk_regs));
74}
75
76static struct syscore_ops s3c2410_clk_syscore_ops = {
77 .suspend = s3c2410_clk_suspend,
78 .resume = s3c2410_clk_resume,
79};
80
81static void s3c2410_clk_sleep_init(void)
82{
83 s3c2410_save = samsung_clk_alloc_reg_dump(s3c2410_clk_regs,
84 ARRAY_SIZE(s3c2410_clk_regs));
85 if (!s3c2410_save) {
86 pr_warn("%s: failed to allocate sleep save data, no sleep support!\n",
87 __func__);
88 return;
89 }
90
91 register_syscore_ops(&s3c2410_clk_syscore_ops);
92 return;
93}
94#else
95static void s3c2410_clk_sleep_init(void) {}
96#endif
97
98PNAME(fclk_p) = { "mpll", "div_slow" };
99
100struct samsung_mux_clock s3c2410_common_muxes[] __initdata = {
101 MUX(FCLK, "fclk", fclk_p, CLKSLOW, 4, 1),
102};
103
104static struct clk_div_table divslow_d[] = {
105 { .val = 0, .div = 1 },
106 { .val = 1, .div = 2 },
107 { .val = 2, .div = 4 },
108 { .val = 3, .div = 6 },
109 { .val = 4, .div = 8 },
110 { .val = 5, .div = 10 },
111 { .val = 6, .div = 12 },
112 { .val = 7, .div = 14 },
113 { },
114};
115
116struct samsung_div_clock s3c2410_common_dividers[] __initdata = {
117 DIV_T(0, "div_slow", "xti", CLKSLOW, 0, 3, divslow_d),
118 DIV(PCLK, "pclk", "hclk", CLKDIVN, 0, 1),
119};
120
121struct samsung_gate_clock s3c2410_common_gates[] __initdata = {
122 GATE(PCLK_SPI, "spi", "pclk", CLKCON, 18, 0, 0),
123 GATE(PCLK_I2S, "i2s", "pclk", CLKCON, 17, 0, 0),
124 GATE(PCLK_I2C, "i2c", "pclk", CLKCON, 16, 0, 0),
125 GATE(PCLK_ADC, "adc", "pclk", CLKCON, 15, 0, 0),
126 GATE(PCLK_RTC, "rtc", "pclk", CLKCON, 14, 0, 0),
127 GATE(PCLK_GPIO, "gpio", "pclk", CLKCON, 13, CLK_IGNORE_UNUSED, 0),
128 GATE(PCLK_UART2, "uart2", "pclk", CLKCON, 12, 0, 0),
129 GATE(PCLK_UART1, "uart1", "pclk", CLKCON, 11, 0, 0),
130 GATE(PCLK_UART0, "uart0", "pclk", CLKCON, 10, 0, 0),
131 GATE(PCLK_SDI, "sdi", "pclk", CLKCON, 9, 0, 0),
132 GATE(PCLK_PWM, "pwm", "pclk", CLKCON, 8, 0, 0),
133 GATE(HCLK_USBD, "usb-device", "hclk", CLKCON, 7, 0, 0),
134 GATE(HCLK_USBH, "usb-host", "hclk", CLKCON, 6, 0, 0),
135 GATE(HCLK_LCD, "lcd", "hclk", CLKCON, 5, 0, 0),
136 GATE(HCLK_NAND, "nand", "hclk", CLKCON, 4, 0, 0),
137};
138
139
140struct samsung_clock_alias s3c2410_common_aliases[] __initdata = {
141 ALIAS(PCLK_I2C, "s3c2410-i2c.0", "i2c"),
142 ALIAS(PCLK_ADC, NULL, "adc"),
143 ALIAS(PCLK_RTC, NULL, "rtc"),
144 ALIAS(PCLK_PWM, NULL, "timers"),
145 ALIAS(HCLK_LCD, NULL, "lcd"),
146 ALIAS(HCLK_USBD, NULL, "usb-device"),
147 ALIAS(HCLK_USBH, NULL, "usb-host"),
148 ALIAS(UCLK, NULL, "usb-bus-host"),
149 ALIAS(UCLK, NULL, "usb-bus-gadget"),
150 ALIAS(ARMCLK, NULL, "armclk"),
151 ALIAS(UCLK, NULL, "uclk"),
152 ALIAS(HCLK, NULL, "hclk"),
153 ALIAS(MPLL, NULL, "mpll"),
154 ALIAS(FCLK, NULL, "fclk"),
155 ALIAS(PCLK, NULL, "watchdog"),
156 ALIAS(PCLK_SDI, NULL, "sdi"),
157 ALIAS(HCLK_NAND, NULL, "nand"),
158 ALIAS(PCLK_I2S, NULL, "iis"),
159 ALIAS(PCLK_I2C, NULL, "i2c"),
160};
161
162
163
164static struct samsung_pll_rate_table pll_s3c2410_12mhz_tbl[] __initdata = {
165
166
167 PLL_35XX_RATE(270000000, 127, 1, 1),
168 PLL_35XX_RATE(268000000, 126, 1, 1),
169 PLL_35XX_RATE(266000000, 125, 1, 1),
170 PLL_35XX_RATE(226000000, 105, 1, 1),
171 PLL_35XX_RATE(210000000, 132, 2, 1),
172
173 PLL_35XX_RATE(203000000, 161, 3, 1),
174 PLL_35XX_RATE(192000000, 88, 1, 1),
175 PLL_35XX_RATE(186000000, 85, 1, 1),
176 PLL_35XX_RATE(180000000, 82, 1, 1),
177 PLL_35XX_RATE(170000000, 77, 1, 1),
178 PLL_35XX_RATE(158000000, 71, 1, 1),
179 PLL_35XX_RATE(152000000, 68, 1, 1),
180 PLL_35XX_RATE(147000000, 90, 2, 1),
181 PLL_35XX_RATE(135000000, 82, 2, 1),
182 PLL_35XX_RATE(124000000, 116, 1, 2),
183 PLL_35XX_RATE(118000000, 150, 2, 2),
184 PLL_35XX_RATE(113000000, 105, 1, 2),
185 PLL_35XX_RATE(101000000, 127, 2, 2),
186 PLL_35XX_RATE(90000000, 112, 2, 2),
187 PLL_35XX_RATE(85000000, 105, 2, 2),
188 PLL_35XX_RATE(79000000, 71, 1, 2),
189 PLL_35XX_RATE(68000000, 82, 2, 2),
190 PLL_35XX_RATE(56000000, 142, 2, 3),
191 PLL_35XX_RATE(48000000, 120, 2, 3),
192 PLL_35XX_RATE(51000000, 161, 3, 3),
193 PLL_35XX_RATE(45000000, 82, 1, 3),
194 PLL_35XX_RATE(34000000, 82, 2, 3),
195 { },
196};
197
198static struct samsung_pll_clock s3c2410_plls[] __initdata = {
199 [mpll] = PLL(pll_s3c2410_mpll, MPLL, "mpll", "xti",
200 LOCKTIME, MPLLCON, NULL),
201 [upll] = PLL(pll_s3c2410_upll, UPLL, "upll", "xti",
202 LOCKTIME, UPLLCON, NULL),
203};
204
205struct samsung_div_clock s3c2410_dividers[] __initdata = {
206 DIV(HCLK, "hclk", "mpll", CLKDIVN, 1, 1),
207};
208
209struct samsung_fixed_factor_clock s3c2410_ffactor[] __initdata = {
210
211
212
213
214 FFACTOR(ARMCLK, "armclk", "fclk", 1, 1, 0),
215
216
217 FFACTOR(UCLK, "uclk", "upll", 1, 1, 0),
218};
219
220struct samsung_clock_alias s3c2410_aliases[] __initdata = {
221 ALIAS(PCLK_UART0, "s3c2410-uart.0", "uart"),
222 ALIAS(PCLK_UART1, "s3c2410-uart.1", "uart"),
223 ALIAS(PCLK_UART2, "s3c2410-uart.2", "uart"),
224 ALIAS(PCLK_UART0, "s3c2410-uart.0", "clk_uart_baud0"),
225 ALIAS(PCLK_UART1, "s3c2410-uart.1", "clk_uart_baud0"),
226 ALIAS(PCLK_UART2, "s3c2410-uart.2", "clk_uart_baud0"),
227 ALIAS(UCLK, NULL, "clk_uart_baud1"),
228};
229
230
231
232static struct samsung_pll_rate_table pll_s3c244x_12mhz_tbl[] __initdata = {
233
234 PLL_35XX_RATE(400000000, 0x5c, 1, 1),
235 PLL_35XX_RATE(390000000, 0x7a, 2, 1),
236 PLL_35XX_RATE(380000000, 0x57, 1, 1),
237 PLL_35XX_RATE(370000000, 0xb1, 4, 1),
238 PLL_35XX_RATE(360000000, 0x70, 2, 1),
239 PLL_35XX_RATE(350000000, 0xa7, 4, 1),
240 PLL_35XX_RATE(340000000, 0x4d, 1, 1),
241 PLL_35XX_RATE(330000000, 0x66, 2, 1),
242 PLL_35XX_RATE(320000000, 0x98, 4, 1),
243 PLL_35XX_RATE(310000000, 0x93, 4, 1),
244 PLL_35XX_RATE(300000000, 0x75, 3, 1),
245 PLL_35XX_RATE(240000000, 0x70, 1, 2),
246 PLL_35XX_RATE(230000000, 0x6b, 1, 2),
247 PLL_35XX_RATE(220000000, 0x66, 1, 2),
248 PLL_35XX_RATE(210000000, 0x84, 2, 2),
249 PLL_35XX_RATE(200000000, 0x5c, 1, 2),
250 PLL_35XX_RATE(190000000, 0x57, 1, 2),
251 PLL_35XX_RATE(180000000, 0x70, 2, 2),
252 PLL_35XX_RATE(170000000, 0x4d, 1, 2),
253 PLL_35XX_RATE(160000000, 0x98, 4, 2),
254 PLL_35XX_RATE(150000000, 0x75, 3, 2),
255 PLL_35XX_RATE(120000000, 0x70, 1, 3),
256 PLL_35XX_RATE(110000000, 0x66, 1, 3),
257 PLL_35XX_RATE(100000000, 0x5c, 1, 3),
258 PLL_35XX_RATE(90000000, 0x70, 2, 3),
259 PLL_35XX_RATE(80000000, 0x98, 4, 3),
260 PLL_35XX_RATE(75000000, 0x75, 3, 3),
261 { },
262};
263
264static struct samsung_pll_clock s3c244x_common_plls[] __initdata = {
265 [mpll] = PLL(pll_s3c2440_mpll, MPLL, "mpll", "xti",
266 LOCKTIME, MPLLCON, NULL),
267 [upll] = PLL(pll_s3c2410_upll, UPLL, "upll", "xti",
268 LOCKTIME, UPLLCON, NULL),
269};
270
271PNAME(hclk_p) = { "fclk", "div_hclk_2", "div_hclk_4", "div_hclk_3" };
272PNAME(armclk_p) = { "fclk", "hclk" };
273
274struct samsung_mux_clock s3c244x_common_muxes[] __initdata = {
275 MUX(HCLK, "hclk", hclk_p, CLKDIVN, 1, 2),
276 MUX(ARMCLK, "armclk", armclk_p, CAMDIVN, 12, 1),
277};
278
279struct samsung_fixed_factor_clock s3c244x_common_ffactor[] __initdata = {
280 FFACTOR(0, "div_hclk_2", "fclk", 1, 2, 0),
281 FFACTOR(0, "ff_cam", "div_cam", 2, 1, CLK_SET_RATE_PARENT),
282};
283
284static struct clk_div_table div_hclk_4_d[] = {
285 { .val = 0, .div = 4 },
286 { .val = 1, .div = 8 },
287 { },
288};
289
290static struct clk_div_table div_hclk_3_d[] = {
291 { .val = 0, .div = 3 },
292 { .val = 1, .div = 6 },
293 { },
294};
295
296struct samsung_div_clock s3c244x_common_dividers[] __initdata = {
297 DIV(UCLK, "uclk", "upll", CLKDIVN, 3, 1),
298 DIV(0, "div_hclk", "fclk", CLKDIVN, 1, 1),
299 DIV_T(0, "div_hclk_4", "fclk", CAMDIVN, 9, 1, div_hclk_4_d),
300 DIV_T(0, "div_hclk_3", "fclk", CAMDIVN, 8, 1, div_hclk_3_d),
301 DIV(0, "div_cam", "upll", CAMDIVN, 0, 3),
302};
303
304struct samsung_gate_clock s3c244x_common_gates[] __initdata = {
305 GATE(HCLK_CAM, "cam", "hclk", CLKCON, 19, 0, 0),
306};
307
308struct samsung_clock_alias s3c244x_common_aliases[] __initdata = {
309 ALIAS(PCLK_UART0, "s3c2440-uart.0", "uart"),
310 ALIAS(PCLK_UART1, "s3c2440-uart.1", "uart"),
311 ALIAS(PCLK_UART2, "s3c2440-uart.2", "uart"),
312 ALIAS(PCLK_UART0, "s3c2440-uart.0", "clk_uart_baud2"),
313 ALIAS(PCLK_UART1, "s3c2440-uart.1", "clk_uart_baud2"),
314 ALIAS(PCLK_UART2, "s3c2440-uart.2", "clk_uart_baud2"),
315 ALIAS(HCLK_CAM, NULL, "camif"),
316 ALIAS(CAMIF, NULL, "camif-upll"),
317};
318
319
320
321PNAME(s3c2440_camif_p) = { "upll", "ff_cam" };
322
323struct samsung_mux_clock s3c2440_muxes[] __initdata = {
324 MUX(CAMIF, "camif", s3c2440_camif_p, CAMDIVN, 4, 1),
325};
326
327struct samsung_gate_clock s3c2440_gates[] __initdata = {
328 GATE(PCLK_AC97, "ac97", "pclk", CLKCON, 20, 0, 0),
329};
330
331
332
333struct samsung_fixed_factor_clock s3c2442_ffactor[] __initdata = {
334 FFACTOR(0, "upll_3", "upll", 1, 3, 0),
335};
336
337PNAME(s3c2442_camif_p) = { "upll", "ff_cam", "upll", "upll_3" };
338
339struct samsung_mux_clock s3c2442_muxes[] __initdata = {
340 MUX(CAMIF, "camif", s3c2442_camif_p, CAMDIVN, 4, 2),
341};
342
343
344
345
346
347#define XTI 1
348struct samsung_fixed_rate_clock s3c2410_common_frate_clks[] __initdata = {
349 FRATE(XTI, "xti", NULL, CLK_IS_ROOT, 0),
350};
351
352static void __init s3c2410_common_clk_register_fixed_ext(
353 struct samsung_clk_provider *ctx,
354 unsigned long xti_f)
355{
356 struct samsung_clock_alias xti_alias = ALIAS(XTI, NULL, "xtal");
357
358 s3c2410_common_frate_clks[0].fixed_rate = xti_f;
359 samsung_clk_register_fixed_rate(ctx, s3c2410_common_frate_clks,
360 ARRAY_SIZE(s3c2410_common_frate_clks));
361
362 samsung_clk_register_alias(ctx, &xti_alias, 1);
363}
364
365void __init s3c2410_common_clk_init(struct device_node *np, unsigned long xti_f,
366 int current_soc,
367 void __iomem *base)
368{
369 struct samsung_clk_provider *ctx;
370 reg_base = base;
371
372 if (np) {
373 reg_base = of_iomap(np, 0);
374 if (!reg_base)
375 panic("%s: failed to map registers\n", __func__);
376 }
377
378 ctx = samsung_clk_init(np, reg_base, NR_CLKS);
379 if (!ctx)
380 panic("%s: unable to allocate context.\n", __func__);
381
382
383 if (!np)
384 s3c2410_common_clk_register_fixed_ext(ctx, xti_f);
385
386 if (current_soc == S3C2410) {
387 if (_get_rate("xti") == 12 * MHZ) {
388 s3c2410_plls[mpll].rate_table = pll_s3c2410_12mhz_tbl;
389 s3c2410_plls[upll].rate_table = pll_s3c2410_12mhz_tbl;
390 }
391
392
393 samsung_clk_register_pll(ctx, s3c2410_plls,
394 ARRAY_SIZE(s3c2410_plls), reg_base);
395
396 } else {
397 if (_get_rate("xti") == 12 * MHZ) {
398
399
400
401
402 s3c244x_common_plls[mpll].rate_table =
403 pll_s3c244x_12mhz_tbl;
404 s3c244x_common_plls[upll].rate_table =
405 pll_s3c2410_12mhz_tbl;
406 }
407
408
409 samsung_clk_register_pll(ctx, s3c244x_common_plls,
410 ARRAY_SIZE(s3c244x_common_plls), reg_base);
411 }
412
413
414 samsung_clk_register_mux(ctx, s3c2410_common_muxes,
415 ARRAY_SIZE(s3c2410_common_muxes));
416 samsung_clk_register_div(ctx, s3c2410_common_dividers,
417 ARRAY_SIZE(s3c2410_common_dividers));
418 samsung_clk_register_gate(ctx, s3c2410_common_gates,
419 ARRAY_SIZE(s3c2410_common_gates));
420
421 if (current_soc == S3C2440 || current_soc == S3C2442) {
422 samsung_clk_register_div(ctx, s3c244x_common_dividers,
423 ARRAY_SIZE(s3c244x_common_dividers));
424 samsung_clk_register_gate(ctx, s3c244x_common_gates,
425 ARRAY_SIZE(s3c244x_common_gates));
426 samsung_clk_register_mux(ctx, s3c244x_common_muxes,
427 ARRAY_SIZE(s3c244x_common_muxes));
428 samsung_clk_register_fixed_factor(ctx, s3c244x_common_ffactor,
429 ARRAY_SIZE(s3c244x_common_ffactor));
430 }
431
432
433 switch (current_soc) {
434 case S3C2410:
435 samsung_clk_register_div(ctx, s3c2410_dividers,
436 ARRAY_SIZE(s3c2410_dividers));
437 samsung_clk_register_fixed_factor(ctx, s3c2410_ffactor,
438 ARRAY_SIZE(s3c2410_ffactor));
439 samsung_clk_register_alias(ctx, s3c2410_aliases,
440 ARRAY_SIZE(s3c2410_aliases));
441 break;
442 case S3C2440:
443 samsung_clk_register_mux(ctx, s3c2440_muxes,
444 ARRAY_SIZE(s3c2440_muxes));
445 samsung_clk_register_gate(ctx, s3c2440_gates,
446 ARRAY_SIZE(s3c2440_gates));
447 break;
448 case S3C2442:
449 samsung_clk_register_mux(ctx, s3c2442_muxes,
450 ARRAY_SIZE(s3c2442_muxes));
451 samsung_clk_register_fixed_factor(ctx, s3c2442_ffactor,
452 ARRAY_SIZE(s3c2442_ffactor));
453 break;
454 }
455
456
457
458
459
460 samsung_clk_register_alias(ctx, s3c2410_common_aliases,
461 ARRAY_SIZE(s3c2410_common_aliases));
462
463 if (current_soc == S3C2440 || current_soc == S3C2442) {
464 samsung_clk_register_alias(ctx, s3c244x_common_aliases,
465 ARRAY_SIZE(s3c244x_common_aliases));
466 }
467
468 s3c2410_clk_sleep_init();
469
470 samsung_clk_of_add_provider(np, ctx);
471}
472
473static void __init s3c2410_clk_init(struct device_node *np)
474{
475 s3c2410_common_clk_init(np, 0, S3C2410, 0);
476}
477CLK_OF_DECLARE(s3c2410_clk, "samsung,s3c2410-clock", s3c2410_clk_init);
478
479static void __init s3c2440_clk_init(struct device_node *np)
480{
481 s3c2410_common_clk_init(np, 0, S3C2440, 0);
482}
483CLK_OF_DECLARE(s3c2440_clk, "samsung,s3c2440-clock", s3c2440_clk_init);
484
485static void __init s3c2442_clk_init(struct device_node *np)
486{
487 s3c2410_common_clk_init(np, 0, S3C2442, 0);
488}
489CLK_OF_DECLARE(s3c2442_clk, "samsung,s3c2442-clock", s3c2442_clk_init);
490
