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16#include <linux/types.h>
17#include <linux/kernel.h>
18#include <linux/ctype.h>
19#include <linux/edac.h>
20#include <linux/interrupt.h>
21#include <linux/platform_device.h>
22#include <linux/of_platform.h>
23#include <linux/uaccess.h>
24
25#include "edac_core.h"
26#include "edac_module.h"
27
28
29
30#define HB_DDR_ECC_ERR_BASE 0x128
31#define MW_DDR_ECC_ERR_BASE 0x1b4
32
33#define HB_DDR_ECC_OPT 0x00
34#define HB_DDR_ECC_U_ERR_ADDR 0x08
35#define HB_DDR_ECC_U_ERR_STAT 0x0c
36#define HB_DDR_ECC_U_ERR_DATAL 0x10
37#define HB_DDR_ECC_U_ERR_DATAH 0x14
38#define HB_DDR_ECC_C_ERR_ADDR 0x18
39#define HB_DDR_ECC_C_ERR_STAT 0x1c
40#define HB_DDR_ECC_C_ERR_DATAL 0x20
41#define HB_DDR_ECC_C_ERR_DATAH 0x24
42
43#define HB_DDR_ECC_OPT_MODE_MASK 0x3
44#define HB_DDR_ECC_OPT_FWC 0x100
45#define HB_DDR_ECC_OPT_XOR_SHIFT 16
46
47
48
49#define HB_DDR_ECC_INT_BASE 0x180
50#define MW_DDR_ECC_INT_BASE 0x218
51
52#define HB_DDR_ECC_INT_STATUS 0x00
53#define HB_DDR_ECC_INT_ACK 0x04
54
55#define HB_DDR_ECC_INT_STAT_CE 0x8
56#define HB_DDR_ECC_INT_STAT_DOUBLE_CE 0x10
57#define HB_DDR_ECC_INT_STAT_UE 0x20
58#define HB_DDR_ECC_INT_STAT_DOUBLE_UE 0x40
59
60struct hb_mc_drvdata {
61 void __iomem *mc_err_base;
62 void __iomem *mc_int_base;
63};
64
65static irqreturn_t highbank_mc_err_handler(int irq, void *dev_id)
66{
67 struct mem_ctl_info *mci = dev_id;
68 struct hb_mc_drvdata *drvdata = mci->pvt_info;
69 u32 status, err_addr;
70
71
72 status = readl(drvdata->mc_int_base + HB_DDR_ECC_INT_STATUS);
73
74 if (status & HB_DDR_ECC_INT_STAT_UE) {
75 err_addr = readl(drvdata->mc_err_base + HB_DDR_ECC_U_ERR_ADDR);
76 edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
77 err_addr >> PAGE_SHIFT,
78 err_addr & ~PAGE_MASK, 0,
79 0, 0, -1,
80 mci->ctl_name, "");
81 }
82 if (status & HB_DDR_ECC_INT_STAT_CE) {
83 u32 syndrome = readl(drvdata->mc_err_base + HB_DDR_ECC_C_ERR_STAT);
84 syndrome = (syndrome >> 8) & 0xff;
85 err_addr = readl(drvdata->mc_err_base + HB_DDR_ECC_C_ERR_ADDR);
86 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,
87 err_addr >> PAGE_SHIFT,
88 err_addr & ~PAGE_MASK, syndrome,
89 0, 0, -1,
90 mci->ctl_name, "");
91 }
92
93
94 writel(status, drvdata->mc_int_base + HB_DDR_ECC_INT_ACK);
95 return IRQ_HANDLED;
96}
97
98static void highbank_mc_err_inject(struct mem_ctl_info *mci, u8 synd)
99{
100 struct hb_mc_drvdata *pdata = mci->pvt_info;
101 u32 reg;
102
103 reg = readl(pdata->mc_err_base + HB_DDR_ECC_OPT);
104 reg &= HB_DDR_ECC_OPT_MODE_MASK;
105 reg |= (synd << HB_DDR_ECC_OPT_XOR_SHIFT) | HB_DDR_ECC_OPT_FWC;
106 writel(reg, pdata->mc_err_base + HB_DDR_ECC_OPT);
107}
108
109#define to_mci(k) container_of(k, struct mem_ctl_info, dev)
110
111static ssize_t highbank_mc_inject_ctrl(struct device *dev,
112 struct device_attribute *attr, const char *buf, size_t count)
113{
114 struct mem_ctl_info *mci = to_mci(dev);
115 u8 synd;
116
117 if (kstrtou8(buf, 16, &synd))
118 return -EINVAL;
119
120 highbank_mc_err_inject(mci, synd);
121
122 return count;
123}
124
125static DEVICE_ATTR(inject_ctrl, S_IWUSR, NULL, highbank_mc_inject_ctrl);
126
127struct hb_mc_settings {
128 int err_offset;
129 int int_offset;
130};
131
132static struct hb_mc_settings hb_settings = {
133 .err_offset = HB_DDR_ECC_ERR_BASE,
134 .int_offset = HB_DDR_ECC_INT_BASE,
135};
136
137static struct hb_mc_settings mw_settings = {
138 .err_offset = MW_DDR_ECC_ERR_BASE,
139 .int_offset = MW_DDR_ECC_INT_BASE,
140};
141
142static struct of_device_id hb_ddr_ctrl_of_match[] = {
143 { .compatible = "calxeda,hb-ddr-ctrl", .data = &hb_settings },
144 { .compatible = "calxeda,ecx-2000-ddr-ctrl", .data = &mw_settings },
145 {},
146};
147MODULE_DEVICE_TABLE(of, hb_ddr_ctrl_of_match);
148
149static int highbank_mc_probe(struct platform_device *pdev)
150{
151 const struct of_device_id *id;
152 const struct hb_mc_settings *settings;
153 struct edac_mc_layer layers[2];
154 struct mem_ctl_info *mci;
155 struct hb_mc_drvdata *drvdata;
156 struct dimm_info *dimm;
157 struct resource *r;
158 void __iomem *base;
159 u32 control;
160 int irq;
161 int res = 0;
162
163 id = of_match_device(hb_ddr_ctrl_of_match, &pdev->dev);
164 if (!id)
165 return -ENODEV;
166
167 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
168 layers[0].size = 1;
169 layers[0].is_virt_csrow = true;
170 layers[1].type = EDAC_MC_LAYER_CHANNEL;
171 layers[1].size = 1;
172 layers[1].is_virt_csrow = false;
173 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers,
174 sizeof(struct hb_mc_drvdata));
175 if (!mci)
176 return -ENOMEM;
177
178 mci->pdev = &pdev->dev;
179 drvdata = mci->pvt_info;
180 platform_set_drvdata(pdev, mci);
181
182 if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL))
183 return -ENOMEM;
184
185 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
186 if (!r) {
187 dev_err(&pdev->dev, "Unable to get mem resource\n");
188 res = -ENODEV;
189 goto err;
190 }
191
192 if (!devm_request_mem_region(&pdev->dev, r->start,
193 resource_size(r), dev_name(&pdev->dev))) {
194 dev_err(&pdev->dev, "Error while requesting mem region\n");
195 res = -EBUSY;
196 goto err;
197 }
198
199 base = devm_ioremap(&pdev->dev, r->start, resource_size(r));
200 if (!base) {
201 dev_err(&pdev->dev, "Unable to map regs\n");
202 res = -ENOMEM;
203 goto err;
204 }
205
206 settings = id->data;
207 drvdata->mc_err_base = base + settings->err_offset;
208 drvdata->mc_int_base = base + settings->int_offset;
209
210 control = readl(drvdata->mc_err_base + HB_DDR_ECC_OPT) & 0x3;
211 if (!control || (control == 0x2)) {
212 dev_err(&pdev->dev, "No ECC present, or ECC disabled\n");
213 res = -ENODEV;
214 goto err;
215 }
216
217 mci->mtype_cap = MEM_FLAG_DDR3;
218 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
219 mci->edac_cap = EDAC_FLAG_SECDED;
220 mci->mod_name = pdev->dev.driver->name;
221 mci->mod_ver = "1";
222 mci->ctl_name = id->compatible;
223 mci->dev_name = dev_name(&pdev->dev);
224 mci->scrub_mode = SCRUB_SW_SRC;
225
226
227 dimm = *mci->dimms;
228 dimm->nr_pages = (~0UL >> PAGE_SHIFT) + 1;
229 dimm->grain = 8;
230 dimm->dtype = DEV_X8;
231 dimm->mtype = MEM_DDR3;
232 dimm->edac_mode = EDAC_SECDED;
233
234 res = edac_mc_add_mc(mci);
235 if (res < 0)
236 goto err;
237
238 irq = platform_get_irq(pdev, 0);
239 res = devm_request_irq(&pdev->dev, irq, highbank_mc_err_handler,
240 0, dev_name(&pdev->dev), mci);
241 if (res < 0) {
242 dev_err(&pdev->dev, "Unable to request irq %d\n", irq);
243 goto err2;
244 }
245
246 device_create_file(&mci->dev, &dev_attr_inject_ctrl);
247
248 devres_close_group(&pdev->dev, NULL);
249 return 0;
250err2:
251 edac_mc_del_mc(&pdev->dev);
252err:
253 devres_release_group(&pdev->dev, NULL);
254 edac_mc_free(mci);
255 return res;
256}
257
258static int highbank_mc_remove(struct platform_device *pdev)
259{
260 struct mem_ctl_info *mci = platform_get_drvdata(pdev);
261
262 device_remove_file(&mci->dev, &dev_attr_inject_ctrl);
263 edac_mc_del_mc(&pdev->dev);
264 edac_mc_free(mci);
265 return 0;
266}
267
268static struct platform_driver highbank_mc_edac_driver = {
269 .probe = highbank_mc_probe,
270 .remove = highbank_mc_remove,
271 .driver = {
272 .name = "hb_mc_edac",
273 .of_match_table = hb_ddr_ctrl_of_match,
274 },
275};
276
277module_platform_driver(highbank_mc_edac_driver);
278
279MODULE_LICENSE("GPL v2");
280MODULE_AUTHOR("Calxeda, Inc.");
281MODULE_DESCRIPTION("EDAC Driver for Calxeda Highbank");
282
