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25#ifndef __INTEL_DRV_H__
26#define __INTEL_DRV_H__
27
28#include <linux/i2c.h>
29#include <linux/hdmi.h>
30#include <drm/i915_drm.h>
31#include "i915_drv.h"
32#include <drm/drm_crtc.h>
33#include <drm/drm_crtc_helper.h>
34#include <drm/drm_fb_helper.h>
35#include <drm/drm_dp_mst_helper.h>
36
37
38
39
40
41
42
43
44
45#define _wait_for(COND, MS, W) ({ \
46 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1; \
47 int ret__ = 0; \
48 while (!(COND)) { \
49 if (time_after(jiffies, timeout__)) { \
50 if (!(COND)) \
51 ret__ = -ETIMEDOUT; \
52 break; \
53 } \
54 if (W && drm_can_sleep()) { \
55 msleep(W); \
56 } else { \
57 cpu_relax(); \
58 } \
59 } \
60 ret__; \
61})
62
63#define wait_for(COND, MS) _wait_for(COND, MS, 1)
64#define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
65#define wait_for_atomic_us(COND, US) _wait_for((COND), \
66 DIV_ROUND_UP((US), 1000), 0)
67
68#define KHz(x) (1000 * (x))
69#define MHz(x) KHz(1000 * (x))
70
71
72
73
74
75
76
77
78#define MAX_OUTPUTS 6
79
80
81
82#define GEN2_CURSOR_WIDTH 64
83#define GEN2_CURSOR_HEIGHT 64
84#define MAX_CURSOR_WIDTH 256
85#define MAX_CURSOR_HEIGHT 256
86
87#define INTEL_I2C_BUS_DVO 1
88#define INTEL_I2C_BUS_SDVO 2
89
90
91
92#define INTEL_OUTPUT_UNUSED 0
93#define INTEL_OUTPUT_ANALOG 1
94#define INTEL_OUTPUT_DVO 2
95#define INTEL_OUTPUT_SDVO 3
96#define INTEL_OUTPUT_LVDS 4
97#define INTEL_OUTPUT_TVOUT 5
98#define INTEL_OUTPUT_HDMI 6
99#define INTEL_OUTPUT_DISPLAYPORT 7
100#define INTEL_OUTPUT_EDP 8
101#define INTEL_OUTPUT_DSI 9
102#define INTEL_OUTPUT_UNKNOWN 10
103#define INTEL_OUTPUT_DP_MST 11
104
105#define INTEL_DVO_CHIP_NONE 0
106#define INTEL_DVO_CHIP_LVDS 1
107#define INTEL_DVO_CHIP_TMDS 2
108#define INTEL_DVO_CHIP_TVOUT 4
109
110#define INTEL_DSI_VIDEO_MODE 0
111#define INTEL_DSI_COMMAND_MODE 1
112
113struct intel_framebuffer {
114 struct drm_framebuffer base;
115 struct drm_i915_gem_object *obj;
116};
117
118struct intel_fbdev {
119 struct drm_fb_helper helper;
120 struct intel_framebuffer *fb;
121 struct list_head fbdev_list;
122 struct drm_display_mode *our_mode;
123 int preferred_bpp;
124};
125
126struct intel_encoder {
127 struct drm_encoder base;
128
129
130
131
132 struct intel_crtc *new_crtc;
133
134 int type;
135 unsigned int cloneable;
136 bool connectors_active;
137 void (*hot_plug)(struct intel_encoder *);
138 bool (*compute_config)(struct intel_encoder *,
139 struct intel_crtc_config *);
140 void (*pre_pll_enable)(struct intel_encoder *);
141 void (*pre_enable)(struct intel_encoder *);
142 void (*enable)(struct intel_encoder *);
143 void (*mode_set)(struct intel_encoder *intel_encoder);
144 void (*disable)(struct intel_encoder *);
145 void (*post_disable)(struct intel_encoder *);
146
147
148
149 bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
150
151
152
153
154 void (*get_config)(struct intel_encoder *,
155 struct intel_crtc_config *pipe_config);
156
157
158
159
160
161 void (*suspend)(struct intel_encoder *);
162 int crtc_mask;
163 enum hpd_pin hpd_pin;
164};
165
166struct intel_panel {
167 struct drm_display_mode *fixed_mode;
168 struct drm_display_mode *downclock_mode;
169 int fitting_mode;
170
171
172 struct {
173 bool present;
174 u32 level;
175 u32 min;
176 u32 max;
177 bool enabled;
178 bool combination_mode;
179 bool active_low_pwm;
180 struct backlight_device *device;
181 } backlight;
182};
183
184struct intel_connector {
185 struct drm_connector base;
186
187
188
189 struct intel_encoder *encoder;
190
191
192
193
194
195 struct intel_encoder *new_encoder;
196
197
198
199 bool (*get_hw_state)(struct intel_connector *);
200
201
202
203
204
205
206
207 void (*unregister)(struct intel_connector *);
208
209
210 struct intel_panel panel;
211
212
213 struct edid *edid;
214
215
216
217 u8 polled;
218
219 void *port;
220
221 struct intel_dp *mst_port;
222};
223
224typedef struct dpll {
225
226 int n;
227 int m1, m2;
228 int p1, p2;
229
230 int dot;
231 int vco;
232 int m;
233 int p;
234} intel_clock_t;
235
236struct intel_plane_config {
237 bool tiled;
238 int size;
239 u32 base;
240};
241
242struct intel_crtc_config {
243
244
245
246
247
248
249
250
251#define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0)
252#define PIPE_CONFIG_QUIRK_INHERITED_MODE (1<<1)
253 unsigned long quirks;
254
255
256
257
258
259
260 struct drm_display_mode requested_mode;
261
262
263 struct drm_display_mode adjusted_mode;
264
265
266
267
268 int pipe_src_w, pipe_src_h;
269
270
271
272 bool has_pch_encoder;
273
274
275
276 enum transcoder cpu_transcoder;
277
278
279
280
281
282 bool limited_color_range;
283
284
285
286 bool has_dp_encoder;
287
288
289 bool has_hdmi_sink;
290
291
292
293 bool has_audio;
294
295
296
297
298
299 bool dither;
300
301
302 bool clock_set;
303
304
305
306 bool sdvo_tv_clock;
307
308
309
310
311
312
313 bool bw_constrained;
314
315
316
317 struct dpll dpll;
318
319
320 enum intel_dpll_id shared_dpll;
321
322
323 uint32_t ddi_pll_sel;
324
325
326 struct intel_dpll_hw_state dpll_hw_state;
327
328 int pipe_bpp;
329 struct intel_link_m_n dp_m_n;
330
331
332 struct intel_link_m_n dp_m2_n2;
333
334
335
336
337
338
339 int port_clock;
340
341
342 unsigned pixel_multiplier;
343
344
345 struct {
346 u32 control;
347 u32 pgm_ratios;
348 u32 lvds_border_bits;
349 } gmch_pfit;
350
351
352 struct {
353 u32 pos;
354 u32 size;
355 bool enabled;
356 bool force_thru;
357 } pch_pfit;
358
359
360 int fdi_lanes;
361 struct intel_link_m_n fdi_m_n;
362
363 bool ips_enabled;
364
365 bool double_wide;
366
367 bool dp_encoder_is_mst;
368 int pbn;
369};
370
371struct intel_pipe_wm {
372 struct intel_wm_level wm[5];
373 uint32_t linetime;
374 bool fbc_wm_enabled;
375 bool pipe_enabled;
376 bool sprites_enabled;
377 bool sprites_scaled;
378};
379
380struct intel_mmio_flip {
381 u32 seqno;
382 u32 ring_id;
383};
384
385struct intel_crtc {
386 struct drm_crtc base;
387 enum pipe pipe;
388 enum plane plane;
389 u8 lut_r[256], lut_g[256], lut_b[256];
390
391
392
393
394
395 bool active;
396 unsigned long enabled_power_domains;
397 bool primary_enabled;
398 bool lowfreq_avail;
399 struct intel_overlay *overlay;
400 struct intel_unpin_work *unpin_work;
401
402 atomic_t unpin_work_count;
403
404
405
406
407 unsigned long dspaddr_offset;
408
409 struct drm_i915_gem_object *cursor_bo;
410 uint32_t cursor_addr;
411 int16_t cursor_width, cursor_height;
412 uint32_t cursor_cntl;
413 uint32_t cursor_base;
414
415 struct intel_plane_config plane_config;
416 struct intel_crtc_config config;
417 struct intel_crtc_config *new_config;
418 bool new_enabled;
419
420
421 unsigned int reset_counter;
422
423
424 bool cpu_fifo_underrun_disabled;
425 bool pch_fifo_underrun_disabled;
426
427
428 struct {
429
430 struct intel_pipe_wm active;
431 } wm;
432
433 wait_queue_head_t vbl_wait;
434
435 int scanline_offset;
436 struct intel_mmio_flip mmio_flip;
437};
438
439struct intel_plane_wm_parameters {
440 uint32_t horiz_pixels;
441 uint32_t vert_pixels;
442 uint8_t bytes_per_pixel;
443 bool enabled;
444 bool scaled;
445};
446
447struct intel_plane {
448 struct drm_plane base;
449 int plane;
450 enum pipe pipe;
451 struct drm_i915_gem_object *obj;
452 bool can_scale;
453 int max_downscale;
454 int crtc_x, crtc_y;
455 unsigned int crtc_w, crtc_h;
456 uint32_t src_x, src_y;
457 uint32_t src_w, src_h;
458
459
460
461
462
463
464 struct intel_plane_wm_parameters wm;
465
466 void (*update_plane)(struct drm_plane *plane,
467 struct drm_crtc *crtc,
468 struct drm_framebuffer *fb,
469 struct drm_i915_gem_object *obj,
470 int crtc_x, int crtc_y,
471 unsigned int crtc_w, unsigned int crtc_h,
472 uint32_t x, uint32_t y,
473 uint32_t src_w, uint32_t src_h);
474 void (*disable_plane)(struct drm_plane *plane,
475 struct drm_crtc *crtc);
476 int (*update_colorkey)(struct drm_plane *plane,
477 struct drm_intel_sprite_colorkey *key);
478 void (*get_colorkey)(struct drm_plane *plane,
479 struct drm_intel_sprite_colorkey *key);
480};
481
482struct intel_watermark_params {
483 unsigned long fifo_size;
484 unsigned long max_wm;
485 unsigned long default_wm;
486 unsigned long guard_size;
487 unsigned long cacheline_size;
488};
489
490struct cxsr_latency {
491 int is_desktop;
492 int is_ddr3;
493 unsigned long fsb_freq;
494 unsigned long mem_freq;
495 unsigned long display_sr;
496 unsigned long display_hpll_disable;
497 unsigned long cursor_sr;
498 unsigned long cursor_hpll_disable;
499};
500
501#define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
502#define to_intel_connector(x) container_of(x, struct intel_connector, base)
503#define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
504#define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
505#define to_intel_plane(x) container_of(x, struct intel_plane, base)
506#define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
507
508struct intel_hdmi {
509 u32 hdmi_reg;
510 int ddc_bus;
511 uint32_t color_range;
512 bool color_range_auto;
513 bool has_hdmi_sink;
514 bool has_audio;
515 enum hdmi_force_audio force_audio;
516 bool rgb_quant_range_selectable;
517 enum hdmi_picture_aspect aspect_ratio;
518 void (*write_infoframe)(struct drm_encoder *encoder,
519 enum hdmi_infoframe_type type,
520 const void *frame, ssize_t len);
521 void (*set_infoframes)(struct drm_encoder *encoder,
522 bool enable,
523 struct drm_display_mode *adjusted_mode);
524};
525
526struct intel_dp_mst_encoder;
527#define DP_MAX_DOWNSTREAM_PORTS 0x10
528
529
530
531
532
533
534enum edp_drrs_refresh_rate_type {
535 DRRS_HIGH_RR,
536 DRRS_LOW_RR,
537 DRRS_MAX_RR,
538};
539
540struct intel_dp {
541 uint32_t output_reg;
542 uint32_t aux_ch_ctl_reg;
543 uint32_t DP;
544 bool has_audio;
545 enum hdmi_force_audio force_audio;
546 uint32_t color_range;
547 bool color_range_auto;
548 uint8_t link_bw;
549 uint8_t lane_count;
550 uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
551 uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
552 uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
553 struct drm_dp_aux aux;
554 uint8_t train_set[4];
555 int panel_power_up_delay;
556 int panel_power_down_delay;
557 int panel_power_cycle_delay;
558 int backlight_on_delay;
559 int backlight_off_delay;
560 struct delayed_work panel_vdd_work;
561 bool want_panel_vdd;
562 unsigned long last_power_cycle;
563 unsigned long last_power_on;
564 unsigned long last_backlight_off;
565
566 struct notifier_block edp_notifier;
567
568 bool use_tps3;
569 bool can_mst;
570 bool is_mst;
571 int active_mst_links;
572
573 struct intel_connector *attached_connector;
574
575
576 struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
577 struct drm_dp_mst_topology_mgr mst_mgr;
578
579 uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
580
581
582
583
584 uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
585 bool has_aux_irq,
586 int send_bytes,
587 uint32_t aux_clock_divider);
588 struct {
589 enum drrs_support_type type;
590 enum edp_drrs_refresh_rate_type refresh_rate_type;
591 struct mutex mutex;
592 } drrs_state;
593
594};
595
596struct intel_digital_port {
597 struct intel_encoder base;
598 enum port port;
599 u32 saved_port_bits;
600 struct intel_dp dp;
601 struct intel_hdmi hdmi;
602 bool (*hpd_pulse)(struct intel_digital_port *, bool);
603};
604
605struct intel_dp_mst_encoder {
606 struct intel_encoder base;
607 enum pipe pipe;
608 struct intel_digital_port *primary;
609 void *port;
610};
611
612static inline int
613vlv_dport_to_channel(struct intel_digital_port *dport)
614{
615 switch (dport->port) {
616 case PORT_B:
617 case PORT_D:
618 return DPIO_CH0;
619 case PORT_C:
620 return DPIO_CH1;
621 default:
622 BUG();
623 }
624}
625
626static inline int
627vlv_pipe_to_channel(enum pipe pipe)
628{
629 switch (pipe) {
630 case PIPE_A:
631 case PIPE_C:
632 return DPIO_CH0;
633 case PIPE_B:
634 return DPIO_CH1;
635 default:
636 BUG();
637 }
638}
639
640static inline struct drm_crtc *
641intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
642{
643 struct drm_i915_private *dev_priv = dev->dev_private;
644 return dev_priv->pipe_to_crtc_mapping[pipe];
645}
646
647static inline struct drm_crtc *
648intel_get_crtc_for_plane(struct drm_device *dev, int plane)
649{
650 struct drm_i915_private *dev_priv = dev->dev_private;
651 return dev_priv->plane_to_crtc_mapping[plane];
652}
653
654struct intel_unpin_work {
655 struct work_struct work;
656 struct drm_crtc *crtc;
657 struct drm_i915_gem_object *old_fb_obj;
658 struct drm_i915_gem_object *pending_flip_obj;
659 struct drm_pending_vblank_event *event;
660 atomic_t pending;
661#define INTEL_FLIP_INACTIVE 0
662#define INTEL_FLIP_PENDING 1
663#define INTEL_FLIP_COMPLETE 2
664 u32 flip_count;
665 u32 gtt_offset;
666 bool enable_stall_check;
667};
668
669struct intel_set_config {
670 struct drm_encoder **save_connector_encoders;
671 struct drm_crtc **save_encoder_crtcs;
672 bool *save_crtc_enabled;
673
674 bool fb_changed;
675 bool mode_changed;
676};
677
678struct intel_load_detect_pipe {
679 struct drm_framebuffer *release_fb;
680 bool load_detect_temp;
681 int dpms_mode;
682};
683
684static inline struct intel_encoder *
685intel_attached_encoder(struct drm_connector *connector)
686{
687 return to_intel_connector(connector)->encoder;
688}
689
690static inline struct intel_digital_port *
691enc_to_dig_port(struct drm_encoder *encoder)
692{
693 return container_of(encoder, struct intel_digital_port, base.base);
694}
695
696static inline struct intel_dp_mst_encoder *
697enc_to_mst(struct drm_encoder *encoder)
698{
699 return container_of(encoder, struct intel_dp_mst_encoder, base.base);
700}
701
702static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
703{
704 return &enc_to_dig_port(encoder)->dp;
705}
706
707static inline struct intel_digital_port *
708dp_to_dig_port(struct intel_dp *intel_dp)
709{
710 return container_of(intel_dp, struct intel_digital_port, dp);
711}
712
713static inline struct intel_digital_port *
714hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
715{
716 return container_of(intel_hdmi, struct intel_digital_port, hdmi);
717}
718
719
720
721bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
722 enum pipe pipe, bool enable);
723bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev,
724 enum transcoder pch_transcoder,
725 bool enable);
726void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
727void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
728void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
729void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
730void gen8_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
731void gen8_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
732void intel_runtime_pm_disable_interrupts(struct drm_device *dev);
733void intel_runtime_pm_restore_interrupts(struct drm_device *dev);
734static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
735{
736
737
738
739
740 return !dev_priv->pm._irqs_disabled;
741}
742
743int intel_get_crtc_scanline(struct intel_crtc *crtc);
744void i9xx_check_fifo_underruns(struct drm_device *dev);
745void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv);
746
747
748void intel_crt_init(struct drm_device *dev);
749
750
751
752void intel_prepare_ddi(struct drm_device *dev);
753void hsw_fdi_link_train(struct drm_crtc *crtc);
754void intel_ddi_init(struct drm_device *dev, enum port port);
755enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
756bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
757int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv);
758void intel_ddi_pll_init(struct drm_device *dev);
759void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
760void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
761 enum transcoder cpu_transcoder);
762void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
763void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
764bool intel_ddi_pll_select(struct intel_crtc *crtc);
765void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
766void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder);
767bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
768void intel_ddi_fdi_disable(struct drm_crtc *crtc);
769void intel_ddi_get_config(struct intel_encoder *encoder,
770 struct intel_crtc_config *pipe_config);
771
772void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder);
773void intel_ddi_clock_get(struct intel_encoder *encoder,
774 struct intel_crtc_config *pipe_config);
775void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state);
776
777
778const char *intel_output_name(int output);
779bool intel_has_pending_fb_unpin(struct drm_device *dev);
780int intel_pch_rawclk(struct drm_device *dev);
781void intel_mark_busy(struct drm_device *dev);
782void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj,
783 struct intel_engine_cs *ring);
784void intel_frontbuffer_flip_prepare(struct drm_device *dev,
785 unsigned frontbuffer_bits);
786void intel_frontbuffer_flip_complete(struct drm_device *dev,
787 unsigned frontbuffer_bits);
788void intel_frontbuffer_flush(struct drm_device *dev,
789 unsigned frontbuffer_bits);
790
791
792
793
794
795
796
797
798
799
800
801static inline
802void intel_frontbuffer_flip(struct drm_device *dev,
803 unsigned frontbuffer_bits)
804{
805 intel_frontbuffer_flush(dev, frontbuffer_bits);
806}
807
808void intel_fb_obj_flush(struct drm_i915_gem_object *obj, bool retire);
809void intel_mark_idle(struct drm_device *dev);
810void intel_crtc_restore_mode(struct drm_crtc *crtc);
811void intel_crtc_control(struct drm_crtc *crtc, bool enable);
812void intel_crtc_update_dpms(struct drm_crtc *crtc);
813void intel_encoder_destroy(struct drm_encoder *encoder);
814void intel_connector_dpms(struct drm_connector *, int mode);
815bool intel_connector_get_hw_state(struct intel_connector *connector);
816void intel_modeset_check_state(struct drm_device *dev);
817bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
818 struct intel_digital_port *port);
819void intel_connector_attach_encoder(struct intel_connector *connector,
820 struct intel_encoder *encoder);
821struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
822struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
823 struct drm_crtc *crtc);
824enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
825int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
826 struct drm_file *file_priv);
827enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
828 enum pipe pipe);
829void intel_wait_for_vblank(struct drm_device *dev, int pipe);
830void intel_wait_for_pipe_off(struct drm_device *dev, int pipe);
831int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
832void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
833 struct intel_digital_port *dport);
834bool intel_get_load_detect_pipe(struct drm_connector *connector,
835 struct drm_display_mode *mode,
836 struct intel_load_detect_pipe *old,
837 struct drm_modeset_acquire_ctx *ctx);
838void intel_release_load_detect_pipe(struct drm_connector *connector,
839 struct intel_load_detect_pipe *old);
840int intel_pin_and_fence_fb_obj(struct drm_device *dev,
841 struct drm_i915_gem_object *obj,
842 struct intel_engine_cs *pipelined);
843void intel_unpin_fb_obj(struct drm_i915_gem_object *obj);
844struct drm_framebuffer *
845__intel_framebuffer_create(struct drm_device *dev,
846 struct drm_mode_fb_cmd2 *mode_cmd,
847 struct drm_i915_gem_object *obj);
848void intel_prepare_page_flip(struct drm_device *dev, int plane);
849void intel_finish_page_flip(struct drm_device *dev, int pipe);
850void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
851
852
853struct intel_shared_dpll *intel_crtc_to_shared_dpll(struct intel_crtc *crtc);
854void assert_shared_dpll(struct drm_i915_private *dev_priv,
855 struct intel_shared_dpll *pll,
856 bool state);
857#define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
858#define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
859struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc);
860void intel_put_shared_dpll(struct intel_crtc *crtc);
861
862
863void assert_pll(struct drm_i915_private *dev_priv,
864 enum pipe pipe, bool state);
865#define assert_pll_enabled(d, p) assert_pll(d, p, true)
866#define assert_pll_disabled(d, p) assert_pll(d, p, false)
867void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
868 enum pipe pipe, bool state);
869#define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
870#define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
871void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
872#define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
873#define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
874void intel_write_eld(struct drm_encoder *encoder,
875 struct drm_display_mode *mode);
876unsigned long intel_gen4_compute_page_offset(int *x, int *y,
877 unsigned int tiling_mode,
878 unsigned int bpp,
879 unsigned int pitch);
880void intel_display_handle_reset(struct drm_device *dev);
881void hsw_enable_pc8(struct drm_i915_private *dev_priv);
882void hsw_disable_pc8(struct drm_i915_private *dev_priv);
883void intel_dp_get_m_n(struct intel_crtc *crtc,
884 struct intel_crtc_config *pipe_config);
885int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
886void
887ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
888 int dotclock);
889bool intel_crtc_active(struct drm_crtc *crtc);
890void hsw_enable_ips(struct intel_crtc *crtc);
891void hsw_disable_ips(struct intel_crtc *crtc);
892void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);
893enum intel_display_power_domain
894intel_display_port_power_domain(struct intel_encoder *intel_encoder);
895void intel_mode_from_pipe_config(struct drm_display_mode *mode,
896 struct intel_crtc_config *pipe_config);
897int intel_format_to_fourcc(int format);
898void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc);
899
900
901
902void intel_dp_init(struct drm_device *dev, int output_reg, enum port port);
903bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
904 struct intel_connector *intel_connector);
905void intel_dp_start_link_train(struct intel_dp *intel_dp);
906void intel_dp_complete_link_train(struct intel_dp *intel_dp);
907void intel_dp_stop_link_train(struct intel_dp *intel_dp);
908void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
909void intel_dp_encoder_destroy(struct drm_encoder *encoder);
910void intel_dp_check_link_status(struct intel_dp *intel_dp);
911int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc);
912bool intel_dp_compute_config(struct intel_encoder *encoder,
913 struct intel_crtc_config *pipe_config);
914bool intel_dp_is_edp(struct drm_device *dev, enum port port);
915bool intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
916 bool long_hpd);
917void intel_edp_backlight_on(struct intel_dp *intel_dp);
918void intel_edp_backlight_off(struct intel_dp *intel_dp);
919void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
920void intel_edp_panel_vdd_sanitize(struct intel_encoder *intel_encoder);
921void intel_edp_panel_on(struct intel_dp *intel_dp);
922void intel_edp_panel_off(struct intel_dp *intel_dp);
923void intel_edp_psr_enable(struct intel_dp *intel_dp);
924void intel_edp_psr_disable(struct intel_dp *intel_dp);
925void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate);
926void intel_edp_psr_invalidate(struct drm_device *dev,
927 unsigned frontbuffer_bits);
928void intel_edp_psr_flush(struct drm_device *dev,
929 unsigned frontbuffer_bits);
930void intel_edp_psr_init(struct drm_device *dev);
931
932int intel_dp_handle_hpd_irq(struct intel_digital_port *digport, bool long_hpd);
933void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector);
934void intel_dp_mst_suspend(struct drm_device *dev);
935void intel_dp_mst_resume(struct drm_device *dev);
936int intel_dp_max_link_bw(struct intel_dp *intel_dp);
937void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
938
939int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
940void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
941
942void intel_dsi_init(struct drm_device *dev);
943
944
945
946void intel_dvo_init(struct drm_device *dev);
947
948
949
950#ifdef CONFIG_DRM_I915_FBDEV
951extern int intel_fbdev_init(struct drm_device *dev);
952extern void intel_fbdev_initial_config(struct drm_device *dev);
953extern void intel_fbdev_fini(struct drm_device *dev);
954extern void intel_fbdev_set_suspend(struct drm_device *dev, int state);
955extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
956extern void intel_fbdev_restore_mode(struct drm_device *dev);
957#else
958static inline int intel_fbdev_init(struct drm_device *dev)
959{
960 return 0;
961}
962
963static inline void intel_fbdev_initial_config(struct drm_device *dev)
964{
965}
966
967static inline void intel_fbdev_fini(struct drm_device *dev)
968{
969}
970
971static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state)
972{
973}
974
975static inline void intel_fbdev_restore_mode(struct drm_device *dev)
976{
977}
978#endif
979
980
981void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port);
982void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
983 struct intel_connector *intel_connector);
984struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
985bool intel_hdmi_compute_config(struct intel_encoder *encoder,
986 struct intel_crtc_config *pipe_config);
987
988
989
990void intel_lvds_init(struct drm_device *dev);
991bool intel_is_dual_link_lvds(struct drm_device *dev);
992
993
994
995int intel_connector_update_modes(struct drm_connector *connector,
996 struct edid *edid);
997int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
998void intel_attach_force_audio_property(struct drm_connector *connector);
999void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
1000
1001
1002
1003void intel_setup_overlay(struct drm_device *dev);
1004void intel_cleanup_overlay(struct drm_device *dev);
1005int intel_overlay_switch_off(struct intel_overlay *overlay);
1006int intel_overlay_put_image(struct drm_device *dev, void *data,
1007 struct drm_file *file_priv);
1008int intel_overlay_attrs(struct drm_device *dev, void *data,
1009 struct drm_file *file_priv);
1010
1011
1012
1013int intel_panel_init(struct intel_panel *panel,
1014 struct drm_display_mode *fixed_mode,
1015 struct drm_display_mode *downclock_mode);
1016void intel_panel_fini(struct intel_panel *panel);
1017void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
1018 struct drm_display_mode *adjusted_mode);
1019void intel_pch_panel_fitting(struct intel_crtc *crtc,
1020 struct intel_crtc_config *pipe_config,
1021 int fitting_mode);
1022void intel_gmch_panel_fitting(struct intel_crtc *crtc,
1023 struct intel_crtc_config *pipe_config,
1024 int fitting_mode);
1025void intel_panel_set_backlight_acpi(struct intel_connector *connector,
1026 u32 level, u32 max);
1027int intel_panel_setup_backlight(struct drm_connector *connector);
1028void intel_panel_enable_backlight(struct intel_connector *connector);
1029void intel_panel_disable_backlight(struct intel_connector *connector);
1030void intel_panel_destroy_backlight(struct drm_connector *connector);
1031void intel_panel_init_backlight_funcs(struct drm_device *dev);
1032enum drm_connector_status intel_panel_detect(struct drm_device *dev);
1033extern struct drm_display_mode *intel_find_panel_downclock(
1034 struct drm_device *dev,
1035 struct drm_display_mode *fixed_mode,
1036 struct drm_connector *connector);
1037
1038
1039void intel_init_clock_gating(struct drm_device *dev);
1040void intel_suspend_hw(struct drm_device *dev);
1041int ilk_wm_max_level(const struct drm_device *dev);
1042void intel_update_watermarks(struct drm_crtc *crtc);
1043void intel_update_sprite_watermarks(struct drm_plane *plane,
1044 struct drm_crtc *crtc,
1045 uint32_t sprite_width,
1046 uint32_t sprite_height,
1047 int pixel_size,
1048 bool enabled, bool scaled);
1049void intel_init_pm(struct drm_device *dev);
1050void intel_pm_setup(struct drm_device *dev);
1051bool intel_fbc_enabled(struct drm_device *dev);
1052void intel_update_fbc(struct drm_device *dev);
1053void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
1054void intel_gpu_ips_teardown(void);
1055int intel_power_domains_init(struct drm_i915_private *);
1056void intel_power_domains_remove(struct drm_i915_private *);
1057bool intel_display_power_enabled(struct drm_i915_private *dev_priv,
1058 enum intel_display_power_domain domain);
1059bool intel_display_power_enabled_unlocked(struct drm_i915_private *dev_priv,
1060 enum intel_display_power_domain domain);
1061void intel_display_power_get(struct drm_i915_private *dev_priv,
1062 enum intel_display_power_domain domain);
1063void intel_display_power_put(struct drm_i915_private *dev_priv,
1064 enum intel_display_power_domain domain);
1065void intel_power_domains_init_hw(struct drm_i915_private *dev_priv);
1066void intel_init_gt_powersave(struct drm_device *dev);
1067void intel_cleanup_gt_powersave(struct drm_device *dev);
1068void intel_enable_gt_powersave(struct drm_device *dev);
1069void intel_disable_gt_powersave(struct drm_device *dev);
1070void intel_suspend_gt_powersave(struct drm_device *dev);
1071void intel_reset_gt_powersave(struct drm_device *dev);
1072void ironlake_teardown_rc6(struct drm_device *dev);
1073void gen6_update_ring_freq(struct drm_device *dev);
1074void gen6_rps_idle(struct drm_i915_private *dev_priv);
1075void gen6_rps_boost(struct drm_i915_private *dev_priv);
1076void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv);
1077void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv);
1078void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
1079void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
1080void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
1081void intel_init_runtime_pm(struct drm_i915_private *dev_priv);
1082void intel_fini_runtime_pm(struct drm_i915_private *dev_priv);
1083void ilk_wm_get_hw_state(struct drm_device *dev);
1084
1085
1086
1087bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob);
1088
1089
1090
1091int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
1092void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
1093 enum plane plane);
1094void intel_plane_restore(struct drm_plane *plane);
1095void intel_plane_disable(struct drm_plane *plane);
1096int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
1097 struct drm_file *file_priv);
1098int intel_sprite_get_colorkey(struct drm_device *dev, void *data,
1099 struct drm_file *file_priv);
1100
1101
1102
1103void intel_tv_init(struct drm_device *dev);
1104
1105#endif
1106