LXR linux/drivers/gpu/drm/nouveau/core/engine/disp/dport.c

   1/*
   2 * Copyright 2013 Red Hat Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 * Authors: Ben Skeggs
  23 */
  24
  25#include <subdev/bios.h>
  26#include <subdev/bios/dcb.h>
  27#include <subdev/bios/dp.h>
  28#include <subdev/bios/init.h>
  29#include <subdev/i2c.h>
  30
  31#include <engine/disp.h>
  32
  33#include <nvif/class.h>
  34
  35#include "dport.h"
  36#include "outpdp.h"
  37
  38/******************************************************************************
  39 * link training
  40 *****************************************************************************/
  41struct dp_state {
  42        struct nvkm_output_dp *outp;
  43        int link_nr;
  44        u32 link_bw;
  45        u8  stat[6];
  46        u8  conf[4];
  47        bool pc2;
  48        u8  pc2stat;
  49        u8  pc2conf[2];
  50};
  51
  52static int
  53dp_set_link_config(struct dp_state *dp)
  54{
  55        struct nvkm_output_dp_impl *impl = (void *)nv_oclass(dp->outp);
  56        struct nvkm_output_dp *outp = dp->outp;
  57        struct nouveau_disp *disp = nouveau_disp(outp);
  58        struct nouveau_bios *bios = nouveau_bios(disp);
  59        struct nvbios_init init = {
  60                .subdev = nv_subdev(disp),
  61                .bios = bios,
  62                .offset = 0x0000,
  63                .outp = &outp->base.info,
  64                .crtc = -1,
  65                .execute = 1,
  66        };
  67        u32 lnkcmp;
  68        u8 sink[2];
  69        int ret;
  70
  71        DBG("%d lanes at %d KB/s\n", dp->link_nr, dp->link_bw);
  72
  73        /* set desired link configuration on the source */
  74        if ((lnkcmp = dp->outp->info.lnkcmp)) {
  75                if (outp->version < 0x30) {
  76                        while ((dp->link_bw / 10) < nv_ro16(bios, lnkcmp))
  77                                lnkcmp += 4;
  78                        init.offset = nv_ro16(bios, lnkcmp + 2);
  79                } else {
  80                        while ((dp->link_bw / 27000) < nv_ro08(bios, lnkcmp))
  81                                lnkcmp += 3;
  82                        init.offset = nv_ro16(bios, lnkcmp + 1);
  83                }
  84
  85                nvbios_exec(&init);
  86        }
  87
  88        ret = impl->lnk_ctl(outp, dp->link_nr, dp->link_bw / 27000,
  89                            outp->dpcd[DPCD_RC02] &
  90                                       DPCD_RC02_ENHANCED_FRAME_CAP);
  91        if (ret) {
  92                if (ret < 0)
  93                        ERR("lnk_ctl failed with %d\n", ret);
  94                return ret;
  95        }
  96
  97        impl->lnk_pwr(outp, dp->link_nr);
  98
  99        /* set desired link configuration on the sink */
 100        sink[0] = dp->link_bw / 27000;
 101        sink[1] = dp->link_nr;
 102        if (outp->dpcd[DPCD_RC02] & DPCD_RC02_ENHANCED_FRAME_CAP)
 103                sink[1] |= DPCD_LC01_ENHANCED_FRAME_EN;
 104
 105        return nv_wraux(outp->base.edid, DPCD_LC00_LINK_BW_SET, sink, 2);
 106}
 107
 108static void
 109dp_set_training_pattern(struct dp_state *dp, u8 pattern)
 110{
 111        struct nvkm_output_dp_impl *impl = (void *)nv_oclass(dp->outp);
 112        struct nvkm_output_dp *outp = dp->outp;
 113        u8 sink_tp;
 114
 115        DBG("training pattern %d\n", pattern);
 116        impl->pattern(outp, pattern);
 117
 118        nv_rdaux(outp->base.edid, DPCD_LC02, &sink_tp, 1);
 119        sink_tp &= ~DPCD_LC02_TRAINING_PATTERN_SET;
 120        sink_tp |= pattern;
 121        nv_wraux(outp->base.edid, DPCD_LC02, &sink_tp, 1);
 122}
 123
 124static int
 125dp_link_train_commit(struct dp_state *dp, bool pc)
 126{
 127        struct nvkm_output_dp_impl *impl = (void *)nv_oclass(dp->outp);
 128        struct nvkm_output_dp *outp = dp->outp;
 129        int ret, i;
 130
 131        for (i = 0; i < dp->link_nr; i++) {
 132                u8 lane = (dp->stat[4 + (i >> 1)] >> ((i & 1) * 4)) & 0xf;
 133                u8 lpc2 = (dp->pc2stat >> (i * 2)) & 0x3;
 134                u8 lpre = (lane & 0x0c) >> 2;
 135                u8 lvsw = (lane & 0x03) >> 0;
 136                u8 hivs = 3 - lpre;
 137                u8 hipe = 3;
 138                u8 hipc = 3;
 139
 140                if (lpc2 >= hipc)
 141                        lpc2 = hipc | DPCD_LC0F_LANE0_MAX_POST_CURSOR2_REACHED;
 142                if (lpre >= hipe) {
 143                        lpre = hipe | DPCD_LC03_MAX_SWING_REACHED; /* yes. */
 144                        lvsw = hivs = 3 - (lpre & 3);
 145                } else
 146                if (lvsw >= hivs) {
 147                        lvsw = hivs | DPCD_LC03_MAX_SWING_REACHED;
 148                }
 149
 150                dp->conf[i] = (lpre << 3) | lvsw;
 151                dp->pc2conf[i >> 1] |= lpc2 << ((i & 1) * 4);
 152
 153                DBG("config lane %d %02x %02x\n", i, dp->conf[i], lpc2);
 154                impl->drv_ctl(outp, i, lvsw & 3, lpre & 3, lpc2 & 3);
 155        }
 156
 157        ret = nv_wraux(outp->base.edid, DPCD_LC03(0), dp->conf, 4);
 158        if (ret)
 159                return ret;
 160
 161        if (pc) {
 162                ret = nv_wraux(outp->base.edid, DPCD_LC0F, dp->pc2conf, 2);
 163                if (ret)
 164                        return ret;
 165        }
 166
 167        return 0;
 168}
 169
 170static int
 171dp_link_train_update(struct dp_state *dp, bool pc, u32 delay)
 172{
 173        struct nvkm_output_dp *outp = dp->outp;
 174        int ret;
 175
 176        if (outp->dpcd[DPCD_RC0E_AUX_RD_INTERVAL])
 177                mdelay(outp->dpcd[DPCD_RC0E_AUX_RD_INTERVAL] * 4);
 178        else
 179                udelay(delay);
 180
 181        ret = nv_rdaux(outp->base.edid, DPCD_LS02, dp->stat, 6);
 182        if (ret)
 183                return ret;
 184
 185        if (pc) {
 186                ret = nv_rdaux(outp->base.edid, DPCD_LS0C, &dp->pc2stat, 1);
 187                if (ret)
 188                        dp->pc2stat = 0x00;
 189                DBG("status %6ph pc2 %02x\n", dp->stat, dp->pc2stat);
 190        } else {
 191                DBG("status %6ph\n", dp->stat);
 192        }
 193
 194        return 0;
 195}
 196
 197static int
 198dp_link_train_cr(struct dp_state *dp)
 199{
 200        bool cr_done = false, abort = false;
 201        int voltage = dp->conf[0] & DPCD_LC03_VOLTAGE_SWING_SET;
 202        int tries = 0, i;
 203
 204        dp_set_training_pattern(dp, 1);
 205
 206        do {
 207                if (dp_link_train_commit(dp, false) ||
 208                    dp_link_train_update(dp, false, 100))
 209                        break;
 210
 211                cr_done = true;
 212                for (i = 0; i < dp->link_nr; i++) {
 213                        u8 lane = (dp->stat[i >> 1] >> ((i & 1) * 4)) & 0xf;
 214                        if (!(lane & DPCD_LS02_LANE0_CR_DONE)) {
 215                                cr_done = false;
 216                                if (dp->conf[i] & DPCD_LC03_MAX_SWING_REACHED)
 217                                        abort = true;
 218                                break;
 219                        }
 220                }
 221
 222                if ((dp->conf[0] & DPCD_LC03_VOLTAGE_SWING_SET) != voltage) {
 223                        voltage = dp->conf[0] & DPCD_LC03_VOLTAGE_SWING_SET;
 224                        tries = 0;
 225                }
 226        } while (!cr_done && !abort && ++tries < 5);
 227
 228        return cr_done ? 0 : -1;
 229}
 230
 231static int
 232dp_link_train_eq(struct dp_state *dp)
 233{
 234        struct nvkm_output_dp *outp = dp->outp;
 235        bool eq_done = false, cr_done = true;
 236        int tries = 0, i;
 237
 238        if (outp->dpcd[2] & DPCD_RC02_TPS3_SUPPORTED)
 239                dp_set_training_pattern(dp, 3);
 240        else
 241                dp_set_training_pattern(dp, 2);
 242
 243        do {
 244                if ((tries &&
 245                    dp_link_train_commit(dp, dp->pc2)) ||
 246                    dp_link_train_update(dp, dp->pc2, 400))
 247                        break;
 248
 249                eq_done = !!(dp->stat[2] & DPCD_LS04_INTERLANE_ALIGN_DONE);
 250                for (i = 0; i < dp->link_nr && eq_done; i++) {
 251                        u8 lane = (dp->stat[i >> 1] >> ((i & 1) * 4)) & 0xf;
 252                        if (!(lane & DPCD_LS02_LANE0_CR_DONE))
 253                                cr_done = false;
 254                        if (!(lane & DPCD_LS02_LANE0_CHANNEL_EQ_DONE) ||
 255                            !(lane & DPCD_LS02_LANE0_SYMBOL_LOCKED))
 256                                eq_done = false;
 257                }
 258        } while (!eq_done && cr_done && ++tries <= 5);
 259
 260        return eq_done ? 0 : -1;
 261}
 262
 263static void
 264dp_link_train_init(struct dp_state *dp, bool spread)
 265{
 266        struct nvkm_output_dp *outp = dp->outp;
 267        struct nouveau_disp *disp = nouveau_disp(outp);
 268        struct nouveau_bios *bios = nouveau_bios(disp);
 269        struct nvbios_init init = {
 270                .subdev = nv_subdev(disp),
 271                .bios = bios,
 272                .outp = &outp->base.info,
 273                .crtc = -1,
 274                .execute = 1,
 275        };
 276
 277        /* set desired spread */
 278        if (spread)
 279                init.offset = outp->info.script[2];
 280        else
 281                init.offset = outp->info.script[3];
 282        nvbios_exec(&init);
 283
 284        /* pre-train script */
 285        init.offset = outp->info.script[0];
 286        nvbios_exec(&init);
 287}
 288
 289static void
 290dp_link_train_fini(struct dp_state *dp)
 291{
 292        struct nvkm_output_dp *outp = dp->outp;
 293        struct nouveau_disp *disp = nouveau_disp(outp);
 294        struct nouveau_bios *bios = nouveau_bios(disp);
 295        struct nvbios_init init = {
 296                .subdev = nv_subdev(disp),
 297                .bios = bios,
 298                .outp = &outp->base.info,
 299                .crtc = -1,
 300                .execute = 1,
 301        };
 302
 303        /* post-train script */
 304        init.offset = outp->info.script[1],
 305        nvbios_exec(&init);
 306}
 307
 308static const struct dp_rates {
 309        u32 rate;
 310        u8  bw;
 311        u8  nr;
 312} nouveau_dp_rates[] = {
 313        { 2160000, 0x14, 4 },
 314        { 1080000, 0x0a, 4 },
 315        { 1080000, 0x14, 2 },
 316        {  648000, 0x06, 4 },
 317        {  540000, 0x0a, 2 },
 318        {  540000, 0x14, 1 },
 319        {  324000, 0x06, 2 },
 320        {  270000, 0x0a, 1 },
 321        {  162000, 0x06, 1 },
 322        {}
 323};
 324
 325void
 326nouveau_dp_train(struct work_struct *w)
 327{
 328        struct nvkm_output_dp *outp = container_of(w, typeof(*outp), lt.work);
 329        struct nouveau_disp *disp = nouveau_disp(outp);
 330        const struct dp_rates *cfg = nouveau_dp_rates;
 331        struct dp_state _dp = {
 332                .outp = outp,
 333        }, *dp = &_dp;
 334        u32 datarate = 0;
 335        int ret;
 336
 337        /* bring capabilities within encoder limits */
 338        if (nv_mclass(disp) < GF110_DISP)
 339                outp->dpcd[2] &= ~DPCD_RC02_TPS3_SUPPORTED;
 340        if ((outp->dpcd[2] & 0x1f) > outp->base.info.dpconf.link_nr) {
 341                outp->dpcd[2] &= ~DPCD_RC02_MAX_LANE_COUNT;
 342                outp->dpcd[2] |= outp->base.info.dpconf.link_nr;
 343        }
 344        if (outp->dpcd[1] > outp->base.info.dpconf.link_bw)
 345                outp->dpcd[1] = outp->base.info.dpconf.link_bw;
 346        dp->pc2 = outp->dpcd[2] & DPCD_RC02_TPS3_SUPPORTED;
 347
 348        /* restrict link config to the lowest required rate, if requested */
 349        if (datarate) {
 350                datarate = (datarate / 8) * 10; /* 8B/10B coding overhead */
 351                while (cfg[1].rate >= datarate)
 352                        cfg++;
 353        }
 354        cfg--;
 355
 356        /* disable link interrupt handling during link training */
 357        nvkm_notify_put(&outp->irq);
 358
 359        /* enable down-spreading and execute pre-train script from vbios */
 360        dp_link_train_init(dp, outp->dpcd[3] & 0x01);
 361
 362        while (ret = -EIO, (++cfg)->rate) {
 363                /* select next configuration supported by encoder and sink */
 364                while (cfg->nr > (outp->dpcd[2] & DPCD_RC02_MAX_LANE_COUNT) ||
 365                       cfg->bw > (outp->dpcd[DPCD_RC01_MAX_LINK_RATE]))
 366                        cfg++;
 367                dp->link_bw = cfg->bw * 27000;
 368                dp->link_nr = cfg->nr;
 369
 370                /* program selected link configuration */
 371                ret = dp_set_link_config(dp);
 372                if (ret == 0) {
 373                        /* attempt to train the link at this configuration */
 374                        memset(dp->stat, 0x00, sizeof(dp->stat));
 375                        if (!dp_link_train_cr(dp) &&
 376                            !dp_link_train_eq(dp))
 377                                break;
 378                } else
 379                if (ret) {
 380                        /* dp_set_link_config() handled training, or
 381                         * we failed to communicate with the sink.
 382                         */
 383                        break;
 384                }
 385        }
 386
 387        /* finish link training and execute post-train script from vbios */
 388        dp_set_training_pattern(dp, 0);
 389        if (ret < 0)
 390                ERR("link training failed\n");
 391
 392        dp_link_train_fini(dp);
 393
 394        /* signal completion and enable link interrupt handling */
 395        DBG("training complete\n");
 396        atomic_set(&outp->lt.done, 1);
 397        wake_up(&outp->lt.wait);
 398        nvkm_notify_get(&outp->irq);
 399}
 400