1#include <core/engine.h>
2#include <core/device.h>
3
4#include <subdev/bios.h>
5#include <subdev/bios/bmp.h>
6#include <subdev/bios/bit.h>
7#include <subdev/bios/conn.h>
8#include <subdev/bios/dcb.h>
9#include <subdev/bios/dp.h>
10#include <subdev/bios/gpio.h>
11#include <subdev/bios/init.h>
12#include <subdev/bios/ramcfg.h>
13#include <subdev/devinit.h>
14#include <subdev/i2c.h>
15#include <subdev/vga.h>
16#include <subdev/gpio.h>
17
18#define bioslog(lvl, fmt, args...) do { \
19 nv_printk(init->bios, lvl, "0x%04x[%c]: "fmt, init->offset, \
20 init_exec(init) ? '0' + (init->nested - 1) : ' ', ##args); \
21} while(0)
22#define cont(fmt, args...) do { \
23 if (nv_subdev(init->bios)->debug >= NV_DBG_TRACE) \
24 printk(fmt, ##args); \
25} while(0)
26#define trace(fmt, args...) bioslog(TRACE, fmt, ##args)
27#define warn(fmt, args...) bioslog(WARN, fmt, ##args)
28#define error(fmt, args...) bioslog(ERROR, fmt, ##args)
29
30
31
32
33
34static inline bool
35init_exec(struct nvbios_init *init)
36{
37 return (init->execute == 1) || ((init->execute & 5) == 5);
38}
39
40static inline void
41init_exec_set(struct nvbios_init *init, bool exec)
42{
43 if (exec) init->execute &= 0xfd;
44 else init->execute |= 0x02;
45}
46
47static inline void
48init_exec_inv(struct nvbios_init *init)
49{
50 init->execute ^= 0x02;
51}
52
53static inline void
54init_exec_force(struct nvbios_init *init, bool exec)
55{
56 if (exec) init->execute |= 0x04;
57 else init->execute &= 0xfb;
58}
59
60
61
62
63
64static inline int
65init_or(struct nvbios_init *init)
66{
67 if (init_exec(init)) {
68 if (init->outp)
69 return ffs(init->outp->or) - 1;
70 error("script needs OR!!\n");
71 }
72 return 0;
73}
74
75static inline int
76init_link(struct nvbios_init *init)
77{
78 if (init_exec(init)) {
79 if (init->outp)
80 return !(init->outp->sorconf.link & 1);
81 error("script needs OR link\n");
82 }
83 return 0;
84}
85
86static inline int
87init_crtc(struct nvbios_init *init)
88{
89 if (init_exec(init)) {
90 if (init->crtc >= 0)
91 return init->crtc;
92 error("script needs crtc\n");
93 }
94 return 0;
95}
96
97static u8
98init_conn(struct nvbios_init *init)
99{
100 struct nouveau_bios *bios = init->bios;
101 struct nvbios_connE connE;
102 u8 ver, hdr;
103 u32 conn;
104
105 if (init_exec(init)) {
106 if (init->outp) {
107 conn = init->outp->connector;
108 conn = nvbios_connEp(bios, conn, &ver, &hdr, &connE);
109 if (conn)
110 return connE.type;
111 }
112
113 error("script needs connector type\n");
114 }
115
116 return 0xff;
117}
118
119static inline u32
120init_nvreg(struct nvbios_init *init, u32 reg)
121{
122 struct nouveau_devinit *devinit = nouveau_devinit(init->bios);
123
124
125
126
127
128
129
130 reg &= ~0x00000003;
131
132
133
134
135 if (nv_device(init->bios)->card_type >= NV_50) {
136 if (reg & 0x80000000) {
137 reg += init_crtc(init) * 0x800;
138 reg &= ~0x80000000;
139 }
140
141 if (reg & 0x40000000) {
142 reg += init_or(init) * 0x800;
143 reg &= ~0x40000000;
144 if (reg & 0x20000000) {
145 reg += init_link(init) * 0x80;
146 reg &= ~0x20000000;
147 }
148 }
149 }
150
151 if (reg & ~0x00fffffc)
152 warn("unknown bits in register 0x%08x\n", reg);
153
154 if (devinit->mmio)
155 reg = devinit->mmio(devinit, reg);
156 return reg;
157}
158
159static u32
160init_rd32(struct nvbios_init *init, u32 reg)
161{
162 reg = init_nvreg(init, reg);
163 if (reg != ~0 && init_exec(init))
164 return nv_rd32(init->subdev, reg);
165 return 0x00000000;
166}
167
168static void
169init_wr32(struct nvbios_init *init, u32 reg, u32 val)
170{
171 reg = init_nvreg(init, reg);
172 if (reg != ~0 && init_exec(init))
173 nv_wr32(init->subdev, reg, val);
174}
175
176static u32
177init_mask(struct nvbios_init *init, u32 reg, u32 mask, u32 val)
178{
179 reg = init_nvreg(init, reg);
180 if (reg != ~0 && init_exec(init)) {
181 u32 tmp = nv_rd32(init->subdev, reg);
182 nv_wr32(init->subdev, reg, (tmp & ~mask) | val);
183 return tmp;
184 }
185 return 0x00000000;
186}
187
188static u8
189init_rdport(struct nvbios_init *init, u16 port)
190{
191 if (init_exec(init))
192 return nv_rdport(init->subdev, init->crtc, port);
193 return 0x00;
194}
195
196static void
197init_wrport(struct nvbios_init *init, u16 port, u8 value)
198{
199 if (init_exec(init))
200 nv_wrport(init->subdev, init->crtc, port, value);
201}
202
203static u8
204init_rdvgai(struct nvbios_init *init, u16 port, u8 index)
205{
206 struct nouveau_subdev *subdev = init->subdev;
207 if (init_exec(init)) {
208 int head = init->crtc < 0 ? 0 : init->crtc;
209 return nv_rdvgai(subdev, head, port, index);
210 }
211 return 0x00;
212}
213
214static void
215init_wrvgai(struct nvbios_init *init, u16 port, u8 index, u8 value)
216{
217
218 if (nv_device(init->subdev)->card_type < NV_50) {
219 if (port == 0x03d4 && index == 0x44)
220 init->crtc = 0;
221 }
222
223 if (init_exec(init)) {
224 int head = init->crtc < 0 ? 0 : init->crtc;
225 nv_wrvgai(init->subdev, head, port, index, value);
226 }
227
228
229 if (nv_device(init->subdev)->card_type < NV_50) {
230 if (port == 0x03d4 && index == 0x44 && value == 3)
231 init->crtc = 1;
232 }
233}
234
235static struct nouveau_i2c_port *
236init_i2c(struct nvbios_init *init, int index)
237{
238 struct nouveau_i2c *i2c = nouveau_i2c(init->bios);
239
240 if (index == 0xff) {
241 index = NV_I2C_DEFAULT(0);
242 if (init->outp && init->outp->i2c_upper_default)
243 index = NV_I2C_DEFAULT(1);
244 } else
245 if (index < 0) {
246 if (!init->outp) {
247 if (init_exec(init))
248 error("script needs output for i2c\n");
249 return NULL;
250 }
251
252 if (index == -2 && init->outp->location) {
253 index = NV_I2C_TYPE_EXTAUX(init->outp->extdev);
254 return i2c->find_type(i2c, index);
255 }
256
257 index = init->outp->i2c_index;
258 }
259
260 return i2c->find(i2c, index);
261}
262
263static int
264init_rdi2cr(struct nvbios_init *init, u8 index, u8 addr, u8 reg)
265{
266 struct nouveau_i2c_port *port = init_i2c(init, index);
267 if (port && init_exec(init))
268 return nv_rdi2cr(port, addr, reg);
269 return -ENODEV;
270}
271
272static int
273init_wri2cr(struct nvbios_init *init, u8 index, u8 addr, u8 reg, u8 val)
274{
275 struct nouveau_i2c_port *port = init_i2c(init, index);
276 if (port && init_exec(init))
277 return nv_wri2cr(port, addr, reg, val);
278 return -ENODEV;
279}
280
281static int
282init_rdauxr(struct nvbios_init *init, u32 addr)
283{
284 struct nouveau_i2c_port *port = init_i2c(init, -2);
285 u8 data;
286
287 if (port && init_exec(init)) {
288 int ret = nv_rdaux(port, addr, &data, 1);
289 if (ret)
290 return ret;
291 return data;
292 }
293
294 return -ENODEV;
295}
296
297static int
298init_wrauxr(struct nvbios_init *init, u32 addr, u8 data)
299{
300 struct nouveau_i2c_port *port = init_i2c(init, -2);
301 if (port && init_exec(init))
302 return nv_wraux(port, addr, &data, 1);
303 return -ENODEV;
304}
305
306static void
307init_prog_pll(struct nvbios_init *init, u32 id, u32 freq)
308{
309 struct nouveau_devinit *devinit = nouveau_devinit(init->bios);
310 if (devinit->pll_set && init_exec(init)) {
311 int ret = devinit->pll_set(devinit, id, freq);
312 if (ret)
313 warn("failed to prog pll 0x%08x to %dkHz\n", id, freq);
314 }
315}
316
317
318
319
320
321static u16
322init_table(struct nouveau_bios *bios, u16 *len)
323{
324 struct bit_entry bit_I;
325
326 if (!bit_entry(bios, 'I', &bit_I)) {
327 *len = bit_I.length;
328 return bit_I.offset;
329 }
330
331 if (bmp_version(bios) >= 0x0510) {
332 *len = 14;
333 return bios->bmp_offset + 75;
334 }
335
336 return 0x0000;
337}
338
339static u16
340init_table_(struct nvbios_init *init, u16 offset, const char *name)
341{
342 struct nouveau_bios *bios = init->bios;
343 u16 len, data = init_table(bios, &len);
344 if (data) {
345 if (len >= offset + 2) {
346 data = nv_ro16(bios, data + offset);
347 if (data)
348 return data;
349
350 warn("%s pointer invalid\n", name);
351 return 0x0000;
352 }
353
354 warn("init data too short for %s pointer", name);
355 return 0x0000;
356 }
357
358 warn("init data not found\n");
359 return 0x0000;
360}
361
362#define init_script_table(b) init_table_((b), 0x00, "script table")
363#define init_macro_index_table(b) init_table_((b), 0x02, "macro index table")
364#define init_macro_table(b) init_table_((b), 0x04, "macro table")
365#define init_condition_table(b) init_table_((b), 0x06, "condition table")
366#define init_io_condition_table(b) init_table_((b), 0x08, "io condition table")
367#define init_io_flag_condition_table(b) init_table_((b), 0x0a, "io flag conditon table")
368#define init_function_table(b) init_table_((b), 0x0c, "function table")
369#define init_xlat_table(b) init_table_((b), 0x10, "xlat table");
370
371static u16
372init_script(struct nouveau_bios *bios, int index)
373{
374 struct nvbios_init init = { .bios = bios };
375 u16 bmp_ver = bmp_version(bios), data;
376
377 if (bmp_ver && bmp_ver < 0x0510) {
378 if (index > 1 || bmp_ver < 0x0100)
379 return 0x0000;
380
381 data = bios->bmp_offset + (bmp_ver < 0x0200 ? 14 : 18);
382 return nv_ro16(bios, data + (index * 2));
383 }
384
385 data = init_script_table(&init);
386 if (data)
387 return nv_ro16(bios, data + (index * 2));
388
389 return 0x0000;
390}
391
392static u16
393init_unknown_script(struct nouveau_bios *bios)
394{
395 u16 len, data = init_table(bios, &len);
396 if (data && len >= 16)
397 return nv_ro16(bios, data + 14);
398 return 0x0000;
399}
400
401static u8
402init_ram_restrict_group_count(struct nvbios_init *init)
403{
404 return nvbios_ramcfg_count(init->bios);
405}
406
407static u8
408init_ram_restrict(struct nvbios_init *init)
409{
410
411
412
413
414
415
416
417
418 if (!init->ramcfg || init->bios->version.major < 0x70)
419 init->ramcfg = 0x80000000 | nvbios_ramcfg_index(init->subdev);
420 return (init->ramcfg & 0x7fffffff);
421}
422
423static u8
424init_xlat_(struct nvbios_init *init, u8 index, u8 offset)
425{
426 struct nouveau_bios *bios = init->bios;
427 u16 table = init_xlat_table(init);
428 if (table) {
429 u16 data = nv_ro16(bios, table + (index * 2));
430 if (data)
431 return nv_ro08(bios, data + offset);
432 warn("xlat table pointer %d invalid\n", index);
433 }
434 return 0x00;
435}
436
437
438
439
440
441static bool
442init_condition_met(struct nvbios_init *init, u8 cond)
443{
444 struct nouveau_bios *bios = init->bios;
445 u16 table = init_condition_table(init);
446 if (table) {
447 u32 reg = nv_ro32(bios, table + (cond * 12) + 0);
448 u32 msk = nv_ro32(bios, table + (cond * 12) + 4);
449 u32 val = nv_ro32(bios, table + (cond * 12) + 8);
450 trace("\t[0x%02x] (R[0x%06x] & 0x%08x) == 0x%08x\n",
451 cond, reg, msk, val);
452 return (init_rd32(init, reg) & msk) == val;
453 }
454 return false;
455}
456
457static bool
458init_io_condition_met(struct nvbios_init *init, u8 cond)
459{
460 struct nouveau_bios *bios = init->bios;
461 u16 table = init_io_condition_table(init);
462 if (table) {
463 u16 port = nv_ro16(bios, table + (cond * 5) + 0);
464 u8 index = nv_ro08(bios, table + (cond * 5) + 2);
465 u8 mask = nv_ro08(bios, table + (cond * 5) + 3);
466 u8 value = nv_ro08(bios, table + (cond * 5) + 4);
467 trace("\t[0x%02x] (0x%04x[0x%02x] & 0x%02x) == 0x%02x\n",
468 cond, port, index, mask, value);
469 return (init_rdvgai(init, port, index) & mask) == value;
470 }
471 return false;
472}
473
474static bool
475init_io_flag_condition_met(struct nvbios_init *init, u8 cond)
476{
477 struct nouveau_bios *bios = init->bios;
478 u16 table = init_io_flag_condition_table(init);
479 if (table) {
480 u16 port = nv_ro16(bios, table + (cond * 9) + 0);
481 u8 index = nv_ro08(bios, table + (cond * 9) + 2);
482 u8 mask = nv_ro08(bios, table + (cond * 9) + 3);
483 u8 shift = nv_ro08(bios, table + (cond * 9) + 4);
484 u16 data = nv_ro16(bios, table + (cond * 9) + 5);
485 u8 dmask = nv_ro08(bios, table + (cond * 9) + 7);
486 u8 value = nv_ro08(bios, table + (cond * 9) + 8);
487 u8 ioval = (init_rdvgai(init, port, index) & mask) >> shift;
488 return (nv_ro08(bios, data + ioval) & dmask) == value;
489 }
490 return false;
491}
492
493static inline u32
494init_shift(u32 data, u8 shift)
495{
496 if (shift < 0x80)
497 return data >> shift;
498 return data << (0x100 - shift);
499}
500
501static u32
502init_tmds_reg(struct nvbios_init *init, u8 tmds)
503{
504
505
506
507
508
509
510
511
512
513 const int pramdac_offset[13] = {
514 0, 0, 0x8, 0, 0x2000, 0, 0, 0, 0x2008, 0, 0, 0, 0x2000 };
515 const u32 pramdac_table[4] = {
516 0x6808b0, 0x6808b8, 0x6828b0, 0x6828b8 };
517
518 if (tmds >= 0x80) {
519 if (init->outp) {
520 u32 dacoffset = pramdac_offset[init->outp->or];
521 if (tmds == 0x81)
522 dacoffset ^= 8;
523 return 0x6808b0 + dacoffset;
524 }
525
526 if (init_exec(init))
527 error("tmds opcodes need dcb\n");
528 } else {
529 if (tmds < ARRAY_SIZE(pramdac_table))
530 return pramdac_table[tmds];
531
532 error("tmds selector 0x%02x unknown\n", tmds);
533 }
534
535 return 0;
536}
537
538
539
540
541
542
543
544
545
546static void
547init_reserved(struct nvbios_init *init)
548{
549 u8 opcode = nv_ro08(init->bios, init->offset);
550 u8 length, i;
551
552 switch (opcode) {
553 case 0xaa:
554 length = 4;
555 break;
556 default:
557 length = 1;
558 break;
559 }
560
561 trace("RESERVED 0x%02x\t", opcode);
562 for (i = 1; i < length; i++)
563 cont(" 0x%02x", nv_ro08(init->bios, init->offset + i));
564 cont("\n");
565 init->offset += length;
566}
567
568
569
570
571
572static void
573init_done(struct nvbios_init *init)
574{
575 trace("DONE\n");
576 init->offset = 0x0000;
577}
578
579
580
581
582
583static void
584init_io_restrict_prog(struct nvbios_init *init)
585{
586 struct nouveau_bios *bios = init->bios;
587 u16 port = nv_ro16(bios, init->offset + 1);
588 u8 index = nv_ro08(bios, init->offset + 3);
589 u8 mask = nv_ro08(bios, init->offset + 4);
590 u8 shift = nv_ro08(bios, init->offset + 5);
591 u8 count = nv_ro08(bios, init->offset + 6);
592 u32 reg = nv_ro32(bios, init->offset + 7);
593 u8 conf, i;
594
595 trace("IO_RESTRICT_PROG\tR[0x%06x] = "
596 "((0x%04x[0x%02x] & 0x%02x) >> %d) [{\n",
597 reg, port, index, mask, shift);
598 init->offset += 11;
599
600 conf = (init_rdvgai(init, port, index) & mask) >> shift;
601 for (i = 0; i < count; i++) {
602 u32 data = nv_ro32(bios, init->offset);
603
604 if (i == conf) {
605 trace("\t0x%08x *\n", data);
606 init_wr32(init, reg, data);
607 } else {
608 trace("\t0x%08x\n", data);
609 }
610
611 init->offset += 4;
612 }
613 trace("}]\n");
614}
615
616
617
618
619
620static void
621init_repeat(struct nvbios_init *init)
622{
623 struct nouveau_bios *bios = init->bios;
624 u8 count = nv_ro08(bios, init->offset + 1);
625 u16 repeat = init->repeat;
626
627 trace("REPEAT\t0x%02x\n", count);
628 init->offset += 2;
629
630 init->repeat = init->offset;
631 init->repend = init->offset;
632 while (count--) {
633 init->offset = init->repeat;
634 nvbios_exec(init);
635 if (count)
636 trace("REPEAT\t0x%02x\n", count);
637 }
638 init->offset = init->repend;
639 init->repeat = repeat;
640}
641
642
643
644
645
646static void
647init_io_restrict_pll(struct nvbios_init *init)
648{
649 struct nouveau_bios *bios = init->bios;
650 u16 port = nv_ro16(bios, init->offset + 1);
651 u8 index = nv_ro08(bios, init->offset + 3);
652 u8 mask = nv_ro08(bios, init->offset + 4);
653 u8 shift = nv_ro08(bios, init->offset + 5);
654 s8 iofc = nv_ro08(bios, init->offset + 6);
655 u8 count = nv_ro08(bios, init->offset + 7);
656 u32 reg = nv_ro32(bios, init->offset + 8);
657 u8 conf, i;
658
659 trace("IO_RESTRICT_PLL\tR[0x%06x] =PLL= "
660 "((0x%04x[0x%02x] & 0x%02x) >> 0x%02x) IOFCOND 0x%02x [{\n",
661 reg, port, index, mask, shift, iofc);
662 init->offset += 12;
663
664 conf = (init_rdvgai(init, port, index) & mask) >> shift;
665 for (i = 0; i < count; i++) {
666 u32 freq = nv_ro16(bios, init->offset) * 10;
667
668 if (i == conf) {
669 trace("\t%dkHz *\n", freq);
670 if (iofc > 0 && init_io_flag_condition_met(init, iofc))
671 freq *= 2;
672 init_prog_pll(init, reg, freq);
673 } else {
674 trace("\t%dkHz\n", freq);
675 }
676
677 init->offset += 2;
678 }
679 trace("}]\n");
680}
681
682
683
684
685
686static void
687init_end_repeat(struct nvbios_init *init)
688{
689 trace("END_REPEAT\n");
690 init->offset += 1;
691
692 if (init->repeat) {
693 init->repend = init->offset;
694 init->offset = 0;
695 }
696}
697
698
699
700
701
702static void
703init_copy(struct nvbios_init *init)
704{
705 struct nouveau_bios *bios = init->bios;
706 u32 reg = nv_ro32(bios, init->offset + 1);
707 u8 shift = nv_ro08(bios, init->offset + 5);
708 u8 smask = nv_ro08(bios, init->offset + 6);
709 u16 port = nv_ro16(bios, init->offset + 7);
710 u8 index = nv_ro08(bios, init->offset + 9);
711 u8 mask = nv_ro08(bios, init->offset + 10);
712 u8 data;
713
714 trace("COPY\t0x%04x[0x%02x] &= 0x%02x |= "
715 "((R[0x%06x] %s 0x%02x) & 0x%02x)\n",
716 port, index, mask, reg, (shift & 0x80) ? "<<" : ">>",
717 (shift & 0x80) ? (0x100 - shift) : shift, smask);
718 init->offset += 11;
719
720 data = init_rdvgai(init, port, index) & mask;
721 data |= init_shift(init_rd32(init, reg), shift) & smask;
722 init_wrvgai(init, port, index, data);
723}
724
725
726
727
728
729static void
730init_not(struct nvbios_init *init)
731{
732 trace("NOT\n");
733 init->offset += 1;
734 init_exec_inv(init);
735}
736
737
738
739
740
741static void
742init_io_flag_condition(struct nvbios_init *init)
743{
744 struct nouveau_bios *bios = init->bios;
745 u8 cond = nv_ro08(bios, init->offset + 1);
746
747 trace("IO_FLAG_CONDITION\t0x%02x\n", cond);
748 init->offset += 2;
749
750 if (!init_io_flag_condition_met(init, cond))
751 init_exec_set(init, false);
752}
753
754
755
756
757
758static void
759init_dp_condition(struct nvbios_init *init)
760{
761 struct nouveau_bios *bios = init->bios;
762 struct nvbios_dpout info;
763 u8 cond = nv_ro08(bios, init->offset + 1);
764 u8 unkn = nv_ro08(bios, init->offset + 2);
765 u8 ver, hdr, cnt, len;
766 u16 data;
767
768 trace("DP_CONDITION\t0x%02x 0x%02x\n", cond, unkn);
769 init->offset += 3;
770
771 switch (cond) {
772 case 0:
773 if (init_conn(init) != DCB_CONNECTOR_eDP)
774 init_exec_set(init, false);
775 break;
776 case 1:
777 case 2:
778 if ( init->outp &&
779 (data = nvbios_dpout_match(bios, DCB_OUTPUT_DP,
780 (init->outp->or << 0) |
781 (init->outp->sorconf.link << 6),
782 &ver, &hdr, &cnt, &len, &info)))
783 {
784 if (!(info.flags & cond))
785 init_exec_set(init, false);
786 break;
787 }
788
789 if (init_exec(init))
790 warn("script needs dp output table data\n");
791 break;
792 case 5:
793 if (!(init_rdauxr(init, 0x0d) & 1))
794 init_exec_set(init, false);
795 break;
796 default:
797 warn("unknown dp condition 0x%02x\n", cond);
798 break;
799 }
800}
801
802
803
804
805
806static void
807init_io_mask_or(struct nvbios_init *init)
808{
809 struct nouveau_bios *bios = init->bios;
810 u8 index = nv_ro08(bios, init->offset + 1);
811 u8 or = init_or(init);
812 u8 data;
813
814 trace("IO_MASK_OR\t0x03d4[0x%02x] &= ~(1 << 0x%02x)\n", index, or);
815 init->offset += 2;
816
817 data = init_rdvgai(init, 0x03d4, index);
818 init_wrvgai(init, 0x03d4, index, data &= ~(1 << or));
819}
820
821
822
823
824
825static void
826init_io_or(struct nvbios_init *init)
827{
828 struct nouveau_bios *bios = init->bios;
829 u8 index = nv_ro08(bios, init->offset + 1);
830 u8 or = init_or(init);
831 u8 data;
832
833 trace("IO_OR\t0x03d4[0x%02x] |= (1 << 0x%02x)\n", index, or);
834 init->offset += 2;
835
836 data = init_rdvgai(init, 0x03d4, index);
837 init_wrvgai(init, 0x03d4, index, data | (1 << or));
838}
839
840
841
842
843
844static void
845init_idx_addr_latched(struct nvbios_init *init)
846{
847 struct nouveau_bios *bios = init->bios;
848 u32 creg = nv_ro32(bios, init->offset + 1);
849 u32 dreg = nv_ro32(bios, init->offset + 5);
850 u32 mask = nv_ro32(bios, init->offset + 9);
851 u32 data = nv_ro32(bios, init->offset + 13);
852 u8 count = nv_ro08(bios, init->offset + 17);
853
854 trace("INDEX_ADDRESS_LATCHED\tR[0x%06x] : R[0x%06x]\n", creg, dreg);
855 trace("\tCTRL &= 0x%08x |= 0x%08x\n", mask, data);
856 init->offset += 18;
857
858 while (count--) {
859 u8 iaddr = nv_ro08(bios, init->offset + 0);
860 u8 idata = nv_ro08(bios, init->offset + 1);
861
862 trace("\t[0x%02x] = 0x%02x\n", iaddr, idata);
863 init->offset += 2;
864
865 init_wr32(init, dreg, idata);
866 init_mask(init, creg, ~mask, data | iaddr);
867 }
868}
869
870
871
872
873
874static void
875init_io_restrict_pll2(struct nvbios_init *init)
876{
877 struct nouveau_bios *bios = init->bios;
878 u16 port = nv_ro16(bios, init->offset + 1);
879 u8 index = nv_ro08(bios, init->offset + 3);
880 u8 mask = nv_ro08(bios, init->offset + 4);
881 u8 shift = nv_ro08(bios, init->offset + 5);
882 u8 count = nv_ro08(bios, init->offset + 6);
883 u32 reg = nv_ro32(bios, init->offset + 7);
884 u8 conf, i;
885
886 trace("IO_RESTRICT_PLL2\t"
887 "R[0x%06x] =PLL= ((0x%04x[0x%02x] & 0x%02x) >> 0x%02x) [{\n",
888 reg, port, index, mask, shift);
889 init->offset += 11;
890
891 conf = (init_rdvgai(init, port, index) & mask) >> shift;
892 for (i = 0; i < count; i++) {
893 u32 freq = nv_ro32(bios, init->offset);
894 if (i == conf) {
895 trace("\t%dkHz *\n", freq);
896 init_prog_pll(init, reg, freq);
897 } else {
898 trace("\t%dkHz\n", freq);
899 }
900 init->offset += 4;
901 }
902 trace("}]\n");
903}
904
905
906
907
908
909static void
910init_pll2(struct nvbios_init *init)
911{
912 struct nouveau_bios *bios = init->bios;
913 u32 reg = nv_ro32(bios, init->offset + 1);
914 u32 freq = nv_ro32(bios, init->offset + 5);
915
916 trace("PLL2\tR[0x%06x] =PLL= %dkHz\n", reg, freq);
917 init->offset += 9;
918
919 init_prog_pll(init, reg, freq);
920}
921
922
923
924
925
926static void
927init_i2c_byte(struct nvbios_init *init)
928{
929 struct nouveau_bios *bios = init->bios;
930 u8 index = nv_ro08(bios, init->offset + 1);
931 u8 addr = nv_ro08(bios, init->offset + 2) >> 1;
932 u8 count = nv_ro08(bios, init->offset + 3);
933
934 trace("I2C_BYTE\tI2C[0x%02x][0x%02x]\n", index, addr);
935 init->offset += 4;
936
937 while (count--) {
938 u8 reg = nv_ro08(bios, init->offset + 0);
939 u8 mask = nv_ro08(bios, init->offset + 1);
940 u8 data = nv_ro08(bios, init->offset + 2);
941 int val;
942
943 trace("\t[0x%02x] &= 0x%02x |= 0x%02x\n", reg, mask, data);
944 init->offset += 3;
945
946 val = init_rdi2cr(init, index, addr, reg);
947 if (val < 0)
948 continue;
949 init_wri2cr(init, index, addr, reg, (val & mask) | data);
950 }
951}
952
953
954
955
956
957static void
958init_zm_i2c_byte(struct nvbios_init *init)
959{
960 struct nouveau_bios *bios = init->bios;
961 u8 index = nv_ro08(bios, init->offset + 1);
962 u8 addr = nv_ro08(bios, init->offset + 2) >> 1;
963 u8 count = nv_ro08(bios, init->offset + 3);
964
965 trace("ZM_I2C_BYTE\tI2C[0x%02x][0x%02x]\n", index, addr);
966 init->offset += 4;
967
968 while (count--) {
969 u8 reg = nv_ro08(bios, init->offset + 0);
970 u8 data = nv_ro08(bios, init->offset + 1);
971
972 trace("\t[0x%02x] = 0x%02x\n", reg, data);
973 init->offset += 2;
974
975 init_wri2cr(init, index, addr, reg, data);
976 }
977
978}
979
980
981
982
983
984static void
985init_zm_i2c(struct nvbios_init *init)
986{
987 struct nouveau_bios *bios = init->bios;
988 u8 index = nv_ro08(bios, init->offset + 1);
989 u8 addr = nv_ro08(bios, init->offset + 2) >> 1;
990 u8 count = nv_ro08(bios, init->offset + 3);
991 u8 data[256], i;
992
993 trace("ZM_I2C\tI2C[0x%02x][0x%02x]\n", index, addr);
994 init->offset += 4;
995
996 for (i = 0; i < count; i++) {
997 data[i] = nv_ro08(bios, init->offset);
998 trace("\t0x%02x\n", data[i]);
999 init->offset++;
1000 }
1001
1002 if (init_exec(init)) {
1003 struct nouveau_i2c_port *port = init_i2c(init, index);
1004 struct i2c_msg msg = {
1005 .addr = addr, .flags = 0, .len = count, .buf = data,
1006 };
1007 int ret;
1008
1009 if (port && (ret = i2c_transfer(&port->adapter, &msg, 1)) != 1)
1010 warn("i2c wr failed, %d\n", ret);
1011 }
1012}
1013
1014
1015
1016
1017
1018static void
1019init_tmds(struct nvbios_init *init)
1020{
1021 struct nouveau_bios *bios = init->bios;
1022 u8 tmds = nv_ro08(bios, init->offset + 1);
1023 u8 addr = nv_ro08(bios, init->offset + 2);
1024 u8 mask = nv_ro08(bios, init->offset + 3);
1025 u8 data = nv_ro08(bios, init->offset + 4);
1026 u32 reg = init_tmds_reg(init, tmds);
1027
1028 trace("TMDS\tT[0x%02x][0x%02x] &= 0x%02x |= 0x%02x\n",
1029 tmds, addr, mask, data);
1030 init->offset += 5;
1031
1032 if (reg == 0)
1033 return;
1034
1035 init_wr32(init, reg + 0, addr | 0x00010000);
1036 init_wr32(init, reg + 4, data | (init_rd32(init, reg + 4) & mask));
1037 init_wr32(init, reg + 0, addr);
1038}
1039
1040
1041
1042
1043
1044static void
1045init_zm_tmds_group(struct nvbios_init *init)
1046{
1047 struct nouveau_bios *bios = init->bios;
1048 u8 tmds = nv_ro08(bios, init->offset + 1);
1049 u8 count = nv_ro08(bios, init->offset + 2);
1050 u32 reg = init_tmds_reg(init, tmds);
1051
1052 trace("TMDS_ZM_GROUP\tT[0x%02x]\n", tmds);
1053 init->offset += 3;
1054
1055 while (count--) {
1056 u8 addr = nv_ro08(bios, init->offset + 0);
1057 u8 data = nv_ro08(bios, init->offset + 1);
1058
1059 trace("\t[0x%02x] = 0x%02x\n", addr, data);
1060 init->offset += 2;
1061
1062 init_wr32(init, reg + 4, data);
1063 init_wr32(init, reg + 0, addr);
1064 }
1065}
1066
1067
1068
1069
1070
1071static void
1072init_cr_idx_adr_latch(struct nvbios_init *init)
1073{
1074 struct nouveau_bios *bios = init->bios;
1075 u8 addr0 = nv_ro08(bios, init->offset + 1);
1076 u8 addr1 = nv_ro08(bios, init->offset + 2);
1077 u8 base = nv_ro08(bios, init->offset + 3);
1078 u8 count = nv_ro08(bios, init->offset + 4);
1079 u8 save0;
1080
1081 trace("CR_INDEX_ADDR C[%02x] C[%02x]\n", addr0, addr1);
1082 init->offset += 5;
1083
1084 save0 = init_rdvgai(init, 0x03d4, addr0);
1085 while (count--) {
1086 u8 data = nv_ro08(bios, init->offset);
1087
1088 trace("\t\t[0x%02x] = 0x%02x\n", base, data);
1089 init->offset += 1;
1090
1091 init_wrvgai(init, 0x03d4, addr0, base++);
1092 init_wrvgai(init, 0x03d4, addr1, data);
1093 }
1094 init_wrvgai(init, 0x03d4, addr0, save0);
1095}
1096
1097
1098
1099
1100
1101static void
1102init_cr(struct nvbios_init *init)
1103{
1104 struct nouveau_bios *bios = init->bios;
1105 u8 addr = nv_ro08(bios, init->offset + 1);
1106 u8 mask = nv_ro08(bios, init->offset + 2);
1107 u8 data = nv_ro08(bios, init->offset + 3);
1108 u8 val;
1109
1110 trace("CR\t\tC[0x%02x] &= 0x%02x |= 0x%02x\n", addr, mask, data);
1111 init->offset += 4;
1112
1113 val = init_rdvgai(init, 0x03d4, addr) & mask;
1114 init_wrvgai(init, 0x03d4, addr, val | data);
1115}
1116
1117
1118
1119
1120
1121static void
1122init_zm_cr(struct nvbios_init *init)
1123{
1124 struct nouveau_bios *bios = init->bios;
1125 u8 addr = nv_ro08(bios, init->offset + 1);
1126 u8 data = nv_ro08(bios, init->offset + 2);
1127
1128 trace("ZM_CR\tC[0x%02x] = 0x%02x\n", addr, data);
1129 init->offset += 3;
1130
1131 init_wrvgai(init, 0x03d4, addr, data);
1132}
1133
1134
1135
1136
1137
1138static void
1139init_zm_cr_group(struct nvbios_init *init)
1140{
1141 struct nouveau_bios *bios = init->bios;
1142 u8 count = nv_ro08(bios, init->offset + 1);
1143
1144 trace("ZM_CR_GROUP\n");
1145 init->offset += 2;
1146
1147 while (count--) {
1148 u8 addr = nv_ro08(bios, init->offset + 0);
1149 u8 data = nv_ro08(bios, init->offset + 1);
1150
1151 trace("\t\tC[0x%02x] = 0x%02x\n", addr, data);
1152 init->offset += 2;
1153
1154 init_wrvgai(init, 0x03d4, addr, data);
1155 }
1156}
1157
1158
1159
1160
1161
1162static void
1163init_condition_time(struct nvbios_init *init)
1164{
1165 struct nouveau_bios *bios = init->bios;
1166 u8 cond = nv_ro08(bios, init->offset + 1);
1167 u8 retry = nv_ro08(bios, init->offset + 2);
1168 u8 wait = min((u16)retry * 50, 100);
1169
1170 trace("CONDITION_TIME\t0x%02x 0x%02x\n", cond, retry);
1171 init->offset += 3;
1172
1173 if (!init_exec(init))
1174 return;
1175
1176 while (wait--) {
1177 if (init_condition_met(init, cond))
1178 return;
1179 mdelay(20);
1180 }
1181
1182 init_exec_set(init, false);
1183}
1184
1185
1186
1187
1188
1189static void
1190init_ltime(struct nvbios_init *init)
1191{
1192 struct nouveau_bios *bios = init->bios;
1193 u16 msec = nv_ro16(bios, init->offset + 1);
1194
1195 trace("LTIME\t0x%04x\n", msec);
1196 init->offset += 3;
1197
1198 if (init_exec(init))
1199 mdelay(msec);
1200}
1201
1202
1203
1204
1205
1206static void
1207init_zm_reg_sequence(struct nvbios_init *init)
1208{
1209 struct nouveau_bios *bios = init->bios;
1210 u32 base = nv_ro32(bios, init->offset + 1);
1211 u8 count = nv_ro08(bios, init->offset + 5);
1212
1213 trace("ZM_REG_SEQUENCE\t0x%02x\n", count);
1214 init->offset += 6;
1215
1216 while (count--) {
1217 u32 data = nv_ro32(bios, init->offset);
1218
1219 trace("\t\tR[0x%06x] = 0x%08x\n", base, data);
1220 init->offset += 4;
1221
1222 init_wr32(init, base, data);
1223 base += 4;
1224 }
1225}
1226
1227
1228
1229
1230
1231static void
1232init_sub_direct(struct nvbios_init *init)
1233{
1234 struct nouveau_bios *bios = init->bios;
1235 u16 addr = nv_ro16(bios, init->offset + 1);
1236 u16 save;
1237
1238 trace("SUB_DIRECT\t0x%04x\n", addr);
1239
1240 if (init_exec(init)) {
1241 save = init->offset;
1242 init->offset = addr;
1243 if (nvbios_exec(init)) {
1244 error("error parsing sub-table\n");
1245 return;
1246 }
1247 init->offset = save;
1248 }
1249
1250 init->offset += 3;
1251}
1252
1253
1254
1255
1256
1257static void
1258init_jump(struct nvbios_init *init)
1259{
1260 struct nouveau_bios *bios = init->bios;
1261 u16 offset = nv_ro16(bios, init->offset + 1);
1262
1263 trace("JUMP\t0x%04x\n", offset);
1264
1265 if (init_exec(init))
1266 init->offset = offset;
1267 else
1268 init->offset += 3;
1269}
1270
1271
1272
1273
1274
1275static void
1276init_i2c_if(struct nvbios_init *init)
1277{
1278 struct nouveau_bios *bios = init->bios;
1279 u8 index = nv_ro08(bios, init->offset + 1);
1280 u8 addr = nv_ro08(bios, init->offset + 2);
1281 u8 reg = nv_ro08(bios, init->offset + 3);
1282 u8 mask = nv_ro08(bios, init->offset + 4);
1283 u8 data = nv_ro08(bios, init->offset + 5);
1284 u8 value;
1285
1286 trace("I2C_IF\tI2C[0x%02x][0x%02x][0x%02x] & 0x%02x == 0x%02x\n",
1287 index, addr, reg, mask, data);
1288 init->offset += 6;
1289 init_exec_force(init, true);
1290
1291 value = init_rdi2cr(init, index, addr, reg);
1292 if ((value & mask) != data)
1293 init_exec_set(init, false);
1294
1295 init_exec_force(init, false);
1296}
1297
1298
1299
1300
1301
1302static void
1303init_copy_nv_reg(struct nvbios_init *init)
1304{
1305 struct nouveau_bios *bios = init->bios;
1306 u32 sreg = nv_ro32(bios, init->offset + 1);
1307 u8 shift = nv_ro08(bios, init->offset + 5);
1308 u32 smask = nv_ro32(bios, init->offset + 6);
1309 u32 sxor = nv_ro32(bios, init->offset + 10);
1310 u32 dreg = nv_ro32(bios, init->offset + 14);
1311 u32 dmask = nv_ro32(bios, init->offset + 18);
1312 u32 data;
1313
1314 trace("COPY_NV_REG\tR[0x%06x] &= 0x%08x |= "
1315 "((R[0x%06x] %s 0x%02x) & 0x%08x ^ 0x%08x)\n",
1316 dreg, dmask, sreg, (shift & 0x80) ? "<<" : ">>",
1317 (shift & 0x80) ? (0x100 - shift) : shift, smask, sxor);
1318 init->offset += 22;
1319
1320 data = init_shift(init_rd32(init, sreg), shift);
1321 init_mask(init, dreg, ~dmask, (data & smask) ^ sxor);
1322}
1323
1324
1325
1326
1327
1328static void
1329init_zm_index_io(struct nvbios_init *init)
1330{
1331 struct nouveau_bios *bios = init->bios;
1332 u16 port = nv_ro16(bios, init->offset + 1);
1333 u8 index = nv_ro08(bios, init->offset + 3);
1334 u8 data = nv_ro08(bios, init->offset + 4);
1335
1336 trace("ZM_INDEX_IO\tI[0x%04x][0x%02x] = 0x%02x\n", port, index, data);
1337 init->offset += 5;
1338
1339 init_wrvgai(init, port, index, data);
1340}
1341
1342
1343
1344
1345
1346static void
1347init_compute_mem(struct nvbios_init *init)
1348{
1349 struct nouveau_devinit *devinit = nouveau_devinit(init->bios);
1350
1351 trace("COMPUTE_MEM\n");
1352 init->offset += 1;
1353
1354 init_exec_force(init, true);
1355 if (init_exec(init) && devinit->meminit)
1356 devinit->meminit(devinit);
1357 init_exec_force(init, false);
1358}
1359
1360
1361
1362
1363
1364static void
1365init_reset(struct nvbios_init *init)
1366{
1367 struct nouveau_bios *bios = init->bios;
1368 u32 reg = nv_ro32(bios, init->offset + 1);
1369 u32 data1 = nv_ro32(bios, init->offset + 5);
1370 u32 data2 = nv_ro32(bios, init->offset + 9);
1371 u32 savepci19;
1372
1373 trace("RESET\tR[0x%08x] = 0x%08x, 0x%08x", reg, data1, data2);
1374 init->offset += 13;
1375 init_exec_force(init, true);
1376
1377 savepci19 = init_mask(init, 0x00184c, 0x00000f00, 0x00000000);
1378 init_wr32(init, reg, data1);
1379 udelay(10);
1380 init_wr32(init, reg, data2);
1381 init_wr32(init, 0x00184c, savepci19);
1382 init_mask(init, 0x001850, 0x00000001, 0x00000000);
1383
1384 init_exec_force(init, false);
1385}
1386
1387
1388
1389
1390
1391static u16
1392init_configure_mem_clk(struct nvbios_init *init)
1393{
1394 u16 mdata = bmp_mem_init_table(init->bios);
1395 if (mdata)
1396 mdata += (init_rdvgai(init, 0x03d4, 0x3c) >> 4) * 66;
1397 return mdata;
1398}
1399
1400static void
1401init_configure_mem(struct nvbios_init *init)
1402{
1403 struct nouveau_bios *bios = init->bios;
1404 u16 mdata, sdata;
1405 u32 addr, data;
1406
1407 trace("CONFIGURE_MEM\n");
1408 init->offset += 1;
1409
1410 if (bios->version.major > 2) {
1411 init_done(init);
1412 return;
1413 }
1414 init_exec_force(init, true);
1415
1416 mdata = init_configure_mem_clk(init);
1417 sdata = bmp_sdr_seq_table(bios);
1418 if (nv_ro08(bios, mdata) & 0x01)
1419 sdata = bmp_ddr_seq_table(bios);
1420 mdata += 6;
1421
1422 data = init_rdvgai(init, 0x03c4, 0x01);
1423 init_wrvgai(init, 0x03c4, 0x01, data | 0x20);
1424
1425 for (; (addr = nv_ro32(bios, sdata)) != 0xffffffff; sdata += 4) {
1426 switch (addr) {
1427 case 0x10021c:
1428 case 0x1002d0:
1429 case 0x1002d4:
1430 data = 0x00000001;
1431 break;
1432 default:
1433 data = nv_ro32(bios, mdata);
1434 mdata += 4;
1435 if (data == 0xffffffff)
1436 continue;
1437 break;
1438 }
1439
1440 init_wr32(init, addr, data);
1441 }
1442
1443 init_exec_force(init, false);
1444}
1445
1446
1447
1448
1449
1450static void
1451init_configure_clk(struct nvbios_init *init)
1452{
1453 struct nouveau_bios *bios = init->bios;
1454 u16 mdata, clock;
1455
1456 trace("CONFIGURE_CLK\n");
1457 init->offset += 1;
1458
1459 if (bios->version.major > 2) {
1460 init_done(init);
1461 return;
1462 }
1463 init_exec_force(init, true);
1464
1465 mdata = init_configure_mem_clk(init);
1466
1467
1468 clock = nv_ro16(bios, mdata + 4) * 10;
1469 init_prog_pll(init, 0x680500, clock);
1470
1471
1472 clock = nv_ro16(bios, mdata + 2) * 10;
1473 if (nv_ro08(bios, mdata) & 0x01)
1474 clock *= 2;
1475 init_prog_pll(init, 0x680504, clock);
1476
1477 init_exec_force(init, false);
1478}
1479
1480
1481
1482
1483
1484static void
1485init_configure_preinit(struct nvbios_init *init)
1486{
1487 struct nouveau_bios *bios = init->bios;
1488 u32 strap;
1489
1490 trace("CONFIGURE_PREINIT\n");
1491 init->offset += 1;
1492
1493 if (bios->version.major > 2) {
1494 init_done(init);
1495 return;
1496 }
1497 init_exec_force(init, true);
1498
1499 strap = init_rd32(init, 0x101000);
1500 strap = ((strap << 2) & 0xf0) | ((strap & 0x40) >> 6);
1501 init_wrvgai(init, 0x03d4, 0x3c, strap);
1502
1503 init_exec_force(init, false);
1504}
1505
1506
1507
1508
1509
1510static void
1511init_io(struct nvbios_init *init)
1512{
1513 struct nouveau_bios *bios = init->bios;
1514 u16 port = nv_ro16(bios, init->offset + 1);
1515 u8 mask = nv_ro16(bios, init->offset + 3);
1516 u8 data = nv_ro16(bios, init->offset + 4);
1517 u8 value;
1518
1519 trace("IO\t\tI[0x%04x] &= 0x%02x |= 0x%02x\n", port, mask, data);
1520 init->offset += 5;
1521
1522
1523
1524
1525
1526 if (nv_device(init->bios)->card_type >= NV_50 &&
1527 port == 0x03c3 && data == 0x01) {
1528 init_mask(init, 0x614100, 0xf0800000, 0x00800000);
1529 init_mask(init, 0x00e18c, 0x00020000, 0x00020000);
1530 init_mask(init, 0x614900, 0xf0800000, 0x00800000);
1531 init_mask(init, 0x000200, 0x40000000, 0x00000000);
1532 mdelay(10);
1533 init_mask(init, 0x00e18c, 0x00020000, 0x00000000);
1534 init_mask(init, 0x000200, 0x40000000, 0x40000000);
1535 init_wr32(init, 0x614100, 0x00800018);
1536 init_wr32(init, 0x614900, 0x00800018);
1537 mdelay(10);
1538 init_wr32(init, 0x614100, 0x10000018);
1539 init_wr32(init, 0x614900, 0x10000018);
1540 }
1541
1542 value = init_rdport(init, port) & mask;
1543 init_wrport(init, port, data | value);
1544}
1545
1546
1547
1548
1549
1550static void
1551init_sub(struct nvbios_init *init)
1552{
1553 struct nouveau_bios *bios = init->bios;
1554 u8 index = nv_ro08(bios, init->offset + 1);
1555 u16 addr, save;
1556
1557 trace("SUB\t0x%02x\n", index);
1558
1559 addr = init_script(bios, index);
1560 if (addr && init_exec(init)) {
1561 save = init->offset;
1562 init->offset = addr;
1563 if (nvbios_exec(init)) {
1564 error("error parsing sub-table\n");
1565 return;
1566 }
1567 init->offset = save;
1568 }
1569
1570 init->offset += 2;
1571}
1572
1573
1574
1575
1576
1577static void
1578init_ram_condition(struct nvbios_init *init)
1579{
1580 struct nouveau_bios *bios = init->bios;
1581 u8 mask = nv_ro08(bios, init->offset + 1);
1582 u8 value = nv_ro08(bios, init->offset + 2);
1583
1584 trace("RAM_CONDITION\t"
1585 "(R[0x100000] & 0x%02x) == 0x%02x\n", mask, value);
1586 init->offset += 3;
1587
1588 if ((init_rd32(init, 0x100000) & mask) != value)
1589 init_exec_set(init, false);
1590}
1591
1592
1593
1594
1595
1596static void
1597init_nv_reg(struct nvbios_init *init)
1598{
1599 struct nouveau_bios *bios = init->bios;
1600 u32 reg = nv_ro32(bios, init->offset + 1);
1601 u32 mask = nv_ro32(bios, init->offset + 5);
1602 u32 data = nv_ro32(bios, init->offset + 9);
1603
1604 trace("NV_REG\tR[0x%06x] &= 0x%08x |= 0x%08x\n", reg, mask, data);
1605 init->offset += 13;
1606
1607 init_mask(init, reg, ~mask, data);
1608}
1609
1610
1611
1612
1613
1614static void
1615init_macro(struct nvbios_init *init)
1616{
1617 struct nouveau_bios *bios = init->bios;
1618 u8 macro = nv_ro08(bios, init->offset + 1);
1619 u16 table;
1620
1621 trace("MACRO\t0x%02x\n", macro);
1622
1623 table = init_macro_table(init);
1624 if (table) {
1625 u32 addr = nv_ro32(bios, table + (macro * 8) + 0);
1626 u32 data = nv_ro32(bios, table + (macro * 8) + 4);
1627 trace("\t\tR[0x%06x] = 0x%08x\n", addr, data);
1628 init_wr32(init, addr, data);
1629 }
1630
1631 init->offset += 2;
1632}
1633
1634
1635
1636
1637
1638static void
1639init_resume(struct nvbios_init *init)
1640{
1641 trace("RESUME\n");
1642 init->offset += 1;
1643 init_exec_set(init, true);
1644}
1645
1646
1647
1648
1649
1650static void
1651init_time(struct nvbios_init *init)
1652{
1653 struct nouveau_bios *bios = init->bios;
1654 u16 usec = nv_ro16(bios, init->offset + 1);
1655
1656 trace("TIME\t0x%04x\n", usec);
1657 init->offset += 3;
1658
1659 if (init_exec(init)) {
1660 if (usec < 1000)
1661 udelay(usec);
1662 else
1663 mdelay((usec + 900) / 1000);
1664 }
1665}
1666
1667
1668
1669
1670
1671static void
1672init_condition(struct nvbios_init *init)
1673{
1674 struct nouveau_bios *bios = init->bios;
1675 u8 cond = nv_ro08(bios, init->offset + 1);
1676
1677 trace("CONDITION\t0x%02x\n", cond);
1678 init->offset += 2;
1679
1680 if (!init_condition_met(init, cond))
1681 init_exec_set(init, false);
1682}
1683
1684
1685
1686
1687
1688static void
1689init_io_condition(struct nvbios_init *init)
1690{
1691 struct nouveau_bios *bios = init->bios;
1692 u8 cond = nv_ro08(bios, init->offset + 1);
1693
1694 trace("IO_CONDITION\t0x%02x\n", cond);
1695 init->offset += 2;
1696
1697 if (!init_io_condition_met(init, cond))
1698 init_exec_set(init, false);
1699}
1700
1701
1702
1703
1704
1705static void
1706init_index_io(struct nvbios_init *init)
1707{
1708 struct nouveau_bios *bios = init->bios;
1709 u16 port = nv_ro16(bios, init->offset + 1);
1710 u8 index = nv_ro16(bios, init->offset + 3);
1711 u8 mask = nv_ro08(bios, init->offset + 4);
1712 u8 data = nv_ro08(bios, init->offset + 5);
1713 u8 value;
1714
1715 trace("INDEX_IO\tI[0x%04x][0x%02x] &= 0x%02x |= 0x%02x\n",
1716 port, index, mask, data);
1717 init->offset += 6;
1718
1719 value = init_rdvgai(init, port, index) & mask;
1720 init_wrvgai(init, port, index, data | value);
1721}
1722
1723
1724
1725
1726
1727static void
1728init_pll(struct nvbios_init *init)
1729{
1730 struct nouveau_bios *bios = init->bios;
1731 u32 reg = nv_ro32(bios, init->offset + 1);
1732 u32 freq = nv_ro16(bios, init->offset + 5) * 10;
1733
1734 trace("PLL\tR[0x%06x] =PLL= %dkHz\n", reg, freq);
1735 init->offset += 7;
1736
1737 init_prog_pll(init, reg, freq);
1738}
1739
1740
1741
1742
1743
1744static void
1745init_zm_reg(struct nvbios_init *init)
1746{
1747 struct nouveau_bios *bios = init->bios;
1748 u32 addr = nv_ro32(bios, init->offset + 1);
1749 u32 data = nv_ro32(bios, init->offset + 5);
1750
1751 trace("ZM_REG\tR[0x%06x] = 0x%08x\n", addr, data);
1752 init->offset += 9;
1753
1754 if (addr == 0x000200)
1755 data |= 0x00000001;
1756
1757 init_wr32(init, addr, data);
1758}
1759
1760
1761
1762
1763
1764static void
1765init_ram_restrict_pll(struct nvbios_init *init)
1766{
1767 struct nouveau_bios *bios = init->bios;
1768 u8 type = nv_ro08(bios, init->offset + 1);
1769 u8 count = init_ram_restrict_group_count(init);
1770 u8 strap = init_ram_restrict(init);
1771 u8 cconf;
1772
1773 trace("RAM_RESTRICT_PLL\t0x%02x\n", type);
1774 init->offset += 2;
1775
1776 for (cconf = 0; cconf < count; cconf++) {
1777 u32 freq = nv_ro32(bios, init->offset);
1778
1779 if (cconf == strap) {
1780 trace("%dkHz *\n", freq);
1781 init_prog_pll(init, type, freq);
1782 } else {
1783 trace("%dkHz\n", freq);
1784 }
1785
1786 init->offset += 4;
1787 }
1788}
1789
1790
1791
1792
1793
1794static void
1795init_gpio(struct nvbios_init *init)
1796{
1797 struct nouveau_gpio *gpio = nouveau_gpio(init->bios);
1798
1799 trace("GPIO\n");
1800 init->offset += 1;
1801
1802 if (init_exec(init) && gpio && gpio->reset)
1803 gpio->reset(gpio, DCB_GPIO_UNUSED);
1804}
1805
1806
1807
1808
1809
1810static void
1811init_ram_restrict_zm_reg_group(struct nvbios_init *init)
1812{
1813 struct nouveau_bios *bios = init->bios;
1814 u32 addr = nv_ro32(bios, init->offset + 1);
1815 u8 incr = nv_ro08(bios, init->offset + 5);
1816 u8 num = nv_ro08(bios, init->offset + 6);
1817 u8 count = init_ram_restrict_group_count(init);
1818 u8 index = init_ram_restrict(init);
1819 u8 i, j;
1820
1821 trace("RAM_RESTRICT_ZM_REG_GROUP\t"
1822 "R[0x%08x] 0x%02x 0x%02x\n", addr, incr, num);
1823 init->offset += 7;
1824
1825 for (i = 0; i < num; i++) {
1826 trace("\tR[0x%06x] = {\n", addr);
1827 for (j = 0; j < count; j++) {
1828 u32 data = nv_ro32(bios, init->offset);
1829
1830 if (j == index) {
1831 trace("\t\t0x%08x *\n", data);
1832 init_wr32(init, addr, data);
1833 } else {
1834 trace("\t\t0x%08x\n", data);
1835 }
1836
1837 init->offset += 4;
1838 }
1839 trace("\t}\n");
1840 addr += incr;
1841 }
1842}
1843
1844
1845
1846
1847
1848static void
1849init_copy_zm_reg(struct nvbios_init *init)
1850{
1851 struct nouveau_bios *bios = init->bios;
1852 u32 sreg = nv_ro32(bios, init->offset + 1);
1853 u32 dreg = nv_ro32(bios, init->offset + 5);
1854
1855 trace("COPY_ZM_REG\tR[0x%06x] = R[0x%06x]\n", dreg, sreg);
1856 init->offset += 9;
1857
1858 init_wr32(init, dreg, init_rd32(init, sreg));
1859}
1860
1861
1862
1863
1864
1865static void
1866init_zm_reg_group(struct nvbios_init *init)
1867{
1868 struct nouveau_bios *bios = init->bios;
1869 u32 addr = nv_ro32(bios, init->offset + 1);
1870 u8 count = nv_ro08(bios, init->offset + 5);
1871
1872 trace("ZM_REG_GROUP\tR[0x%06x] =\n", addr);
1873 init->offset += 6;
1874
1875 while (count--) {
1876 u32 data = nv_ro32(bios, init->offset);
1877 trace("\t0x%08x\n", data);
1878 init_wr32(init, addr, data);
1879 init->offset += 4;
1880 }
1881}
1882
1883
1884
1885
1886
1887static void
1888init_xlat(struct nvbios_init *init)
1889{
1890 struct nouveau_bios *bios = init->bios;
1891 u32 saddr = nv_ro32(bios, init->offset + 1);
1892 u8 sshift = nv_ro08(bios, init->offset + 5);
1893 u8 smask = nv_ro08(bios, init->offset + 6);
1894 u8 index = nv_ro08(bios, init->offset + 7);
1895 u32 daddr = nv_ro32(bios, init->offset + 8);
1896 u32 dmask = nv_ro32(bios, init->offset + 12);
1897 u8 shift = nv_ro08(bios, init->offset + 16);
1898 u32 data;
1899
1900 trace("INIT_XLAT\tR[0x%06x] &= 0x%08x |= "
1901 "(X%02x((R[0x%06x] %s 0x%02x) & 0x%02x) << 0x%02x)\n",
1902 daddr, dmask, index, saddr, (sshift & 0x80) ? "<<" : ">>",
1903 (sshift & 0x80) ? (0x100 - sshift) : sshift, smask, shift);
1904 init->offset += 17;
1905
1906 data = init_shift(init_rd32(init, saddr), sshift) & smask;
1907 data = init_xlat_(init, index, data) << shift;
1908 init_mask(init, daddr, ~dmask, data);
1909}
1910
1911
1912
1913
1914
1915static void
1916init_zm_mask_add(struct nvbios_init *init)
1917{
1918 struct nouveau_bios *bios = init->bios;
1919 u32 addr = nv_ro32(bios, init->offset + 1);
1920 u32 mask = nv_ro32(bios, init->offset + 5);
1921 u32 add = nv_ro32(bios, init->offset + 9);
1922 u32 data;
1923
1924 trace("ZM_MASK_ADD\tR[0x%06x] &= 0x%08x += 0x%08x\n", addr, mask, add);
1925 init->offset += 13;
1926
1927 data = init_rd32(init, addr);
1928 data = (data & mask) | ((data + add) & ~mask);
1929 init_wr32(init, addr, data);
1930}
1931
1932
1933
1934
1935
1936static void
1937init_auxch(struct nvbios_init *init)
1938{
1939 struct nouveau_bios *bios = init->bios;
1940 u32 addr = nv_ro32(bios, init->offset + 1);
1941 u8 count = nv_ro08(bios, init->offset + 5);
1942
1943 trace("AUXCH\tAUX[0x%08x] 0x%02x\n", addr, count);
1944 init->offset += 6;
1945
1946 while (count--) {
1947 u8 mask = nv_ro08(bios, init->offset + 0);
1948 u8 data = nv_ro08(bios, init->offset + 1);
1949 trace("\tAUX[0x%08x] &= 0x%02x |= 0x%02x\n", addr, mask, data);
1950 mask = init_rdauxr(init, addr) & mask;
1951 init_wrauxr(init, addr, mask | data);
1952 init->offset += 2;
1953 }
1954}
1955
1956
1957
1958
1959
1960static void
1961init_zm_auxch(struct nvbios_init *init)
1962{
1963 struct nouveau_bios *bios = init->bios;
1964 u32 addr = nv_ro32(bios, init->offset + 1);
1965 u8 count = nv_ro08(bios, init->offset + 5);
1966
1967 trace("ZM_AUXCH\tAUX[0x%08x] 0x%02x\n", addr, count);
1968 init->offset += 6;
1969
1970 while (count--) {
1971 u8 data = nv_ro08(bios, init->offset + 0);
1972 trace("\tAUX[0x%08x] = 0x%02x\n", addr, data);
1973 init_wrauxr(init, addr, data);
1974 init->offset += 1;
1975 }
1976}
1977
1978
1979
1980
1981
1982static void
1983init_i2c_long_if(struct nvbios_init *init)
1984{
1985 struct nouveau_bios *bios = init->bios;
1986 u8 index = nv_ro08(bios, init->offset + 1);
1987 u8 addr = nv_ro08(bios, init->offset + 2) >> 1;
1988 u8 reglo = nv_ro08(bios, init->offset + 3);
1989 u8 reghi = nv_ro08(bios, init->offset + 4);
1990 u8 mask = nv_ro08(bios, init->offset + 5);
1991 u8 data = nv_ro08(bios, init->offset + 6);
1992 struct nouveau_i2c_port *port;
1993
1994 trace("I2C_LONG_IF\t"
1995 "I2C[0x%02x][0x%02x][0x%02x%02x] & 0x%02x == 0x%02x\n",
1996 index, addr, reglo, reghi, mask, data);
1997 init->offset += 7;
1998
1999 port = init_i2c(init, index);
2000 if (port) {
2001 u8 i[2] = { reghi, reglo };
2002 u8 o[1] = {};
2003 struct i2c_msg msg[] = {
2004 { .addr = addr, .flags = 0, .len = 2, .buf = i },
2005 { .addr = addr, .flags = I2C_M_RD, .len = 1, .buf = o }
2006 };
2007 int ret;
2008
2009 ret = i2c_transfer(&port->adapter, msg, 2);
2010 if (ret == 2 && ((o[0] & mask) == data))
2011 return;
2012 }
2013
2014 init_exec_set(init, false);
2015}
2016
2017
2018
2019
2020
2021static void
2022init_gpio_ne(struct nvbios_init *init)
2023{
2024 struct nouveau_bios *bios = init->bios;
2025 struct nouveau_gpio *gpio = nouveau_gpio(bios);
2026 struct dcb_gpio_func func;
2027 u8 count = nv_ro08(bios, init->offset + 1);
2028 u8 idx = 0, ver, len;
2029 u16 data, i;
2030
2031 trace("GPIO_NE\t");
2032 init->offset += 2;
2033
2034 for (i = init->offset; i < init->offset + count; i++)
2035 cont("0x%02x ", nv_ro08(bios, i));
2036 cont("\n");
2037
2038 while ((data = dcb_gpio_parse(bios, 0, idx++, &ver, &len, &func))) {
2039 if (func.func != DCB_GPIO_UNUSED) {
2040 for (i = init->offset; i < init->offset + count; i++) {
2041 if (func.func == nv_ro08(bios, i))
2042 break;
2043 }
2044
2045 trace("\tFUNC[0x%02x]", func.func);
2046 if (i == (init->offset + count)) {
2047 cont(" *");
2048 if (init_exec(init) && gpio && gpio->reset)
2049 gpio->reset(gpio, func.func);
2050 }
2051 cont("\n");
2052 }
2053 }
2054
2055 init->offset += count;
2056}
2057
2058static struct nvbios_init_opcode {
2059 void (*exec)(struct nvbios_init *);
2060} init_opcode[] = {
2061 [0x32] = { init_io_restrict_prog },
2062 [0x33] = { init_repeat },
2063 [0x34] = { init_io_restrict_pll },
2064 [0x36] = { init_end_repeat },
2065 [0x37] = { init_copy },
2066 [0x38] = { init_not },
2067 [0x39] = { init_io_flag_condition },
2068 [0x3a] = { init_dp_condition },
2069 [0x3b] = { init_io_mask_or },
2070 [0x3c] = { init_io_or },
2071 [0x49] = { init_idx_addr_latched },
2072 [0x4a] = { init_io_restrict_pll2 },
2073 [0x4b] = { init_pll2 },
2074 [0x4c] = { init_i2c_byte },
2075 [0x4d] = { init_zm_i2c_byte },
2076 [0x4e] = { init_zm_i2c },
2077 [0x4f] = { init_tmds },
2078 [0x50] = { init_zm_tmds_group },
2079 [0x51] = { init_cr_idx_adr_latch },
2080 [0x52] = { init_cr },
2081 [0x53] = { init_zm_cr },
2082 [0x54] = { init_zm_cr_group },
2083 [0x56] = { init_condition_time },
2084 [0x57] = { init_ltime },
2085 [0x58] = { init_zm_reg_sequence },
2086 [0x5b] = { init_sub_direct },
2087 [0x5c] = { init_jump },
2088 [0x5e] = { init_i2c_if },
2089 [0x5f] = { init_copy_nv_reg },
2090 [0x62] = { init_zm_index_io },
2091 [0x63] = { init_compute_mem },
2092 [0x65] = { init_reset },
2093 [0x66] = { init_configure_mem },
2094 [0x67] = { init_configure_clk },
2095 [0x68] = { init_configure_preinit },
2096 [0x69] = { init_io },
2097 [0x6b] = { init_sub },
2098 [0x6d] = { init_ram_condition },
2099 [0x6e] = { init_nv_reg },
2100 [0x6f] = { init_macro },
2101 [0x71] = { init_done },
2102 [0x72] = { init_resume },
2103 [0x74] = { init_time },
2104 [0x75] = { init_condition },
2105 [0x76] = { init_io_condition },
2106 [0x78] = { init_index_io },
2107 [0x79] = { init_pll },
2108 [0x7a] = { init_zm_reg },
2109 [0x87] = { init_ram_restrict_pll },
2110 [0x8c] = { init_reserved },
2111 [0x8d] = { init_reserved },
2112 [0x8e] = { init_gpio },
2113 [0x8f] = { init_ram_restrict_zm_reg_group },
2114 [0x90] = { init_copy_zm_reg },
2115 [0x91] = { init_zm_reg_group },
2116 [0x92] = { init_reserved },
2117 [0x96] = { init_xlat },
2118 [0x97] = { init_zm_mask_add },
2119 [0x98] = { init_auxch },
2120 [0x99] = { init_zm_auxch },
2121 [0x9a] = { init_i2c_long_if },
2122 [0xa9] = { init_gpio_ne },
2123 [0xaa] = { init_reserved },
2124};
2125
2126#define init_opcode_nr (sizeof(init_opcode) / sizeof(init_opcode[0]))
2127
2128int
2129nvbios_exec(struct nvbios_init *init)
2130{
2131 init->nested++;
2132 while (init->offset) {
2133 u8 opcode = nv_ro08(init->bios, init->offset);
2134 if (opcode >= init_opcode_nr || !init_opcode[opcode].exec) {
2135 error("unknown opcode 0x%02x\n", opcode);
2136 return -EINVAL;
2137 }
2138
2139 init_opcode[opcode].exec(init);
2140 }
2141 init->nested--;
2142 return 0;
2143}
2144
2145int
2146nvbios_init(struct nouveau_subdev *subdev, bool execute)
2147{
2148 struct nouveau_bios *bios = nouveau_bios(subdev);
2149 int ret = 0;
2150 int i = -1;
2151 u16 data;
2152
2153 if (execute)
2154 nv_info(bios, "running init tables\n");
2155 while (!ret && (data = (init_script(bios, ++i)))) {
2156 struct nvbios_init init = {
2157 .subdev = subdev,
2158 .bios = bios,
2159 .offset = data,
2160 .outp = NULL,
2161 .crtc = -1,
2162 .execute = execute ? 1 : 0,
2163 };
2164
2165 ret = nvbios_exec(&init);
2166 }
2167
2168
2169
2170
2171 if (!ret && (data = init_unknown_script(bios))) {
2172 struct nvbios_init init = {
2173 .subdev = subdev,
2174 .bios = bios,
2175 .offset = data,
2176 .outp = NULL,
2177 .crtc = -1,
2178 .execute = execute ? 1 : 0,
2179 };
2180
2181 ret = nvbios_exec(&init);
2182 }
2183
2184 return ret;
2185}
2186
