LXR linux/drivers/gpu/drm/nouveau/core/subdev/devinit/nv05.c

   1/*
   2 * Copyright (C) 2010 Francisco Jerez.
   3 * All Rights Reserved.
   4 *
   5 * Permission is hereby granted, free of charge, to any person obtaining
   6 * a copy of this software and associated documentation files (the
   7 * "Software"), to deal in the Software without restriction, including
   8 * without limitation the rights to use, copy, modify, merge, publish,
   9 * distribute, sublicense, and/or sell copies of the Software, and to
  10 * permit persons to whom the Software is furnished to do so, subject to
  11 * the following conditions:
  12 *
  13 * The above copyright notice and this permission notice (including the
  14 * next paragraph) shall be included in all copies or substantial
  15 * portions of the Software.
  16 *
  17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  20 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  21 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  22 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  24 *
  25 */
  26
  27#include <subdev/bios.h>
  28#include <subdev/bios/bmp.h>
  29#include <subdev/vga.h>
  30
  31#include "fbmem.h"
  32#include "nv04.h"
  33
  34static void
  35nv05_devinit_meminit(struct nouveau_devinit *devinit)
  36{
  37        static const u8 default_config_tab[][2] = {
  38                { 0x24, 0x00 },
  39                { 0x28, 0x00 },
  40                { 0x24, 0x01 },
  41                { 0x1f, 0x00 },
  42                { 0x0f, 0x00 },
  43                { 0x17, 0x00 },
  44                { 0x06, 0x00 },
  45                { 0x00, 0x00 }
  46        };
  47        struct nv04_devinit_priv *priv = (void *)devinit;
  48        struct nouveau_bios *bios = nouveau_bios(priv);
  49        struct io_mapping *fb;
  50        u32 patt = 0xdeadbeef;
  51        u16 data;
  52        u8 strap, ramcfg[2];
  53        int i, v;
  54
  55        /* Map the framebuffer aperture */
  56        fb = fbmem_init(nv_device(priv));
  57        if (!fb) {
  58                nv_error(priv, "failed to map fb\n");
  59                return;
  60        }
  61
  62        strap = (nv_rd32(priv, 0x101000) & 0x0000003c) >> 2;
  63        if ((data = bmp_mem_init_table(bios))) {
  64                ramcfg[0] = nv_ro08(bios, data + 2 * strap + 0);
  65                ramcfg[1] = nv_ro08(bios, data + 2 * strap + 1);
  66        } else {
  67                ramcfg[0] = default_config_tab[strap][0];
  68                ramcfg[1] = default_config_tab[strap][1];
  69        }
  70
  71        /* Sequencer off */
  72        nv_wrvgas(priv, 0, 1, nv_rdvgas(priv, 0, 1) | 0x20);
  73
  74        if (nv_rd32(priv, NV04_PFB_BOOT_0) & NV04_PFB_BOOT_0_UMA_ENABLE)
  75                goto out;
  76
  77        nv_mask(priv, NV04_PFB_DEBUG_0, NV04_PFB_DEBUG_0_REFRESH_OFF, 0);
  78
  79        /* If present load the hardcoded scrambling table */
  80        if (data) {
  81                for (i = 0, data += 0x10; i < 8; i++, data += 4) {
  82                        u32 scramble = nv_ro32(bios, data);
  83                        nv_wr32(priv, NV04_PFB_SCRAMBLE(i), scramble);
  84                }
  85        }
  86
  87        /* Set memory type/width/length defaults depending on the straps */
  88        nv_mask(priv, NV04_PFB_BOOT_0, 0x3f, ramcfg[0]);
  89
  90        if (ramcfg[1] & 0x80)
  91                nv_mask(priv, NV04_PFB_CFG0, 0, NV04_PFB_CFG0_SCRAMBLE);
  92
  93        nv_mask(priv, NV04_PFB_CFG1, 0x700001, (ramcfg[1] & 1) << 20);
  94        nv_mask(priv, NV04_PFB_CFG1, 0, 1);
  95
  96        /* Probe memory bus width */
  97        for (i = 0; i < 4; i++)
  98                fbmem_poke(fb, 4 * i, patt);
  99
 100        if (fbmem_peek(fb, 0xc) != patt)
 101                nv_mask(priv, NV04_PFB_BOOT_0,
 102                          NV04_PFB_BOOT_0_RAM_WIDTH_128, 0);
 103
 104        /* Probe memory length */
 105        v = nv_rd32(priv, NV04_PFB_BOOT_0) & NV04_PFB_BOOT_0_RAM_AMOUNT;
 106
 107        if (v == NV04_PFB_BOOT_0_RAM_AMOUNT_32MB &&
 108            (!fbmem_readback(fb, 0x1000000, ++patt) ||
 109             !fbmem_readback(fb, 0, ++patt)))
 110                nv_mask(priv, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT,
 111                          NV04_PFB_BOOT_0_RAM_AMOUNT_16MB);
 112
 113        if (v == NV04_PFB_BOOT_0_RAM_AMOUNT_16MB &&
 114            !fbmem_readback(fb, 0x800000, ++patt))
 115                nv_mask(priv, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT,
 116                          NV04_PFB_BOOT_0_RAM_AMOUNT_8MB);
 117
 118        if (!fbmem_readback(fb, 0x400000, ++patt))
 119                nv_mask(priv, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT,
 120                          NV04_PFB_BOOT_0_RAM_AMOUNT_4MB);
 121
 122out:
 123        /* Sequencer on */
 124        nv_wrvgas(priv, 0, 1, nv_rdvgas(priv, 0, 1) & ~0x20);
 125        fbmem_fini(fb);
 126}
 127
 128struct nouveau_oclass *
 129nv05_devinit_oclass = &(struct nouveau_devinit_impl) {
 130        .base.handle = NV_SUBDEV(DEVINIT, 0x05),
 131        .base.ofuncs = &(struct nouveau_ofuncs) {
 132                .ctor = nv04_devinit_ctor,
 133                .dtor = nv04_devinit_dtor,
 134                .init = nv04_devinit_init,
 135                .fini = nv04_devinit_fini,
 136        },
 137        .meminit = nv05_devinit_meminit,
 138        .pll_set = nv04_devinit_pll_set,
 139}.base;
 140