1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25#include <subdev/bios.h>
26#include <subdev/bios/pll.h>
27#include <subdev/bios/rammap.h>
28#include <subdev/bios/timing.h>
29#include <subdev/ltc.h>
30
31#include <subdev/clock.h>
32#include <subdev/clock/pll.h>
33
34#include <core/option.h>
35
36#include "ramfuc.h"
37
38#include "nvc0.h"
39
40struct nvc0_ramfuc {
41 struct ramfuc base;
42
43 struct ramfuc_reg r_0x10fe20;
44 struct ramfuc_reg r_0x10fe24;
45 struct ramfuc_reg r_0x137320;
46 struct ramfuc_reg r_0x137330;
47
48 struct ramfuc_reg r_0x132000;
49 struct ramfuc_reg r_0x132004;
50 struct ramfuc_reg r_0x132100;
51
52 struct ramfuc_reg r_0x137390;
53
54 struct ramfuc_reg r_0x10f290;
55 struct ramfuc_reg r_0x10f294;
56 struct ramfuc_reg r_0x10f298;
57 struct ramfuc_reg r_0x10f29c;
58 struct ramfuc_reg r_0x10f2a0;
59
60 struct ramfuc_reg r_0x10f300;
61 struct ramfuc_reg r_0x10f338;
62 struct ramfuc_reg r_0x10f340;
63 struct ramfuc_reg r_0x10f344;
64 struct ramfuc_reg r_0x10f348;
65
66 struct ramfuc_reg r_0x10f910;
67 struct ramfuc_reg r_0x10f914;
68
69 struct ramfuc_reg r_0x100b0c;
70 struct ramfuc_reg r_0x10f050;
71 struct ramfuc_reg r_0x10f090;
72 struct ramfuc_reg r_0x10f200;
73 struct ramfuc_reg r_0x10f210;
74 struct ramfuc_reg r_0x10f310;
75 struct ramfuc_reg r_0x10f314;
76 struct ramfuc_reg r_0x10f610;
77 struct ramfuc_reg r_0x10f614;
78 struct ramfuc_reg r_0x10f800;
79 struct ramfuc_reg r_0x10f808;
80 struct ramfuc_reg r_0x10f824;
81 struct ramfuc_reg r_0x10f830;
82 struct ramfuc_reg r_0x10f988;
83 struct ramfuc_reg r_0x10f98c;
84 struct ramfuc_reg r_0x10f990;
85 struct ramfuc_reg r_0x10f998;
86 struct ramfuc_reg r_0x10f9b0;
87 struct ramfuc_reg r_0x10f9b4;
88 struct ramfuc_reg r_0x10fb04;
89 struct ramfuc_reg r_0x10fb08;
90 struct ramfuc_reg r_0x137300;
91 struct ramfuc_reg r_0x137310;
92 struct ramfuc_reg r_0x137360;
93 struct ramfuc_reg r_0x1373ec;
94 struct ramfuc_reg r_0x1373f0;
95 struct ramfuc_reg r_0x1373f8;
96
97 struct ramfuc_reg r_0x61c140;
98 struct ramfuc_reg r_0x611200;
99
100 struct ramfuc_reg r_0x13d8f4;
101};
102
103struct nvc0_ram {
104 struct nouveau_ram base;
105 struct nvc0_ramfuc fuc;
106 struct nvbios_pll refpll;
107 struct nvbios_pll mempll;
108};
109
110static void
111nvc0_ram_train(struct nvc0_ramfuc *fuc, u32 magic)
112{
113 struct nvc0_ram *ram = container_of(fuc, typeof(*ram), fuc);
114 struct nouveau_fb *pfb = nouveau_fb(ram);
115 u32 part = nv_rd32(pfb, 0x022438), i;
116 u32 mask = nv_rd32(pfb, 0x022554);
117 u32 addr = 0x110974;
118
119 ram_wr32(fuc, 0x10f910, magic);
120 ram_wr32(fuc, 0x10f914, magic);
121
122 for (i = 0; (magic & 0x80000000) && i < part; addr += 0x1000, i++) {
123 if (mask & (1 << i))
124 continue;
125 ram_wait(fuc, addr, 0x0000000f, 0x00000000, 500000);
126 }
127}
128
129static int
130nvc0_ram_calc(struct nouveau_fb *pfb, u32 freq)
131{
132 struct nouveau_clock *clk = nouveau_clock(pfb);
133 struct nouveau_bios *bios = nouveau_bios(pfb);
134 struct nvc0_ram *ram = (void *)pfb->ram;
135 struct nvc0_ramfuc *fuc = &ram->fuc;
136 u8 ver, cnt, len, strap;
137 struct {
138 u32 data;
139 u8 size;
140 } rammap, ramcfg, timing;
141 int ref, div, out;
142 int from, mode;
143 int N1, M1, P;
144 int ret;
145
146
147 rammap.data = nvbios_rammapEm(bios, freq / 1000, &ver, &rammap.size,
148 &cnt, &ramcfg.size);
149 if (!rammap.data || ver != 0x10 || rammap.size < 0x0e) {
150 nv_error(pfb, "invalid/missing rammap entry\n");
151 return -EINVAL;
152 }
153
154
155 strap = nvbios_ramcfg_index(nv_subdev(pfb));
156 if (strap >= cnt) {
157 nv_error(pfb, "invalid ramcfg strap\n");
158 return -EINVAL;
159 }
160
161 ramcfg.data = rammap.data + rammap.size + (strap * ramcfg.size);
162 if (!ramcfg.data || ver != 0x10 || ramcfg.size < 0x0e) {
163 nv_error(pfb, "invalid/missing ramcfg entry\n");
164 return -EINVAL;
165 }
166
167
168 strap = nv_ro08(bios, ramcfg.data + 0x01);
169 if (strap != 0xff) {
170 timing.data = nvbios_timingEe(bios, strap, &ver, &timing.size,
171 &cnt, &len);
172 if (!timing.data || ver != 0x10 || timing.size < 0x19) {
173 nv_error(pfb, "invalid/missing timing entry\n");
174 return -EINVAL;
175 }
176 } else {
177 timing.data = 0;
178 }
179
180 ret = ram_init(fuc, pfb);
181 if (ret)
182 return ret;
183
184
185 from = !!(ram_rd32(fuc, 0x1373f0) & 0x00000002);
186
187
188 if (!(ram_rd32(fuc, 0x137300) & 0x00000100))
189 ref = clk->read(clk, nv_clk_src_sppll0);
190 else
191 ref = clk->read(clk, nv_clk_src_sppll1);
192 div = max(min((ref * 2) / freq, (u32)65), (u32)2) - 2;
193 out = (ref * 2) / (div + 2);
194 mode = freq != out;
195
196 ram_mask(fuc, 0x137360, 0x00000002, 0x00000000);
197
198 if ((ram_rd32(fuc, 0x132000) & 0x00000002) || 0 ) {
199 ram_nuke(fuc, 0x132000);
200 ram_mask(fuc, 0x132000, 0x00000002, 0x00000002);
201 ram_mask(fuc, 0x132000, 0x00000002, 0x00000000);
202 }
203
204 if (mode == 1) {
205 ram_nuke(fuc, 0x10fe20);
206 ram_mask(fuc, 0x10fe20, 0x00000002, 0x00000002);
207 ram_mask(fuc, 0x10fe20, 0x00000002, 0x00000000);
208 }
209
210
211 ram_wr32(fuc, 0x132100, 0x00000001);
212
213 if (mode == 1 && from == 0) {
214
215 ret = nva3_pll_calc(nv_subdev(pfb), &ram->refpll,
216 ram->mempll.refclk, &N1, NULL, &M1, &P);
217 if (ret <= 0) {
218 nv_error(pfb, "unable to calc refpll\n");
219 return ret ? ret : -ERANGE;
220 }
221
222 ram_wr32(fuc, 0x10fe20, 0x20010000);
223 ram_wr32(fuc, 0x137320, 0x00000003);
224 ram_wr32(fuc, 0x137330, 0x81200006);
225 ram_wr32(fuc, 0x10fe24, (P << 16) | (N1 << 8) | M1);
226 ram_wr32(fuc, 0x10fe20, 0x20010001);
227 ram_wait(fuc, 0x137390, 0x00020000, 0x00020000, 64000);
228
229
230 ret = nva3_pll_calc(nv_subdev(pfb), &ram->mempll, freq,
231 &N1, NULL, &M1, &P);
232 if (ret <= 0) {
233 nv_error(pfb, "unable to calc refpll\n");
234 return ret ? ret : -ERANGE;
235 }
236
237 ram_wr32(fuc, 0x10fe20, 0x20010005);
238 ram_wr32(fuc, 0x132004, (P << 16) | (N1 << 8) | M1);
239 ram_wr32(fuc, 0x132000, 0x18010101);
240 ram_wait(fuc, 0x137390, 0x00000002, 0x00000002, 64000);
241 } else
242 if (mode == 0) {
243 ram_wr32(fuc, 0x137300, 0x00000003);
244 }
245
246 if (from == 0) {
247 ram_nuke(fuc, 0x10fb04);
248 ram_mask(fuc, 0x10fb04, 0x0000ffff, 0x00000000);
249 ram_nuke(fuc, 0x10fb08);
250 ram_mask(fuc, 0x10fb08, 0x0000ffff, 0x00000000);
251 ram_wr32(fuc, 0x10f988, 0x2004ff00);
252 ram_wr32(fuc, 0x10f98c, 0x003fc040);
253 ram_wr32(fuc, 0x10f990, 0x20012001);
254 ram_wr32(fuc, 0x10f998, 0x00011a00);
255 ram_wr32(fuc, 0x13d8f4, 0x00000000);
256 } else {
257 ram_wr32(fuc, 0x10f988, 0x20010000);
258 ram_wr32(fuc, 0x10f98c, 0x00000000);
259 ram_wr32(fuc, 0x10f990, 0x20012001);
260 ram_wr32(fuc, 0x10f998, 0x00010a00);
261 }
262
263 if (from == 0) {
264
265 }
266
267
268 ram_wr32(fuc, 0x100b0c, 0x00080012);
269
270
271 ram_wr32(fuc, 0x611200, 0x00003300);
272
273
274
275 ram_mask(fuc, 0x10f200, 0x00000800, 0x00000000);
276 ram_wr32(fuc, 0x10f210, 0x00000000);
277 ram_nsec(fuc, 1000);
278 if (mode == 0)
279 nvc0_ram_train(fuc, 0x000c1001);
280 ram_wr32(fuc, 0x10f310, 0x00000001);
281 ram_nsec(fuc, 1000);
282 ram_wr32(fuc, 0x10f090, 0x00000061);
283 ram_wr32(fuc, 0x10f090, 0xc000007f);
284 ram_nsec(fuc, 1000);
285
286 if (from == 0) {
287 ram_wr32(fuc, 0x10f824, 0x00007fd4);
288 } else {
289 ram_wr32(fuc, 0x1373ec, 0x00020404);
290 }
291
292 if (mode == 0) {
293 ram_mask(fuc, 0x10f808, 0x00080000, 0x00000000);
294 ram_mask(fuc, 0x10f200, 0x00008000, 0x00008000);
295 ram_wr32(fuc, 0x10f830, 0x41500010);
296 ram_mask(fuc, 0x10f830, 0x01000000, 0x00000000);
297 ram_mask(fuc, 0x132100, 0x00000100, 0x00000100);
298 ram_wr32(fuc, 0x10f050, 0xff000090);
299 ram_wr32(fuc, 0x1373ec, 0x00020f0f);
300 ram_wr32(fuc, 0x1373f0, 0x00000003);
301 ram_wr32(fuc, 0x137310, 0x81201616);
302 ram_wr32(fuc, 0x132100, 0x00000001);
303
304 ram_wr32(fuc, 0x10f830, 0x00300017);
305 ram_wr32(fuc, 0x1373f0, 0x00000001);
306 ram_wr32(fuc, 0x10f824, 0x00007e77);
307 ram_wr32(fuc, 0x132000, 0x18030001);
308 ram_wr32(fuc, 0x10f090, 0x4000007e);
309 ram_nsec(fuc, 2000);
310 ram_wr32(fuc, 0x10f314, 0x00000001);
311 ram_wr32(fuc, 0x10f210, 0x80000000);
312 ram_wr32(fuc, 0x10f338, 0x00300220);
313 ram_wr32(fuc, 0x10f300, 0x0000011d);
314 ram_nsec(fuc, 1000);
315 ram_wr32(fuc, 0x10f290, 0x02060505);
316 ram_wr32(fuc, 0x10f294, 0x34208288);
317 ram_wr32(fuc, 0x10f298, 0x44050411);
318 ram_wr32(fuc, 0x10f29c, 0x0000114c);
319 ram_wr32(fuc, 0x10f2a0, 0x42e10069);
320 ram_wr32(fuc, 0x10f614, 0x40044f77);
321 ram_wr32(fuc, 0x10f610, 0x40044f77);
322 ram_wr32(fuc, 0x10f344, 0x00600009);
323 ram_nsec(fuc, 1000);
324 ram_wr32(fuc, 0x10f348, 0x00700008);
325 ram_wr32(fuc, 0x61c140, 0x19240000);
326 ram_wr32(fuc, 0x10f830, 0x00300017);
327 nvc0_ram_train(fuc, 0x80021001);
328 nvc0_ram_train(fuc, 0x80081001);
329 ram_wr32(fuc, 0x10f340, 0x00500004);
330 ram_nsec(fuc, 1000);
331 ram_wr32(fuc, 0x10f830, 0x01300017);
332 ram_wr32(fuc, 0x10f830, 0x00300017);
333
334
335 ram_wr32(fuc, 0x100b0c, 0x00080028);
336 ram_wr32(fuc, 0x611200, 0x00003330);
337 } else {
338 ram_wr32(fuc, 0x10f800, 0x00001800);
339 ram_wr32(fuc, 0x13d8f4, 0x00000000);
340 ram_wr32(fuc, 0x1373ec, 0x00020404);
341 ram_wr32(fuc, 0x1373f0, 0x00000003);
342 ram_wr32(fuc, 0x10f830, 0x40700010);
343 ram_wr32(fuc, 0x10f830, 0x40500010);
344 ram_wr32(fuc, 0x13d8f4, 0x00000000);
345 ram_wr32(fuc, 0x1373f8, 0x00000000);
346 ram_wr32(fuc, 0x132100, 0x00000101);
347 ram_wr32(fuc, 0x137310, 0x89201616);
348 ram_wr32(fuc, 0x10f050, 0xff000090);
349 ram_wr32(fuc, 0x1373ec, 0x00030404);
350 ram_wr32(fuc, 0x1373f0, 0x00000002);
351
352 ram_wr32(fuc, 0x132100, 0x00000001);
353 ram_wr32(fuc, 0x1373f8, 0x00002000);
354 ram_nsec(fuc, 2000);
355 ram_wr32(fuc, 0x10f808, 0x7aaa0050);
356 ram_wr32(fuc, 0x10f830, 0x00500010);
357 ram_wr32(fuc, 0x10f200, 0x00ce1000);
358 ram_wr32(fuc, 0x10f090, 0x4000007e);
359 ram_nsec(fuc, 2000);
360 ram_wr32(fuc, 0x10f314, 0x00000001);
361 ram_wr32(fuc, 0x10f210, 0x80000000);
362 ram_wr32(fuc, 0x10f338, 0x00300200);
363 ram_wr32(fuc, 0x10f300, 0x0000084d);
364 ram_nsec(fuc, 1000);
365 ram_wr32(fuc, 0x10f290, 0x0b343825);
366 ram_wr32(fuc, 0x10f294, 0x3483028e);
367 ram_wr32(fuc, 0x10f298, 0x440c0600);
368 ram_wr32(fuc, 0x10f29c, 0x0000214c);
369 ram_wr32(fuc, 0x10f2a0, 0x42e20069);
370 ram_wr32(fuc, 0x10f200, 0x00ce0000);
371 ram_wr32(fuc, 0x10f614, 0x60044e77);
372 ram_wr32(fuc, 0x10f610, 0x60044e77);
373 ram_wr32(fuc, 0x10f340, 0x00500000);
374 ram_nsec(fuc, 1000);
375 ram_wr32(fuc, 0x10f344, 0x00600228);
376 ram_nsec(fuc, 1000);
377 ram_wr32(fuc, 0x10f348, 0x00700000);
378 ram_wr32(fuc, 0x13d8f4, 0x00000000);
379 ram_wr32(fuc, 0x61c140, 0x09a40000);
380
381 nvc0_ram_train(fuc, 0x800e1008);
382
383 ram_nsec(fuc, 1000);
384 ram_wr32(fuc, 0x10f800, 0x00001804);
385
386
387 ram_wr32(fuc, 0x13d8f4, 0x00000000);
388 ram_wr32(fuc, 0x100b0c, 0x00080028);
389 ram_wr32(fuc, 0x611200, 0x00003330);
390 ram_nsec(fuc, 100000);
391 ram_wr32(fuc, 0x10f9b0, 0x05313f41);
392 ram_wr32(fuc, 0x10f9b4, 0x00002f50);
393
394 nvc0_ram_train(fuc, 0x010c1001);
395 }
396
397 ram_mask(fuc, 0x10f200, 0x00000800, 0x00000800);
398
399
400 if (mode == 0)
401 ram_mask(fuc, 0x132000, 0x00000001, 0x00000000);
402 return 0;
403}
404
405static int
406nvc0_ram_prog(struct nouveau_fb *pfb)
407{
408 struct nouveau_device *device = nv_device(pfb);
409 struct nvc0_ram *ram = (void *)pfb->ram;
410 struct nvc0_ramfuc *fuc = &ram->fuc;
411 ram_exec(fuc, nouveau_boolopt(device->cfgopt, "NvMemExec", true));
412 return 0;
413}
414
415static void
416nvc0_ram_tidy(struct nouveau_fb *pfb)
417{
418 struct nvc0_ram *ram = (void *)pfb->ram;
419 struct nvc0_ramfuc *fuc = &ram->fuc;
420 ram_exec(fuc, false);
421}
422
423extern const u8 nvc0_pte_storage_type_map[256];
424
425void
426nvc0_ram_put(struct nouveau_fb *pfb, struct nouveau_mem **pmem)
427{
428 struct nouveau_ltc *ltc = nouveau_ltc(pfb);
429 struct nouveau_mem *mem = *pmem;
430
431 *pmem = NULL;
432 if (unlikely(mem == NULL))
433 return;
434
435 mutex_lock(&pfb->base.mutex);
436 if (mem->tag)
437 ltc->tags_free(ltc, &mem->tag);
438 __nv50_ram_put(pfb, mem);
439 mutex_unlock(&pfb->base.mutex);
440
441 kfree(mem);
442}
443
444int
445nvc0_ram_get(struct nouveau_fb *pfb, u64 size, u32 align, u32 ncmin,
446 u32 memtype, struct nouveau_mem **pmem)
447{
448 struct nouveau_mm *mm = &pfb->vram;
449 struct nouveau_mm_node *r;
450 struct nouveau_mem *mem;
451 int type = (memtype & 0x0ff);
452 int back = (memtype & 0x800);
453 const bool comp = nvc0_pte_storage_type_map[type] != type;
454 int ret;
455
456 size >>= 12;
457 align >>= 12;
458 ncmin >>= 12;
459 if (!ncmin)
460 ncmin = size;
461
462 mem = kzalloc(sizeof(*mem), GFP_KERNEL);
463 if (!mem)
464 return -ENOMEM;
465
466 INIT_LIST_HEAD(&mem->regions);
467 mem->size = size;
468
469 mutex_lock(&pfb->base.mutex);
470 if (comp) {
471 struct nouveau_ltc *ltc = nouveau_ltc(pfb);
472
473
474 if (align == (1 << (17 - 12))) {
475 int n = size >> 5;
476 ltc->tags_alloc(ltc, n, &mem->tag);
477 }
478
479 if (unlikely(!mem->tag))
480 type = nvc0_pte_storage_type_map[type];
481 }
482 mem->memtype = type;
483
484 do {
485 if (back)
486 ret = nouveau_mm_tail(mm, 1, size, ncmin, align, &r);
487 else
488 ret = nouveau_mm_head(mm, 1, size, ncmin, align, &r);
489 if (ret) {
490 mutex_unlock(&pfb->base.mutex);
491 pfb->ram->put(pfb, &mem);
492 return ret;
493 }
494
495 list_add_tail(&r->rl_entry, &mem->regions);
496 size -= r->length;
497 } while (size);
498 mutex_unlock(&pfb->base.mutex);
499
500 r = list_first_entry(&mem->regions, struct nouveau_mm_node, rl_entry);
501 mem->offset = (u64)r->offset << 12;
502 *pmem = mem;
503 return 0;
504}
505
506int
507nvc0_ram_create_(struct nouveau_object *parent, struct nouveau_object *engine,
508 struct nouveau_oclass *oclass, u32 maskaddr, int size,
509 void **pobject)
510{
511 struct nouveau_fb *pfb = nouveau_fb(parent);
512 struct nouveau_bios *bios = nouveau_bios(pfb);
513 struct nouveau_ram *ram;
514 const u32 rsvd_head = ( 256 * 1024) >> 12;
515 const u32 rsvd_tail = (1024 * 1024) >> 12;
516 u32 parts = nv_rd32(pfb, 0x022438);
517 u32 pmask = nv_rd32(pfb, maskaddr);
518 u32 bsize = nv_rd32(pfb, 0x10f20c);
519 u32 offset, length;
520 bool uniform = true;
521 int ret, part;
522
523 ret = nouveau_ram_create_(parent, engine, oclass, size, pobject);
524 ram = *pobject;
525 if (ret)
526 return ret;
527
528 nv_debug(pfb, "0x100800: 0x%08x\n", nv_rd32(pfb, 0x100800));
529 nv_debug(pfb, "parts 0x%08x mask 0x%08x\n", parts, pmask);
530
531 ram->type = nouveau_fb_bios_memtype(bios);
532 ram->ranks = (nv_rd32(pfb, 0x10f200) & 0x00000004) ? 2 : 1;
533
534
535 for (part = 0; part < parts; part++) {
536 if (!(pmask & (1 << part))) {
537 u32 psize = nv_rd32(pfb, 0x11020c + (part * 0x1000));
538 if (psize != bsize) {
539 if (psize < bsize)
540 bsize = psize;
541 uniform = false;
542 }
543
544 nv_debug(pfb, "%d: mem_amount 0x%08x\n", part, psize);
545 ram->size += (u64)psize << 20;
546 }
547 }
548
549
550 if (uniform) {
551 offset = rsvd_head;
552 length = (ram->size >> 12) - rsvd_head - rsvd_tail;
553 ret = nouveau_mm_init(&pfb->vram, offset, length, 1);
554 } else {
555
556 ret = nouveau_mm_init(&pfb->vram, rsvd_head,
557 (bsize << 8) * parts - rsvd_head, 1);
558 if (ret)
559 return ret;
560
561
562 offset = (0x0200000000ULL >> 12) + (bsize << 8);
563 length = (ram->size >> 12) - ((bsize * parts) << 8) - rsvd_tail;
564
565 ret = nouveau_mm_init(&pfb->vram, offset, length, 0);
566 if (ret)
567 nouveau_mm_fini(&pfb->vram);
568 }
569
570 if (ret)
571 return ret;
572
573 ram->get = nvc0_ram_get;
574 ram->put = nvc0_ram_put;
575 return 0;
576}
577
578static int
579nvc0_ram_init(struct nouveau_object *object)
580{
581 struct nouveau_fb *pfb = (void *)object->parent;
582 struct nvc0_ram *ram = (void *)object;
583 int ret, i;
584
585 ret = nouveau_ram_init(&ram->base);
586 if (ret)
587 return ret;
588
589
590 switch (ram->base.type) {
591 case NV_MEM_TYPE_GDDR5: {
592 static const u8 train0[] = {
593 0x00, 0xff, 0x55, 0xaa, 0x33, 0xcc,
594 0x00, 0xff, 0xff, 0x00, 0xff, 0x00,
595 };
596 static const u32 train1[] = {
597 0x00000000, 0xffffffff,
598 0x55555555, 0xaaaaaaaa,
599 0x33333333, 0xcccccccc,
600 0xf0f0f0f0, 0x0f0f0f0f,
601 0x00ff00ff, 0xff00ff00,
602 0x0000ffff, 0xffff0000,
603 };
604
605 for (i = 0; i < 0x30; i++) {
606 nv_wr32(pfb, 0x10f968, 0x00000000 | (i << 8));
607 nv_wr32(pfb, 0x10f96c, 0x00000000 | (i << 8));
608 nv_wr32(pfb, 0x10f920, 0x00000100 | train0[i % 12]);
609 nv_wr32(pfb, 0x10f924, 0x00000100 | train0[i % 12]);
610 nv_wr32(pfb, 0x10f918, train1[i % 12]);
611 nv_wr32(pfb, 0x10f91c, train1[i % 12]);
612 nv_wr32(pfb, 0x10f920, 0x00000000 | train0[i % 12]);
613 nv_wr32(pfb, 0x10f924, 0x00000000 | train0[i % 12]);
614 nv_wr32(pfb, 0x10f918, train1[i % 12]);
615 nv_wr32(pfb, 0x10f91c, train1[i % 12]);
616 }
617 } break;
618 default:
619 break;
620 }
621
622 return 0;
623}
624
625static int
626nvc0_ram_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
627 struct nouveau_oclass *oclass, void *data, u32 size,
628 struct nouveau_object **pobject)
629{
630 struct nouveau_bios *bios = nouveau_bios(parent);
631 struct nvc0_ram *ram;
632 int ret;
633
634 ret = nvc0_ram_create(parent, engine, oclass, 0x022554, &ram);
635 *pobject = nv_object(ram);
636 if (ret)
637 return ret;
638
639 ret = nvbios_pll_parse(bios, 0x0c, &ram->refpll);
640 if (ret) {
641 nv_error(ram, "mclk refpll data not found\n");
642 return ret;
643 }
644
645 ret = nvbios_pll_parse(bios, 0x04, &ram->mempll);
646 if (ret) {
647 nv_error(ram, "mclk pll data not found\n");
648 return ret;
649 }
650
651 switch (ram->base.type) {
652 case NV_MEM_TYPE_GDDR5:
653 ram->base.calc = nvc0_ram_calc;
654 ram->base.prog = nvc0_ram_prog;
655 ram->base.tidy = nvc0_ram_tidy;
656 break;
657 default:
658 nv_warn(ram, "reclocking of this ram type unsupported\n");
659 return 0;
660 }
661
662 ram->fuc.r_0x10fe20 = ramfuc_reg(0x10fe20);
663 ram->fuc.r_0x10fe24 = ramfuc_reg(0x10fe24);
664 ram->fuc.r_0x137320 = ramfuc_reg(0x137320);
665 ram->fuc.r_0x137330 = ramfuc_reg(0x137330);
666
667 ram->fuc.r_0x132000 = ramfuc_reg(0x132000);
668 ram->fuc.r_0x132004 = ramfuc_reg(0x132004);
669 ram->fuc.r_0x132100 = ramfuc_reg(0x132100);
670
671 ram->fuc.r_0x137390 = ramfuc_reg(0x137390);
672
673 ram->fuc.r_0x10f290 = ramfuc_reg(0x10f290);
674 ram->fuc.r_0x10f294 = ramfuc_reg(0x10f294);
675 ram->fuc.r_0x10f298 = ramfuc_reg(0x10f298);
676 ram->fuc.r_0x10f29c = ramfuc_reg(0x10f29c);
677 ram->fuc.r_0x10f2a0 = ramfuc_reg(0x10f2a0);
678
679 ram->fuc.r_0x10f300 = ramfuc_reg(0x10f300);
680 ram->fuc.r_0x10f338 = ramfuc_reg(0x10f338);
681 ram->fuc.r_0x10f340 = ramfuc_reg(0x10f340);
682 ram->fuc.r_0x10f344 = ramfuc_reg(0x10f344);
683 ram->fuc.r_0x10f348 = ramfuc_reg(0x10f348);
684
685 ram->fuc.r_0x10f910 = ramfuc_reg(0x10f910);
686 ram->fuc.r_0x10f914 = ramfuc_reg(0x10f914);
687
688 ram->fuc.r_0x100b0c = ramfuc_reg(0x100b0c);
689 ram->fuc.r_0x10f050 = ramfuc_reg(0x10f050);
690 ram->fuc.r_0x10f090 = ramfuc_reg(0x10f090);
691 ram->fuc.r_0x10f200 = ramfuc_reg(0x10f200);
692 ram->fuc.r_0x10f210 = ramfuc_reg(0x10f210);
693 ram->fuc.r_0x10f310 = ramfuc_reg(0x10f310);
694 ram->fuc.r_0x10f314 = ramfuc_reg(0x10f314);
695 ram->fuc.r_0x10f610 = ramfuc_reg(0x10f610);
696 ram->fuc.r_0x10f614 = ramfuc_reg(0x10f614);
697 ram->fuc.r_0x10f800 = ramfuc_reg(0x10f800);
698 ram->fuc.r_0x10f808 = ramfuc_reg(0x10f808);
699 ram->fuc.r_0x10f824 = ramfuc_reg(0x10f824);
700 ram->fuc.r_0x10f830 = ramfuc_reg(0x10f830);
701 ram->fuc.r_0x10f988 = ramfuc_reg(0x10f988);
702 ram->fuc.r_0x10f98c = ramfuc_reg(0x10f98c);
703 ram->fuc.r_0x10f990 = ramfuc_reg(0x10f990);
704 ram->fuc.r_0x10f998 = ramfuc_reg(0x10f998);
705 ram->fuc.r_0x10f9b0 = ramfuc_reg(0x10f9b0);
706 ram->fuc.r_0x10f9b4 = ramfuc_reg(0x10f9b4);
707 ram->fuc.r_0x10fb04 = ramfuc_reg(0x10fb04);
708 ram->fuc.r_0x10fb08 = ramfuc_reg(0x10fb08);
709 ram->fuc.r_0x137310 = ramfuc_reg(0x137300);
710 ram->fuc.r_0x137310 = ramfuc_reg(0x137310);
711 ram->fuc.r_0x137360 = ramfuc_reg(0x137360);
712 ram->fuc.r_0x1373ec = ramfuc_reg(0x1373ec);
713 ram->fuc.r_0x1373f0 = ramfuc_reg(0x1373f0);
714 ram->fuc.r_0x1373f8 = ramfuc_reg(0x1373f8);
715
716 ram->fuc.r_0x61c140 = ramfuc_reg(0x61c140);
717 ram->fuc.r_0x611200 = ramfuc_reg(0x611200);
718
719 ram->fuc.r_0x13d8f4 = ramfuc_reg(0x13d8f4);
720 return 0;
721}
722
723struct nouveau_oclass
724nvc0_ram_oclass = {
725 .handle = 0,
726 .ofuncs = &(struct nouveau_ofuncs) {
727 .ctor = nvc0_ram_ctor,
728 .dtor = _nouveau_ram_dtor,
729 .init = nvc0_ram_init,
730 .fini = _nouveau_ram_fini,
731 }
732};
733