LXR linux/drivers/gpu/drm/radeon/dce3_1

   1/*
   2 * Copyright 2013 Advanced Micro Devices, Inc.
   3 * Copyright 2014 Rafał Miłecki
   4 *
   5 * Permission is hereby granted, free of charge, to any person obtaining a
   6 * copy of this software and associated documentation files (the "Software"),
   7 * to deal in the Software without restriction, including without limitation
   8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9 * and/or sell copies of the Software, and to permit persons to whom the
  10 * Software is furnished to do so, subject to the following conditions:
  11 *
  12 * The above copyright notice and this permission notice shall be included in
  13 * all copies or substantial portions of the Software.
  14 *
  15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21 * OTHER DEALINGS IN THE SOFTWARE.
  22 */
  23#include <linux/hdmi.h>
  24#include <drm/drmP.h>
  25#include "radeon.h"
  26#include "radeon_asic.h"
  27#include "r600d.h"
  28
  29static void dce3_2_afmt_write_speaker_allocation(struct drm_encoder *encoder)
  30{
  31        struct radeon_device *rdev = encoder->dev->dev_private;
  32        struct drm_connector *connector;
  33        struct radeon_connector *radeon_connector = NULL;
  34        u32 tmp;
  35        u8 *sadb;
  36        int sad_count;
  37
  38        list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
  39                if (connector->encoder == encoder) {
  40                        radeon_connector = to_radeon_connector(connector);
  41                        break;
  42                }
  43        }
  44
  45        if (!radeon_connector) {
  46                DRM_ERROR("Couldn't find encoder's connector\n");
  47                return;
  48        }
  49
  50        sad_count = drm_edid_to_speaker_allocation(radeon_connector->edid, &sadb);
  51        if (sad_count < 0) {
  52                DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);
  53                return;
  54        }
  55
  56        /* program the speaker allocation */
  57        tmp = RREG32(AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER);
  58        tmp &= ~(DP_CONNECTION | SPEAKER_ALLOCATION_MASK);
  59        /* set HDMI mode */
  60        tmp |= HDMI_CONNECTION;
  61        if (sad_count)
  62                tmp |= SPEAKER_ALLOCATION(sadb[0]);
  63        else
  64                tmp |= SPEAKER_ALLOCATION(5); /* stereo */
  65        WREG32(AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER, tmp);
  66
  67        kfree(sadb);
  68}
  69
  70static void dce3_2_afmt_write_sad_regs(struct drm_encoder *encoder)
  71{
  72        struct radeon_device *rdev = encoder->dev->dev_private;
  73        struct drm_connector *connector;
  74        struct radeon_connector *radeon_connector = NULL;
  75        struct cea_sad *sads;
  76        int i, sad_count;
  77
  78        static const u16 eld_reg_to_type[][2] = {
  79                { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
  80                { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
  81                { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
  82                { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
  83                { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
  84                { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
  85                { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
  86                { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
  87                { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
  88                { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
  89                { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
  90                { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
  91        };
  92
  93        list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
  94                if (connector->encoder == encoder) {
  95                        radeon_connector = to_radeon_connector(connector);
  96                        break;
  97                }
  98        }
  99
 100        if (!radeon_connector) {
 101                DRM_ERROR("Couldn't find encoder's connector\n");
 102                return;
 103        }
 104
 105        sad_count = drm_edid_to_sad(radeon_connector->edid, &sads);
 106        if (sad_count < 0) {
 107                DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
 108                return;
 109        }
 110        BUG_ON(!sads);
 111
 112        for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
 113                u32 value = 0;
 114                u8 stereo_freqs = 0;
 115                int max_channels = -1;
 116                int j;
 117
 118                for (j = 0; j < sad_count; j++) {
 119                        struct cea_sad *sad = &sads[j];
 120
 121                        if (sad->format == eld_reg_to_type[i][1]) {
 122                                if (sad->channels > max_channels) {
 123                                        value = MAX_CHANNELS(sad->channels) |
 124                                                DESCRIPTOR_BYTE_2(sad->byte2) |
 125                                                SUPPORTED_FREQUENCIES(sad->freq);
 126                                        max_channels = sad->channels;
 127                                }
 128
 129                                if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
 130                                        stereo_freqs |= sad->freq;
 131                                else
 132                                        break;
 133                        }
 134                }
 135
 136                value |= SUPPORTED_FREQUENCIES_STEREO(stereo_freqs);
 137
 138                WREG32(eld_reg_to_type[i][0], value);
 139        }
 140
 141        kfree(sads);
 142}
 143
 144/*
 145 * update the info frames with the data from the current display mode
 146 */
 147void dce3_1_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode)
 148{
 149        struct drm_device *dev = encoder->dev;
 150        struct radeon_device *rdev = dev->dev_private;
 151        struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 152        struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 153        u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
 154        struct hdmi_avi_infoframe frame;
 155        uint32_t offset;
 156        ssize_t err;
 157
 158        if (!dig || !dig->afmt)
 159                return;
 160
 161        /* Silent, r600_hdmi_enable will raise WARN for us */
 162        if (!dig->afmt->enabled)
 163                return;
 164        offset = dig->afmt->offset;
 165
 166        /* disable audio prior to setting up hw */
 167        dig->afmt->pin = r600_audio_get_pin(rdev);
 168        r600_audio_enable(rdev, dig->afmt->pin, false);
 169
 170        r600_audio_set_dto(encoder, mode->clock);
 171
 172        WREG32(HDMI0_VBI_PACKET_CONTROL + offset,
 173               HDMI0_NULL_SEND); /* send null packets when required */
 174
 175        WREG32(HDMI0_AUDIO_CRC_CONTROL + offset, 0x1000);
 176
 177        if (ASIC_IS_DCE32(rdev)) {
 178                WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset,
 179                       HDMI0_AUDIO_DELAY_EN(1) | /* default audio delay */
 180                       HDMI0_AUDIO_PACKETS_PER_LINE(3)); /* should be suffient for all audio modes and small enough for all hblanks */
 181                WREG32(AFMT_AUDIO_PACKET_CONTROL + offset,
 182                       AFMT_AUDIO_SAMPLE_SEND | /* send audio packets */
 183                       AFMT_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */
 184        } else {
 185                WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset,
 186                       HDMI0_AUDIO_SAMPLE_SEND | /* send audio packets */
 187                       HDMI0_AUDIO_DELAY_EN(1) | /* default audio delay */
 188                       HDMI0_AUDIO_PACKETS_PER_LINE(3) | /* should be suffient for all audio modes and small enough for all hblanks */
 189                       HDMI0_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */
 190        }
 191
 192        if (ASIC_IS_DCE32(rdev)) {
 193                dce3_2_afmt_write_speaker_allocation(encoder);
 194                dce3_2_afmt_write_sad_regs(encoder);
 195        }
 196
 197        WREG32(HDMI0_ACR_PACKET_CONTROL + offset,
 198               HDMI0_ACR_SOURCE | /* select SW CTS value - XXX verify that hw CTS works on all families */
 199               HDMI0_ACR_AUTO_SEND); /* allow hw to sent ACR packets when required */
 200
 201        WREG32(HDMI0_VBI_PACKET_CONTROL + offset,
 202               HDMI0_NULL_SEND | /* send null packets when required */
 203               HDMI0_GC_SEND | /* send general control packets */
 204               HDMI0_GC_CONT); /* send general control packets every frame */
 205
 206        /* TODO: HDMI0_AUDIO_INFO_UPDATE */
 207        WREG32(HDMI0_INFOFRAME_CONTROL0 + offset,
 208               HDMI0_AVI_INFO_SEND | /* enable AVI info frames */
 209               HDMI0_AVI_INFO_CONT | /* send AVI info frames every frame/field */
 210               HDMI0_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */
 211               HDMI0_AUDIO_INFO_CONT); /* send audio info frames every frame/field */
 212
 213        WREG32(HDMI0_INFOFRAME_CONTROL1 + offset,
 214               HDMI0_AVI_INFO_LINE(2) | /* anything other than 0 */
 215               HDMI0_AUDIO_INFO_LINE(2)); /* anything other than 0 */
 216
 217        WREG32(HDMI0_GC + offset, 0); /* unset HDMI0_GC_AVMUTE */
 218
 219        err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
 220        if (err < 0) {
 221                DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
 222                return;
 223        }
 224
 225        err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
 226        if (err < 0) {
 227                DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
 228                return;
 229        }
 230
 231        r600_hdmi_update_avi_infoframe(encoder, buffer, sizeof(buffer));
 232        r600_hdmi_update_ACR(encoder, mode->clock);
 233
 234        /* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */
 235        WREG32(HDMI0_RAMP_CONTROL0 + offset, 0x00FFFFFF);
 236        WREG32(HDMI0_RAMP_CONTROL1 + offset, 0x007FFFFF);
 237        WREG32(HDMI0_RAMP_CONTROL2 + offset, 0x00000001);
 238        WREG32(HDMI0_RAMP_CONTROL3 + offset, 0x00000001);
 239
 240        r600_hdmi_audio_workaround(encoder);
 241
 242        /* enable audio after to setting up hw */
 243        r600_audio_enable(rdev, dig->afmt->pin, true);
 244}
 245