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27#ifndef _VMXNET3_DEFS_H_
28#define _VMXNET3_DEFS_H_
29
30#include "upt1_defs.h"
31
32
33
34enum {
35 VMXNET3_REG_VRRS = 0x0,
36 VMXNET3_REG_UVRS = 0x8,
37 VMXNET3_REG_DSAL = 0x10,
38 VMXNET3_REG_DSAH = 0x18,
39 VMXNET3_REG_CMD = 0x20,
40 VMXNET3_REG_MACL = 0x28,
41 VMXNET3_REG_MACH = 0x30,
42 VMXNET3_REG_ICR = 0x38,
43 VMXNET3_REG_ECR = 0x40
44};
45
46
47enum {
48 VMXNET3_REG_IMR = 0x0,
49 VMXNET3_REG_TXPROD = 0x600,
50 VMXNET3_REG_RXPROD = 0x800,
51 VMXNET3_REG_RXPROD2 = 0xA00
52};
53
54#define VMXNET3_PT_REG_SIZE 4096
55#define VMXNET3_VD_REG_SIZE 4096
56
57#define VMXNET3_REG_ALIGN 8
58#define VMXNET3_REG_ALIGN_MASK 0x7
59
60
61#define VMXNET3_IO_TYPE_PT 0
62#define VMXNET3_IO_TYPE_VD 1
63#define VMXNET3_IO_ADDR(type, reg) (((type) << 24) | ((reg) & 0xFFFFFF))
64#define VMXNET3_IO_TYPE(addr) ((addr) >> 24)
65#define VMXNET3_IO_REG(addr) ((addr) & 0xFFFFFF)
66
67enum {
68 VMXNET3_CMD_FIRST_SET = 0xCAFE0000,
69 VMXNET3_CMD_ACTIVATE_DEV = VMXNET3_CMD_FIRST_SET,
70 VMXNET3_CMD_QUIESCE_DEV,
71 VMXNET3_CMD_RESET_DEV,
72 VMXNET3_CMD_UPDATE_RX_MODE,
73 VMXNET3_CMD_UPDATE_MAC_FILTERS,
74 VMXNET3_CMD_UPDATE_VLAN_FILTERS,
75 VMXNET3_CMD_UPDATE_RSSIDT,
76 VMXNET3_CMD_UPDATE_IML,
77 VMXNET3_CMD_UPDATE_PMCFG,
78 VMXNET3_CMD_UPDATE_FEATURE,
79 VMXNET3_CMD_LOAD_PLUGIN,
80
81 VMXNET3_CMD_FIRST_GET = 0xF00D0000,
82 VMXNET3_CMD_GET_QUEUE_STATUS = VMXNET3_CMD_FIRST_GET,
83 VMXNET3_CMD_GET_STATS,
84 VMXNET3_CMD_GET_LINK,
85 VMXNET3_CMD_GET_PERM_MAC_LO,
86 VMXNET3_CMD_GET_PERM_MAC_HI,
87 VMXNET3_CMD_GET_DID_LO,
88 VMXNET3_CMD_GET_DID_HI,
89 VMXNET3_CMD_GET_DEV_EXTRA_INFO,
90 VMXNET3_CMD_GET_CONF_INTR
91};
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110
111struct Vmxnet3_TxDesc {
112 __le64 addr;
113
114#ifdef __BIG_ENDIAN_BITFIELD
115 u32 msscof:14;
116 u32 ext1:1;
117 u32 dtype:1;
118 u32 rsvd:1;
119 u32 gen:1;
120 u32 len:14;
121#else
122 u32 len:14;
123 u32 gen:1;
124 u32 rsvd:1;
125 u32 dtype:1;
126 u32 ext1:1;
127 u32 msscof:14;
128#endif
129
130#ifdef __BIG_ENDIAN_BITFIELD
131 u32 tci:16;
132 u32 ti:1;
133 u32 ext2:1;
134 u32 cq:1;
135 u32 eop:1;
136 u32 om:2;
137 u32 hlen:10;
138#else
139 u32 hlen:10;
140 u32 om:2;
141 u32 eop:1;
142 u32 cq:1;
143 u32 ext2:1;
144 u32 ti:1;
145 u32 tci:16;
146#endif
147};
148
149
150#define VMXNET3_OM_NONE 0
151#define VMXNET3_OM_CSUM 2
152#define VMXNET3_OM_TSO 3
153
154
155#define VMXNET3_TXD_EOP_SHIFT 12
156#define VMXNET3_TXD_CQ_SHIFT 13
157#define VMXNET3_TXD_GEN_SHIFT 14
158#define VMXNET3_TXD_EOP_DWORD_SHIFT 3
159#define VMXNET3_TXD_GEN_DWORD_SHIFT 2
160
161#define VMXNET3_TXD_CQ (1 << VMXNET3_TXD_CQ_SHIFT)
162#define VMXNET3_TXD_EOP (1 << VMXNET3_TXD_EOP_SHIFT)
163#define VMXNET3_TXD_GEN (1 << VMXNET3_TXD_GEN_SHIFT)
164
165#define VMXNET3_HDR_COPY_SIZE 128
166
167
168struct Vmxnet3_TxDataDesc {
169 u8 data[VMXNET3_HDR_COPY_SIZE];
170};
171
172#define VMXNET3_TCD_GEN_SHIFT 31
173#define VMXNET3_TCD_GEN_SIZE 1
174#define VMXNET3_TCD_TXIDX_SHIFT 0
175#define VMXNET3_TCD_TXIDX_SIZE 12
176#define VMXNET3_TCD_GEN_DWORD_SHIFT 3
177
178struct Vmxnet3_TxCompDesc {
179 u32 txdIdx:12;
180 u32 ext1:20;
181
182 __le32 ext2;
183 __le32 ext3;
184
185 u32 rsvd:24;
186 u32 type:7;
187 u32 gen:1;
188};
189
190struct Vmxnet3_RxDesc {
191 __le64 addr;
192
193#ifdef __BIG_ENDIAN_BITFIELD
194 u32 gen:1;
195 u32 rsvd:15;
196 u32 dtype:1;
197 u32 btype:1;
198 u32 len:14;
199#else
200 u32 len:14;
201 u32 btype:1;
202 u32 dtype:1;
203 u32 rsvd:15;
204 u32 gen:1;
205#endif
206 u32 ext1;
207};
208
209
210#define VMXNET3_RXD_BTYPE_HEAD 0
211#define VMXNET3_RXD_BTYPE_BODY 1
212
213
214#define VMXNET3_RXD_BTYPE_SHIFT 14
215#define VMXNET3_RXD_GEN_SHIFT 31
216
217struct Vmxnet3_RxCompDesc {
218#ifdef __BIG_ENDIAN_BITFIELD
219 u32 ext2:1;
220 u32 cnc:1;
221 u32 rssType:4;
222 u32 rqID:10;
223 u32 sop:1;
224 u32 eop:1;
225 u32 ext1:2;
226 u32 rxdIdx:12;
227#else
228 u32 rxdIdx:12;
229 u32 ext1:2;
230 u32 eop:1;
231 u32 sop:1;
232 u32 rqID:10;
233 u32 rssType:4;
234 u32 cnc:1;
235 u32 ext2:1;
236#endif
237
238 __le32 rssHash;
239
240#ifdef __BIG_ENDIAN_BITFIELD
241 u32 tci:16;
242 u32 ts:1;
243 u32 err:1;
244 u32 len:14;
245#else
246 u32 len:14;
247 u32 err:1;
248 u32 ts:1;
249 u32 tci:16;
250#endif
251
252
253#ifdef __BIG_ENDIAN_BITFIELD
254 u32 gen:1;
255 u32 type:7;
256 u32 fcs:1;
257 u32 frg:1;
258 u32 v4:1;
259 u32 v6:1;
260 u32 ipc:1;
261 u32 tcp:1;
262 u32 udp:1;
263 u32 tuc:1;
264 u32 csum:16;
265#else
266 u32 csum:16;
267 u32 tuc:1;
268 u32 udp:1;
269 u32 tcp:1;
270 u32 ipc:1;
271 u32 v6:1;
272 u32 v4:1;
273 u32 frg:1;
274 u32 fcs:1;
275 u32 type:7;
276 u32 gen:1;
277#endif
278};
279
280
281#define VMXNET3_RCD_TUC_SHIFT 16
282#define VMXNET3_RCD_IPC_SHIFT 19
283
284
285#define VMXNET3_RCD_TYPE_SHIFT 56
286#define VMXNET3_RCD_GEN_SHIFT 63
287
288
289#define VMXNET3_RCD_CSUM_OK (1 << VMXNET3_RCD_TUC_SHIFT | \
290 1 << VMXNET3_RCD_IPC_SHIFT)
291#define VMXNET3_TXD_GEN_SIZE 1
292#define VMXNET3_TXD_EOP_SIZE 1
293
294
295enum {
296 VMXNET3_RCD_RSS_TYPE_NONE = 0,
297 VMXNET3_RCD_RSS_TYPE_IPV4 = 1,
298 VMXNET3_RCD_RSS_TYPE_TCPIPV4 = 2,
299 VMXNET3_RCD_RSS_TYPE_IPV6 = 3,
300 VMXNET3_RCD_RSS_TYPE_TCPIPV6 = 4,
301};
302
303
304
305union Vmxnet3_GenericDesc {
306 __le64 qword[2];
307 __le32 dword[4];
308 __le16 word[8];
309 struct Vmxnet3_TxDesc txd;
310 struct Vmxnet3_RxDesc rxd;
311 struct Vmxnet3_TxCompDesc tcd;
312 struct Vmxnet3_RxCompDesc rcd;
313};
314
315#define VMXNET3_INIT_GEN 1
316
317
318#define VMXNET3_MAX_TX_BUF_SIZE (1 << 14)
319
320
321#define VMXNET3_TXD_NEEDED(size) (((size) + VMXNET3_MAX_TX_BUF_SIZE - 1) / \
322 VMXNET3_MAX_TX_BUF_SIZE)
323
324
325#define VMXNET3_MAX_TXD_PER_PKT 16
326
327
328#define VMXNET3_MAX_RX_BUF_SIZE ((1 << 14) - 1)
329
330#define VMXNET3_MIN_T0_BUF_SIZE 128
331#define VMXNET3_MAX_CSUM_OFFSET 1024
332
333
334#define VMXNET3_RING_BA_ALIGN 512
335#define VMXNET3_RING_BA_MASK (VMXNET3_RING_BA_ALIGN - 1)
336
337
338#define VMXNET3_RING_SIZE_ALIGN 32
339#define VMXNET3_RING_SIZE_MASK (VMXNET3_RING_SIZE_ALIGN - 1)
340
341
342#define VMXNET3_TX_RING_MAX_SIZE 4096
343#define VMXNET3_TC_RING_MAX_SIZE 4096
344#define VMXNET3_RX_RING_MAX_SIZE 4096
345#define VMXNET3_RC_RING_MAX_SIZE 8192
346
347
348
349enum {
350 VMXNET3_ERR_NOEOP = 0x80000000,
351 VMXNET3_ERR_TXD_REUSE = 0x80000001,
352 VMXNET3_ERR_BIG_PKT = 0x80000002,
353 VMXNET3_ERR_DESC_NOT_SPT = 0x80000003,
354 VMXNET3_ERR_SMALL_BUF = 0x80000004,
355 VMXNET3_ERR_STRESS = 0x80000005,
356 VMXNET3_ERR_SWITCH = 0x80000006,
357 VMXNET3_ERR_TXD_INVALID = 0x80000007,
358};
359
360
361#define VMXNET3_CDTYPE_TXCOMP 0
362#define VMXNET3_CDTYPE_RXCOMP 3
363
364enum {
365 VMXNET3_GOS_BITS_UNK = 0,
366 VMXNET3_GOS_BITS_32 = 1,
367 VMXNET3_GOS_BITS_64 = 2,
368};
369
370#define VMXNET3_GOS_TYPE_LINUX 1
371
372
373struct Vmxnet3_GOSInfo {
374#ifdef __BIG_ENDIAN_BITFIELD
375 u32 gosMisc:10;
376 u32 gosVer:16;
377 u32 gosType:4;
378 u32 gosBits:2;
379#else
380 u32 gosBits:2;
381 u32 gosType:4;
382 u32 gosVer:16;
383 u32 gosMisc:10;
384#endif
385};
386
387struct Vmxnet3_DriverInfo {
388 __le32 version;
389 struct Vmxnet3_GOSInfo gos;
390 __le32 vmxnet3RevSpt;
391 __le32 uptVerSpt;
392};
393
394
395#define VMXNET3_REV1_MAGIC 0xbabefee1
396
397
398
399
400
401
402
403#define VMXNET3_QUEUE_DESC_ALIGN 128
404
405
406struct Vmxnet3_MiscConf {
407 struct Vmxnet3_DriverInfo driverInfo;
408 __le64 uptFeatures;
409 __le64 ddPA;
410 __le64 queueDescPA;
411 __le32 ddLen;
412 __le32 queueDescLen;
413 __le32 mtu;
414 __le16 maxNumRxSG;
415 u8 numTxQueues;
416 u8 numRxQueues;
417 __le32 reserved[4];
418};
419
420
421struct Vmxnet3_TxQueueConf {
422 __le64 txRingBasePA;
423 __le64 dataRingBasePA;
424 __le64 compRingBasePA;
425 __le64 ddPA;
426 __le64 reserved;
427 __le32 txRingSize;
428 __le32 dataRingSize;
429 __le32 compRingSize;
430 __le32 ddLen;
431 u8 intrIdx;
432 u8 _pad[7];
433};
434
435
436struct Vmxnet3_RxQueueConf {
437 __le64 rxRingBasePA[2];
438 __le64 compRingBasePA;
439 __le64 ddPA;
440 __le64 reserved;
441 __le32 rxRingSize[2];
442 __le32 compRingSize;
443 __le32 ddLen;
444 u8 intrIdx;
445 u8 _pad[7];
446};
447
448
449enum vmxnet3_intr_mask_mode {
450 VMXNET3_IMM_AUTO = 0,
451 VMXNET3_IMM_ACTIVE = 1,
452 VMXNET3_IMM_LAZY = 2
453};
454
455enum vmxnet3_intr_type {
456 VMXNET3_IT_AUTO = 0,
457 VMXNET3_IT_INTX = 1,
458 VMXNET3_IT_MSI = 2,
459 VMXNET3_IT_MSIX = 3
460};
461
462#define VMXNET3_MAX_TX_QUEUES 8
463#define VMXNET3_MAX_RX_QUEUES 16
464
465#define VMXNET3_MAX_INTRS 25
466
467
468#define VMXNET3_IC_DISABLE_ALL 0x1
469
470
471struct Vmxnet3_IntrConf {
472 bool autoMask;
473 u8 numIntrs;
474 u8 eventIntrIdx;
475 u8 modLevels[VMXNET3_MAX_INTRS];
476
477 __le32 intrCtrl;
478 __le32 reserved[2];
479};
480
481
482#define VMXNET3_VFT_SIZE (4096 / (sizeof(u32) * 8))
483
484
485struct Vmxnet3_QueueStatus {
486 bool stopped;
487 u8 _pad[3];
488 __le32 error;
489};
490
491
492struct Vmxnet3_TxQueueCtrl {
493 __le32 txNumDeferred;
494 __le32 txThreshold;
495 __le64 reserved;
496};
497
498
499struct Vmxnet3_RxQueueCtrl {
500 bool updateRxProd;
501 u8 _pad[7];
502 __le64 reserved;
503};
504
505enum {
506 VMXNET3_RXM_UCAST = 0x01,
507 VMXNET3_RXM_MCAST = 0x02,
508 VMXNET3_RXM_BCAST = 0x04,
509 VMXNET3_RXM_ALL_MULTI = 0x08,
510 VMXNET3_RXM_PROMISC = 0x10
511};
512
513struct Vmxnet3_RxFilterConf {
514 __le32 rxMode;
515 __le16 mfTableLen;
516 __le16 _pad1;
517 __le64 mfTablePA;
518 __le32 vfTable[VMXNET3_VFT_SIZE];
519};
520
521
522#define VMXNET3_PM_MAX_FILTERS 6
523#define VMXNET3_PM_MAX_PATTERN_SIZE 128
524#define VMXNET3_PM_MAX_MASK_SIZE (VMXNET3_PM_MAX_PATTERN_SIZE / 8)
525
526#define VMXNET3_PM_WAKEUP_MAGIC cpu_to_le16(0x01)
527#define VMXNET3_PM_WAKEUP_FILTER cpu_to_le16(0x02)
528
529
530
531struct Vmxnet3_PM_PktFilter {
532 u8 maskSize;
533 u8 patternSize;
534 u8 mask[VMXNET3_PM_MAX_MASK_SIZE];
535 u8 pattern[VMXNET3_PM_MAX_PATTERN_SIZE];
536 u8 pad[6];
537};
538
539
540struct Vmxnet3_PMConf {
541 __le16 wakeUpEvents;
542 u8 numFilters;
543 u8 pad[5];
544 struct Vmxnet3_PM_PktFilter filters[VMXNET3_PM_MAX_FILTERS];
545};
546
547
548struct Vmxnet3_VariableLenConfDesc {
549 __le32 confVer;
550 __le32 confLen;
551 __le64 confPA;
552};
553
554
555struct Vmxnet3_TxQueueDesc {
556 struct Vmxnet3_TxQueueCtrl ctrl;
557 struct Vmxnet3_TxQueueConf conf;
558
559
560 struct Vmxnet3_QueueStatus status;
561 struct UPT1_TxStats stats;
562 u8 _pad[88];
563};
564
565
566struct Vmxnet3_RxQueueDesc {
567 struct Vmxnet3_RxQueueCtrl ctrl;
568 struct Vmxnet3_RxQueueConf conf;
569
570 struct Vmxnet3_QueueStatus status;
571 struct UPT1_RxStats stats;
572 u8 __pad[88];
573};
574
575
576struct Vmxnet3_DSDevRead {
577
578 struct Vmxnet3_MiscConf misc;
579 struct Vmxnet3_IntrConf intrConf;
580 struct Vmxnet3_RxFilterConf rxFilterConf;
581 struct Vmxnet3_VariableLenConfDesc rssConfDesc;
582 struct Vmxnet3_VariableLenConfDesc pmConfDesc;
583 struct Vmxnet3_VariableLenConfDesc pluginConfDesc;
584};
585
586
587struct Vmxnet3_DriverShared {
588 __le32 magic;
589
590 __le32 pad;
591 struct Vmxnet3_DSDevRead devRead;
592 __le32 ecr;
593 __le32 reserved[5];
594};
595
596
597#define VMXNET3_ECR_RQERR (1 << 0)
598#define VMXNET3_ECR_TQERR (1 << 1)
599#define VMXNET3_ECR_LINK (1 << 2)
600#define VMXNET3_ECR_DIC (1 << 3)
601#define VMXNET3_ECR_DEBUG (1 << 4)
602
603
604#define VMXNET3_FLIP_RING_GEN(gen) ((gen) = (gen) ^ 0x1)
605
606
607#define VMXNET3_INC_RING_IDX_ONLY(idx, ring_size) \
608 do {\
609 (idx)++;\
610 if (unlikely((idx) == (ring_size))) {\
611 (idx) = 0;\
612 } \
613 } while (0)
614
615#define VMXNET3_SET_VFTABLE_ENTRY(vfTable, vid) \
616 (vfTable[vid >> 5] |= (1 << (vid & 31)))
617#define VMXNET3_CLEAR_VFTABLE_ENTRY(vfTable, vid) \
618 (vfTable[vid >> 5] &= ~(1 << (vid & 31)))
619
620#define VMXNET3_VFTABLE_ENTRY_IS_SET(vfTable, vid) \
621 ((vfTable[vid >> 5] & (1 << (vid & 31))) != 0)
622
623#define VMXNET3_MAX_MTU 9000
624#define VMXNET3_MIN_MTU 60
625
626#define VMXNET3_LINK_UP (10000 << 16 | 1)
627#define VMXNET3_LINK_DOWN 0
628
629#endif
630