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19#include <linux/module.h>
20#include <linux/platform_device.h>
21#include <linux/slab.h>
22#include <linux/phy/phy.h>
23#include <linux/of.h>
24#include <linux/clk.h>
25#include <linux/err.h>
26#include <linux/io.h>
27#include <linux/pm_runtime.h>
28#include <linux/delay.h>
29#include <linux/phy/omap_control_phy.h>
30#include <linux/of_platform.h>
31
32#define PLL_STATUS 0x00000004
33#define PLL_GO 0x00000008
34#define PLL_CONFIGURATION1 0x0000000C
35#define PLL_CONFIGURATION2 0x00000010
36#define PLL_CONFIGURATION3 0x00000014
37#define PLL_CONFIGURATION4 0x00000020
38
39#define PLL_REGM_MASK 0x001FFE00
40#define PLL_REGM_SHIFT 0x9
41#define PLL_REGM_F_MASK 0x0003FFFF
42#define PLL_REGM_F_SHIFT 0x0
43#define PLL_REGN_MASK 0x000001FE
44#define PLL_REGN_SHIFT 0x1
45#define PLL_SELFREQDCO_MASK 0x0000000E
46#define PLL_SELFREQDCO_SHIFT 0x1
47#define PLL_SD_MASK 0x0003FC00
48#define PLL_SD_SHIFT 10
49#define SET_PLL_GO 0x1
50#define PLL_LDOPWDN BIT(15)
51#define PLL_TICOPWDN BIT(16)
52#define PLL_LOCK 0x2
53#define PLL_IDLE 0x1
54
55
56
57
58
59
60#define PLL_IDLE_TIME 100
61#define PLL_LOCK_TIME 100
62
63struct pipe3_dpll_params {
64 u16 m;
65 u8 n;
66 u8 freq:3;
67 u8 sd;
68 u32 mf;
69};
70
71struct pipe3_dpll_map {
72 unsigned long rate;
73 struct pipe3_dpll_params params;
74};
75
76struct ti_pipe3 {
77 void __iomem *pll_ctrl_base;
78 struct device *dev;
79 struct device *control_dev;
80 struct clk *wkupclk;
81 struct clk *sys_clk;
82 struct clk *refclk;
83 struct clk *div_clk;
84 struct pipe3_dpll_map *dpll_map;
85 u8 id;
86};
87
88static struct pipe3_dpll_map dpll_map_usb[] = {
89 {12000000, {1250, 5, 4, 20, 0} },
90 {16800000, {3125, 20, 4, 20, 0} },
91 {19200000, {1172, 8, 4, 20, 65537} },
92 {20000000, {1000, 7, 4, 10, 0} },
93 {26000000, {1250, 12, 4, 20, 0} },
94 {38400000, {3125, 47, 4, 20, 92843} },
95 { },
96};
97
98static struct pipe3_dpll_map dpll_map_sata[] = {
99 {12000000, {1000, 7, 4, 6, 0} },
100 {16800000, {714, 7, 4, 6, 0} },
101 {19200000, {625, 7, 4, 6, 0} },
102 {20000000, {600, 7, 4, 6, 0} },
103 {26000000, {461, 7, 4, 6, 0} },
104 {38400000, {312, 7, 4, 6, 0} },
105 { },
106};
107
108static inline u32 ti_pipe3_readl(void __iomem *addr, unsigned offset)
109{
110 return __raw_readl(addr + offset);
111}
112
113static inline void ti_pipe3_writel(void __iomem *addr, unsigned offset,
114 u32 data)
115{
116 __raw_writel(data, addr + offset);
117}
118
119static struct pipe3_dpll_params *ti_pipe3_get_dpll_params(struct ti_pipe3 *phy)
120{
121 unsigned long rate;
122 struct pipe3_dpll_map *dpll_map = phy->dpll_map;
123
124 rate = clk_get_rate(phy->sys_clk);
125
126 for (; dpll_map->rate; dpll_map++) {
127 if (rate == dpll_map->rate)
128 return &dpll_map->params;
129 }
130
131 dev_err(phy->dev, "No DPLL configuration for %lu Hz SYS CLK\n", rate);
132
133 return NULL;
134}
135
136static int ti_pipe3_power_off(struct phy *x)
137{
138 struct ti_pipe3 *phy = phy_get_drvdata(x);
139
140 omap_control_phy_power(phy->control_dev, 0);
141
142 return 0;
143}
144
145static int ti_pipe3_power_on(struct phy *x)
146{
147 struct ti_pipe3 *phy = phy_get_drvdata(x);
148
149 omap_control_phy_power(phy->control_dev, 1);
150
151 return 0;
152}
153
154static int ti_pipe3_dpll_wait_lock(struct ti_pipe3 *phy)
155{
156 u32 val;
157 unsigned long timeout;
158
159 timeout = jiffies + msecs_to_jiffies(PLL_LOCK_TIME);
160 do {
161 cpu_relax();
162 val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
163 if (val & PLL_LOCK)
164 break;
165 } while (!time_after(jiffies, timeout));
166
167 if (!(val & PLL_LOCK)) {
168 dev_err(phy->dev, "DPLL failed to lock\n");
169 return -EBUSY;
170 }
171
172 return 0;
173}
174
175static int ti_pipe3_dpll_program(struct ti_pipe3 *phy)
176{
177 u32 val;
178 struct pipe3_dpll_params *dpll_params;
179
180 dpll_params = ti_pipe3_get_dpll_params(phy);
181 if (!dpll_params)
182 return -EINVAL;
183
184 val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1);
185 val &= ~PLL_REGN_MASK;
186 val |= dpll_params->n << PLL_REGN_SHIFT;
187 ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val);
188
189 val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
190 val &= ~PLL_SELFREQDCO_MASK;
191 val |= dpll_params->freq << PLL_SELFREQDCO_SHIFT;
192 ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);
193
194 val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1);
195 val &= ~PLL_REGM_MASK;
196 val |= dpll_params->m << PLL_REGM_SHIFT;
197 ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val);
198
199 val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION4);
200 val &= ~PLL_REGM_F_MASK;
201 val |= dpll_params->mf << PLL_REGM_F_SHIFT;
202 ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION4, val);
203
204 val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION3);
205 val &= ~PLL_SD_MASK;
206 val |= dpll_params->sd << PLL_SD_SHIFT;
207 ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION3, val);
208
209 ti_pipe3_writel(phy->pll_ctrl_base, PLL_GO, SET_PLL_GO);
210
211 return ti_pipe3_dpll_wait_lock(phy);
212}
213
214static int ti_pipe3_init(struct phy *x)
215{
216 struct ti_pipe3 *phy = phy_get_drvdata(x);
217 u32 val;
218 int ret = 0;
219
220 if (of_device_is_compatible(phy->dev->of_node, "ti,phy-pipe3-pcie")) {
221 omap_control_pcie_pcs(phy->control_dev, phy->id, 0xF1);
222 return 0;
223 }
224
225
226 val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
227 if (val & PLL_IDLE) {
228 val &= ~PLL_IDLE;
229 ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);
230 ret = ti_pipe3_dpll_wait_lock(phy);
231 }
232
233
234 val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
235 if (!(val & PLL_LOCK))
236 if (ti_pipe3_dpll_program(phy))
237 return -EINVAL;
238
239 return ret;
240}
241
242static int ti_pipe3_exit(struct phy *x)
243{
244 struct ti_pipe3 *phy = phy_get_drvdata(x);
245 u32 val;
246 unsigned long timeout;
247
248
249
250
251 if (of_device_is_compatible(phy->dev->of_node, "ti,phy-pipe3-sata") ||
252 of_device_is_compatible(phy->dev->of_node, "ti,phy-pipe3-pcie"))
253 return 0;
254
255
256 val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
257 val |= PLL_IDLE;
258 ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);
259
260
261 timeout = jiffies + msecs_to_jiffies(PLL_IDLE_TIME);
262 do {
263 cpu_relax();
264 val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
265 if ((val & PLL_TICOPWDN) && (val & PLL_LDOPWDN))
266 break;
267 } while (!time_after(jiffies, timeout));
268
269 if (!(val & PLL_TICOPWDN) || !(val & PLL_LDOPWDN)) {
270 dev_err(phy->dev, "Failed to power down: PLL_STATUS 0x%x\n",
271 val);
272 return -EBUSY;
273 }
274
275 return 0;
276}
277static struct phy_ops ops = {
278 .init = ti_pipe3_init,
279 .exit = ti_pipe3_exit,
280 .power_on = ti_pipe3_power_on,
281 .power_off = ti_pipe3_power_off,
282 .owner = THIS_MODULE,
283};
284
285#ifdef CONFIG_OF
286static const struct of_device_id ti_pipe3_id_table[];
287#endif
288
289static int ti_pipe3_probe(struct platform_device *pdev)
290{
291 struct ti_pipe3 *phy;
292 struct phy *generic_phy;
293 struct phy_provider *phy_provider;
294 struct resource *res;
295 struct device_node *node = pdev->dev.of_node;
296 struct device_node *control_node;
297 struct platform_device *control_pdev;
298 const struct of_device_id *match;
299 struct clk *clk;
300
301 phy = devm_kzalloc(&pdev->dev, sizeof(*phy), GFP_KERNEL);
302 if (!phy) {
303 dev_err(&pdev->dev, "unable to alloc mem for TI PIPE3 PHY\n");
304 return -ENOMEM;
305 }
306 phy->dev = &pdev->dev;
307
308 if (!of_device_is_compatible(node, "ti,phy-pipe3-pcie")) {
309 match = of_match_device(of_match_ptr(ti_pipe3_id_table),
310 &pdev->dev);
311 if (!match)
312 return -EINVAL;
313
314 phy->dpll_map = (struct pipe3_dpll_map *)match->data;
315 if (!phy->dpll_map) {
316 dev_err(&pdev->dev, "no DPLL data\n");
317 return -EINVAL;
318 }
319
320 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
321 "pll_ctrl");
322 phy->pll_ctrl_base = devm_ioremap_resource(&pdev->dev, res);
323 if (IS_ERR(phy->pll_ctrl_base))
324 return PTR_ERR(phy->pll_ctrl_base);
325
326 phy->sys_clk = devm_clk_get(phy->dev, "sysclk");
327 if (IS_ERR(phy->sys_clk)) {
328 dev_err(&pdev->dev, "unable to get sysclk\n");
329 return -EINVAL;
330 }
331 }
332
333 if (!of_device_is_compatible(node, "ti,phy-pipe3-sata")) {
334 phy->wkupclk = devm_clk_get(phy->dev, "wkupclk");
335 if (IS_ERR(phy->wkupclk)) {
336 dev_err(&pdev->dev, "unable to get wkupclk\n");
337 return PTR_ERR(phy->wkupclk);
338 }
339
340 phy->refclk = devm_clk_get(phy->dev, "refclk");
341 if (IS_ERR(phy->refclk)) {
342 dev_err(&pdev->dev, "unable to get refclk\n");
343 return PTR_ERR(phy->refclk);
344 }
345 } else {
346 phy->wkupclk = ERR_PTR(-ENODEV);
347 phy->refclk = ERR_PTR(-ENODEV);
348 }
349
350 if (of_device_is_compatible(node, "ti,phy-pipe3-pcie")) {
351 if (of_property_read_u8(node, "id", &phy->id) < 0)
352 phy->id = 1;
353
354 clk = devm_clk_get(phy->dev, "dpll_ref");
355 if (IS_ERR(clk)) {
356 dev_err(&pdev->dev, "unable to get dpll ref clk\n");
357 return PTR_ERR(clk);
358 }
359 clk_set_rate(clk, 1500000000);
360
361 clk = devm_clk_get(phy->dev, "dpll_ref_m2");
362 if (IS_ERR(clk)) {
363 dev_err(&pdev->dev, "unable to get dpll ref m2 clk\n");
364 return PTR_ERR(clk);
365 }
366 clk_set_rate(clk, 100000000);
367
368 clk = devm_clk_get(phy->dev, "phy-div");
369 if (IS_ERR(clk)) {
370 dev_err(&pdev->dev, "unable to get phy-div clk\n");
371 return PTR_ERR(clk);
372 }
373 clk_set_rate(clk, 100000000);
374
375 phy->div_clk = devm_clk_get(phy->dev, "div-clk");
376 if (IS_ERR(phy->div_clk)) {
377 dev_err(&pdev->dev, "unable to get div-clk\n");
378 return PTR_ERR(phy->div_clk);
379 }
380 } else {
381 phy->div_clk = ERR_PTR(-ENODEV);
382 }
383
384 control_node = of_parse_phandle(node, "ctrl-module", 0);
385 if (!control_node) {
386 dev_err(&pdev->dev, "Failed to get control device phandle\n");
387 return -EINVAL;
388 }
389
390 control_pdev = of_find_device_by_node(control_node);
391 if (!control_pdev) {
392 dev_err(&pdev->dev, "Failed to get control device\n");
393 return -EINVAL;
394 }
395
396 phy->control_dev = &control_pdev->dev;
397
398 omap_control_phy_power(phy->control_dev, 0);
399
400 platform_set_drvdata(pdev, phy);
401 pm_runtime_enable(phy->dev);
402
403 generic_phy = devm_phy_create(phy->dev, NULL, &ops, NULL);
404 if (IS_ERR(generic_phy))
405 return PTR_ERR(generic_phy);
406
407 phy_set_drvdata(generic_phy, phy);
408 phy_provider = devm_of_phy_provider_register(phy->dev,
409 of_phy_simple_xlate);
410 if (IS_ERR(phy_provider))
411 return PTR_ERR(phy_provider);
412
413 pm_runtime_get(&pdev->dev);
414
415 return 0;
416}
417
418static int ti_pipe3_remove(struct platform_device *pdev)
419{
420 if (!pm_runtime_suspended(&pdev->dev))
421 pm_runtime_put(&pdev->dev);
422 pm_runtime_disable(&pdev->dev);
423
424 return 0;
425}
426
427#ifdef CONFIG_PM_RUNTIME
428
429static int ti_pipe3_runtime_suspend(struct device *dev)
430{
431 struct ti_pipe3 *phy = dev_get_drvdata(dev);
432
433 if (!IS_ERR(phy->wkupclk))
434 clk_disable_unprepare(phy->wkupclk);
435 if (!IS_ERR(phy->refclk))
436 clk_disable_unprepare(phy->refclk);
437 if (!IS_ERR(phy->div_clk))
438 clk_disable_unprepare(phy->div_clk);
439
440 return 0;
441}
442
443static int ti_pipe3_runtime_resume(struct device *dev)
444{
445 u32 ret = 0;
446 struct ti_pipe3 *phy = dev_get_drvdata(dev);
447
448 if (!IS_ERR(phy->refclk)) {
449 ret = clk_prepare_enable(phy->refclk);
450 if (ret) {
451 dev_err(phy->dev, "Failed to enable refclk %d\n", ret);
452 goto err1;
453 }
454 }
455
456 if (!IS_ERR(phy->wkupclk)) {
457 ret = clk_prepare_enable(phy->wkupclk);
458 if (ret) {
459 dev_err(phy->dev, "Failed to enable wkupclk %d\n", ret);
460 goto err2;
461 }
462 }
463
464 if (!IS_ERR(phy->div_clk)) {
465 ret = clk_prepare_enable(phy->div_clk);
466 if (ret) {
467 dev_err(phy->dev, "Failed to enable div_clk %d\n", ret);
468 goto err3;
469 }
470 }
471 return 0;
472
473err3:
474 if (!IS_ERR(phy->wkupclk))
475 clk_disable_unprepare(phy->wkupclk);
476
477err2:
478 if (!IS_ERR(phy->refclk))
479 clk_disable_unprepare(phy->refclk);
480
481err1:
482 return ret;
483}
484
485static const struct dev_pm_ops ti_pipe3_pm_ops = {
486 SET_RUNTIME_PM_OPS(ti_pipe3_runtime_suspend,
487 ti_pipe3_runtime_resume, NULL)
488};
489
490#define DEV_PM_OPS (&ti_pipe3_pm_ops)
491#else
492#define DEV_PM_OPS NULL
493#endif
494
495#ifdef CONFIG_OF
496static const struct of_device_id ti_pipe3_id_table[] = {
497 {
498 .compatible = "ti,phy-usb3",
499 .data = dpll_map_usb,
500 },
501 {
502 .compatible = "ti,omap-usb3",
503 .data = dpll_map_usb,
504 },
505 {
506 .compatible = "ti,phy-pipe3-sata",
507 .data = dpll_map_sata,
508 },
509 {
510 .compatible = "ti,phy-pipe3-pcie",
511 },
512 {}
513};
514MODULE_DEVICE_TABLE(of, ti_pipe3_id_table);
515#endif
516
517static struct platform_driver ti_pipe3_driver = {
518 .probe = ti_pipe3_probe,
519 .remove = ti_pipe3_remove,
520 .driver = {
521 .name = "ti-pipe3",
522 .owner = THIS_MODULE,
523 .pm = DEV_PM_OPS,
524 .of_match_table = of_match_ptr(ti_pipe3_id_table),
525 },
526};
527
528module_platform_driver(ti_pipe3_driver);
529
530MODULE_ALIAS("platform: ti_pipe3");
531MODULE_AUTHOR("Texas Instruments Inc.");
532MODULE_DESCRIPTION("TI PIPE3 phy driver");
533MODULE_LICENSE("GPL v2");
534
