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11#ifndef __SH_PFC_H
12#define __SH_PFC_H
13
14#include <linux/bug.h>
15#include <linux/stringify.h>
16
17enum {
18 PINMUX_TYPE_NONE,
19 PINMUX_TYPE_FUNCTION,
20 PINMUX_TYPE_GPIO,
21 PINMUX_TYPE_OUTPUT,
22 PINMUX_TYPE_INPUT,
23};
24
25#define SH_PFC_PIN_CFG_INPUT (1 << 0)
26#define SH_PFC_PIN_CFG_OUTPUT (1 << 1)
27#define SH_PFC_PIN_CFG_PULL_UP (1 << 2)
28#define SH_PFC_PIN_CFG_PULL_DOWN (1 << 3)
29#define SH_PFC_PIN_CFG_NO_GPIO (1 << 31)
30
31struct sh_pfc_pin {
32 u16 pin;
33 u16 enum_id;
34 const char *name;
35 unsigned int configs;
36};
37
38#define SH_PFC_PIN_GROUP(n) \
39 { \
40 .name = #n, \
41 .pins = n##_pins, \
42 .mux = n##_mux, \
43 .nr_pins = ARRAY_SIZE(n##_pins), \
44 }
45
46struct sh_pfc_pin_group {
47 const char *name;
48 const unsigned int *pins;
49 const unsigned int *mux;
50 unsigned int nr_pins;
51};
52
53#define SH_PFC_FUNCTION(n) \
54 { \
55 .name = #n, \
56 .groups = n##_groups, \
57 .nr_groups = ARRAY_SIZE(n##_groups), \
58 }
59
60struct sh_pfc_function {
61 const char *name;
62 const char * const *groups;
63 unsigned int nr_groups;
64};
65
66struct pinmux_func {
67 u16 enum_id;
68 const char *name;
69};
70
71struct pinmux_cfg_reg {
72 unsigned long reg, reg_width, field_width;
73 const u16 *enum_ids;
74 const unsigned long *var_field_width;
75};
76
77#define PINMUX_CFG_REG(name, r, r_width, f_width) \
78 .reg = r, .reg_width = r_width, .field_width = f_width, \
79 .enum_ids = (const u16 [(r_width / f_width) * (1 << f_width)])
80
81#define PINMUX_CFG_REG_VAR(name, r, r_width, var_fw0, var_fwn...) \
82 .reg = r, .reg_width = r_width, \
83 .var_field_width = (const unsigned long [r_width]) \
84 { var_fw0, var_fwn, 0 }, \
85 .enum_ids = (const u16 [])
86
87struct pinmux_data_reg {
88 unsigned long reg, reg_width;
89 const u16 *enum_ids;
90};
91
92#define PINMUX_DATA_REG(name, r, r_width) \
93 .reg = r, .reg_width = r_width, \
94 .enum_ids = (const u16 [r_width]) \
95
96struct pinmux_irq {
97 int irq;
98 const short *gpios;
99};
100
101#ifdef CONFIG_ARCH_MULTIPLATFORM
102#define PINMUX_IRQ(irq_nr, ids...) \
103 { .gpios = (const short []) { ids, -1 } }
104#else
105#define PINMUX_IRQ(irq_nr, ids...) \
106 { .irq = irq_nr, .gpios = (const short []) { ids, -1 } }
107#endif
108
109struct pinmux_range {
110 u16 begin;
111 u16 end;
112 u16 force;
113};
114
115struct sh_pfc;
116
117struct sh_pfc_soc_operations {
118 int (*init)(struct sh_pfc *pfc);
119 void (*exit)(struct sh_pfc *pfc);
120 unsigned int (*get_bias)(struct sh_pfc *pfc, unsigned int pin);
121 void (*set_bias)(struct sh_pfc *pfc, unsigned int pin,
122 unsigned int bias);
123};
124
125struct sh_pfc_soc_info {
126 const char *name;
127 const struct sh_pfc_soc_operations *ops;
128
129 struct pinmux_range input;
130 struct pinmux_range output;
131 struct pinmux_range function;
132
133 const struct sh_pfc_pin *pins;
134 unsigned int nr_pins;
135 const struct sh_pfc_pin_group *groups;
136 unsigned int nr_groups;
137 const struct sh_pfc_function *functions;
138 unsigned int nr_functions;
139
140 const struct pinmux_func *func_gpios;
141 unsigned int nr_func_gpios;
142
143 const struct pinmux_cfg_reg *cfg_regs;
144 const struct pinmux_data_reg *data_regs;
145
146 const u16 *gpio_data;
147 unsigned int gpio_data_size;
148
149 const struct pinmux_irq *gpio_irq;
150 unsigned int gpio_irq_size;
151
152 unsigned long unlock_reg;
153};
154
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161
162
163#define PINMUX_DATA(data_or_mark, ids...) data_or_mark, ids, 0
164
165#define PINMUX_IPSR_NOGP(ispr, fn) \
166 PINMUX_DATA(fn##_MARK, FN_##fn)
167#define PINMUX_IPSR_DATA(ipsr, fn) \
168 PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ipsr)
169#define PINMUX_IPSR_NOGM(ispr, fn, ms) \
170 PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ms)
171#define PINMUX_IPSR_MSEL(ipsr, fn, ms) \
172 PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ipsr, FN_##ms)
173#define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) \
174 PINMUX_DATA(fn##_MARK, FN_##ms, FN_##ipsr, FN_##fn)
175
176
177
178
179
180#define PORT_GP_1(bank, pin, fn, sfx) fn(bank, pin, GP_##bank##_##pin, sfx)
181
182#define PORT_GP_32(bank, fn, sfx) \
183 PORT_GP_1(bank, 0, fn, sfx), PORT_GP_1(bank, 1, fn, sfx), \
184 PORT_GP_1(bank, 2, fn, sfx), PORT_GP_1(bank, 3, fn, sfx), \
185 PORT_GP_1(bank, 4, fn, sfx), PORT_GP_1(bank, 5, fn, sfx), \
186 PORT_GP_1(bank, 6, fn, sfx), PORT_GP_1(bank, 7, fn, sfx), \
187 PORT_GP_1(bank, 8, fn, sfx), PORT_GP_1(bank, 9, fn, sfx), \
188 PORT_GP_1(bank, 10, fn, sfx), PORT_GP_1(bank, 11, fn, sfx), \
189 PORT_GP_1(bank, 12, fn, sfx), PORT_GP_1(bank, 13, fn, sfx), \
190 PORT_GP_1(bank, 14, fn, sfx), PORT_GP_1(bank, 15, fn, sfx), \
191 PORT_GP_1(bank, 16, fn, sfx), PORT_GP_1(bank, 17, fn, sfx), \
192 PORT_GP_1(bank, 18, fn, sfx), PORT_GP_1(bank, 19, fn, sfx), \
193 PORT_GP_1(bank, 20, fn, sfx), PORT_GP_1(bank, 21, fn, sfx), \
194 PORT_GP_1(bank, 22, fn, sfx), PORT_GP_1(bank, 23, fn, sfx), \
195 PORT_GP_1(bank, 24, fn, sfx), PORT_GP_1(bank, 25, fn, sfx), \
196 PORT_GP_1(bank, 26, fn, sfx), PORT_GP_1(bank, 27, fn, sfx), \
197 PORT_GP_1(bank, 28, fn, sfx), PORT_GP_1(bank, 29, fn, sfx), \
198 PORT_GP_1(bank, 30, fn, sfx), PORT_GP_1(bank, 31, fn, sfx)
199
200#define PORT_GP_32_REV(bank, fn, sfx) \
201 PORT_GP_1(bank, 31, fn, sfx), PORT_GP_1(bank, 30, fn, sfx), \
202 PORT_GP_1(bank, 29, fn, sfx), PORT_GP_1(bank, 28, fn, sfx), \
203 PORT_GP_1(bank, 27, fn, sfx), PORT_GP_1(bank, 26, fn, sfx), \
204 PORT_GP_1(bank, 25, fn, sfx), PORT_GP_1(bank, 24, fn, sfx), \
205 PORT_GP_1(bank, 23, fn, sfx), PORT_GP_1(bank, 22, fn, sfx), \
206 PORT_GP_1(bank, 21, fn, sfx), PORT_GP_1(bank, 20, fn, sfx), \
207 PORT_GP_1(bank, 19, fn, sfx), PORT_GP_1(bank, 18, fn, sfx), \
208 PORT_GP_1(bank, 17, fn, sfx), PORT_GP_1(bank, 16, fn, sfx), \
209 PORT_GP_1(bank, 15, fn, sfx), PORT_GP_1(bank, 14, fn, sfx), \
210 PORT_GP_1(bank, 13, fn, sfx), PORT_GP_1(bank, 12, fn, sfx), \
211 PORT_GP_1(bank, 11, fn, sfx), PORT_GP_1(bank, 10, fn, sfx), \
212 PORT_GP_1(bank, 9, fn, sfx), PORT_GP_1(bank, 8, fn, sfx), \
213 PORT_GP_1(bank, 7, fn, sfx), PORT_GP_1(bank, 6, fn, sfx), \
214 PORT_GP_1(bank, 5, fn, sfx), PORT_GP_1(bank, 4, fn, sfx), \
215 PORT_GP_1(bank, 3, fn, sfx), PORT_GP_1(bank, 2, fn, sfx), \
216 PORT_GP_1(bank, 1, fn, sfx), PORT_GP_1(bank, 0, fn, sfx)
217
218
219#define _GP_ALL(bank, pin, name, sfx) name##_##sfx
220#define GP_ALL(str) CPU_ALL_PORT(_GP_ALL, str)
221
222
223#define _GP_GPIO(bank, _pin, _name, sfx) \
224 [(bank * 32) + _pin] = { \
225 .pin = (bank * 32) + _pin, \
226 .name = __stringify(_name), \
227 .enum_id = _name##_DATA, \
228 }
229#define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, unused)
230
231
232#define _GP_DATA(bank, pin, name, sfx) PINMUX_DATA(name##_DATA, name##_FN)
233#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, unused)
234
235
236
237
238
239#define PORT_1(pn, fn, pfx, sfx) fn(pn, pfx, sfx)
240
241#define PORT_10(pn, fn, pfx, sfx) \
242 PORT_1(pn, fn, pfx##0, sfx), PORT_1(pn+1, fn, pfx##1, sfx), \
243 PORT_1(pn+2, fn, pfx##2, sfx), PORT_1(pn+3, fn, pfx##3, sfx), \
244 PORT_1(pn+4, fn, pfx##4, sfx), PORT_1(pn+5, fn, pfx##5, sfx), \
245 PORT_1(pn+6, fn, pfx##6, sfx), PORT_1(pn+7, fn, pfx##7, sfx), \
246 PORT_1(pn+8, fn, pfx##8, sfx), PORT_1(pn+9, fn, pfx##9, sfx)
247
248#define PORT_90(pn, fn, pfx, sfx) \
249 PORT_10(pn+10, fn, pfx##1, sfx), PORT_10(pn+20, fn, pfx##2, sfx), \
250 PORT_10(pn+30, fn, pfx##3, sfx), PORT_10(pn+40, fn, pfx##4, sfx), \
251 PORT_10(pn+50, fn, pfx##5, sfx), PORT_10(pn+60, fn, pfx##6, sfx), \
252 PORT_10(pn+70, fn, pfx##7, sfx), PORT_10(pn+80, fn, pfx##8, sfx), \
253 PORT_10(pn+90, fn, pfx##9, sfx)
254
255
256#define _PORT_ALL(pn, pfx, sfx) pfx##_##sfx
257#define PORT_ALL(str) CPU_ALL_PORT(_PORT_ALL, PORT, str)
258
259
260#define PINMUX_GPIO(_pin) \
261 [GPIO_##_pin] = { \
262 .pin = (u16)-1, \
263 .name = __stringify(GPIO_##_pin), \
264 .enum_id = _pin##_DATA, \
265 }
266
267
268#define SH_PFC_PIN_CFG(_pin, cfgs) \
269 { \
270 .pin = _pin, \
271 .name = __stringify(PORT##_pin), \
272 .enum_id = PORT##_pin##_DATA, \
273 .configs = cfgs, \
274 }
275
276
277#define SH_PFC_PIN_NAMED(row, col, _name) \
278 { \
279 .pin = PIN_NUMBER(row, col), \
280 .name = __stringify(PIN_##_name), \
281 .configs = SH_PFC_PIN_CFG_NO_GPIO, \
282 }
283
284
285
286
287#define _PORT_DATA(pn, pfx, sfx) \
288 PINMUX_DATA(PORT##pfx##_DATA, PORT##pfx##_FN0, \
289 PORT##pfx##_OUT, PORT##pfx##_IN)
290#define PINMUX_DATA_ALL() CPU_ALL_PORT(_PORT_DATA, , unused)
291
292
293#define PINMUX_GPIO_FN(gpio, base, data_or_mark) \
294 [gpio - (base)] = { \
295 .name = __stringify(gpio), \
296 .enum_id = data_or_mark, \
297 }
298#define GPIO_FN(str) \
299 PINMUX_GPIO_FN(GPIO_FN_##str, PINMUX_FN_BASE, str##_MARK)
300
301
302
303
304#define _PCRH(in, in_pd, in_pu, out) \
305 0, (out), (in), 0, \
306 0, 0, 0, 0, \
307 0, 0, (in_pd), 0, \
308 0, 0, (in_pu), 0
309
310#define PORTCR(nr, reg) \
311 { \
312 PINMUX_CFG_REG("PORT" nr "CR", reg, 8, 4) { \
313 _PCRH(PORT##nr##_IN, 0, 0, PORT##nr##_OUT), \
314 PORT##nr##_FN0, PORT##nr##_FN1, \
315 PORT##nr##_FN2, PORT##nr##_FN3, \
316 PORT##nr##_FN4, PORT##nr##_FN5, \
317 PORT##nr##_FN6, PORT##nr##_FN7 } \
318 }
319
320#endif
321
