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10#include <linux/init.h>
11#include <linux/module.h>
12#include <linux/irq.h>
13#include <linux/platform_device.h>
14#include <linux/io.h>
15#include <linux/slab.h>
16#include <linux/err.h>
17#include <linux/pinctrl/pinctrl.h>
18#include <linux/pinctrl/pinmux.h>
19#include <linux/pinctrl/consumer.h>
20#include <linux/pinctrl/machine.h>
21#include <linux/of.h>
22#include <linux/of_address.h>
23#include <linux/of_device.h>
24#include <linux/of_platform.h>
25#include <linux/bitops.h>
26#include <linux/gpio.h>
27#include <linux/of_gpio.h>
28
29#include "pinctrl-sirf.h"
30
31#define DRIVER_NAME "pinmux-sirf"
32
33struct sirfsoc_gpio_bank {
34 int id;
35 int parent_irq;
36 spinlock_t lock;
37};
38
39struct sirfsoc_gpio_chip {
40 struct of_mm_gpio_chip chip;
41 bool is_marco;
42 struct sirfsoc_gpio_bank sgpio_bank[SIRFSOC_GPIO_NO_OF_BANKS];
43};
44
45static DEFINE_SPINLOCK(sgpio_lock);
46
47static struct sirfsoc_pin_group *sirfsoc_pin_groups;
48static int sirfsoc_pingrp_cnt;
49
50static int sirfsoc_get_groups_count(struct pinctrl_dev *pctldev)
51{
52 return sirfsoc_pingrp_cnt;
53}
54
55static const char *sirfsoc_get_group_name(struct pinctrl_dev *pctldev,
56 unsigned selector)
57{
58 return sirfsoc_pin_groups[selector].name;
59}
60
61static int sirfsoc_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
62 const unsigned **pins,
63 unsigned *num_pins)
64{
65 *pins = sirfsoc_pin_groups[selector].pins;
66 *num_pins = sirfsoc_pin_groups[selector].num_pins;
67 return 0;
68}
69
70static void sirfsoc_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
71 unsigned offset)
72{
73 seq_printf(s, " " DRIVER_NAME);
74}
75
76static int sirfsoc_dt_node_to_map(struct pinctrl_dev *pctldev,
77 struct device_node *np_config,
78 struct pinctrl_map **map, unsigned *num_maps)
79{
80 struct sirfsoc_pmx *spmx = pinctrl_dev_get_drvdata(pctldev);
81 struct device_node *np;
82 struct property *prop;
83 const char *function, *group;
84 int ret, index = 0, count = 0;
85
86
87 for_each_child_of_node(np_config, np) {
88 ret = of_property_read_string(np, "sirf,function", &function);
89 if (ret < 0)
90 return ret;
91
92 ret = of_property_count_strings(np, "sirf,pins");
93 if (ret < 0)
94 return ret;
95
96 count += ret;
97 }
98
99 if (!count) {
100 dev_err(spmx->dev, "No child nodes passed via DT\n");
101 return -ENODEV;
102 }
103
104 *map = kzalloc(sizeof(**map) * count, GFP_KERNEL);
105 if (!*map)
106 return -ENOMEM;
107
108 for_each_child_of_node(np_config, np) {
109 of_property_read_string(np, "sirf,function", &function);
110 of_property_for_each_string(np, "sirf,pins", prop, group) {
111 (*map)[index].type = PIN_MAP_TYPE_MUX_GROUP;
112 (*map)[index].data.mux.group = group;
113 (*map)[index].data.mux.function = function;
114 index++;
115 }
116 }
117
118 *num_maps = count;
119
120 return 0;
121}
122
123static void sirfsoc_dt_free_map(struct pinctrl_dev *pctldev,
124 struct pinctrl_map *map, unsigned num_maps)
125{
126 kfree(map);
127}
128
129static struct pinctrl_ops sirfsoc_pctrl_ops = {
130 .get_groups_count = sirfsoc_get_groups_count,
131 .get_group_name = sirfsoc_get_group_name,
132 .get_group_pins = sirfsoc_get_group_pins,
133 .pin_dbg_show = sirfsoc_pin_dbg_show,
134 .dt_node_to_map = sirfsoc_dt_node_to_map,
135 .dt_free_map = sirfsoc_dt_free_map,
136};
137
138static struct sirfsoc_pmx_func *sirfsoc_pmx_functions;
139static int sirfsoc_pmxfunc_cnt;
140
141static void sirfsoc_pinmux_endisable(struct sirfsoc_pmx *spmx, unsigned selector,
142 bool enable)
143{
144 int i;
145 const struct sirfsoc_padmux *mux = sirfsoc_pmx_functions[selector].padmux;
146 const struct sirfsoc_muxmask *mask = mux->muxmask;
147
148 for (i = 0; i < mux->muxmask_counts; i++) {
149 u32 muxval;
150 if (!spmx->is_marco) {
151 muxval = readl(spmx->gpio_virtbase + SIRFSOC_GPIO_PAD_EN(mask[i].group));
152 if (enable)
153 muxval = muxval & ~mask[i].mask;
154 else
155 muxval = muxval | mask[i].mask;
156 writel(muxval, spmx->gpio_virtbase + SIRFSOC_GPIO_PAD_EN(mask[i].group));
157 } else {
158 if (enable)
159 writel(mask[i].mask, spmx->gpio_virtbase +
160 SIRFSOC_GPIO_PAD_EN_CLR(mask[i].group));
161 else
162 writel(mask[i].mask, spmx->gpio_virtbase +
163 SIRFSOC_GPIO_PAD_EN(mask[i].group));
164 }
165 }
166
167 if (mux->funcmask && enable) {
168 u32 func_en_val;
169
170 func_en_val =
171 readl(spmx->rsc_virtbase + mux->ctrlreg);
172 func_en_val =
173 (func_en_val & ~mux->funcmask) | (mux->funcval);
174 writel(func_en_val, spmx->rsc_virtbase + mux->ctrlreg);
175 }
176}
177
178static int sirfsoc_pinmux_enable(struct pinctrl_dev *pmxdev, unsigned selector,
179 unsigned group)
180{
181 struct sirfsoc_pmx *spmx;
182
183 spmx = pinctrl_dev_get_drvdata(pmxdev);
184 sirfsoc_pinmux_endisable(spmx, selector, true);
185
186 return 0;
187}
188
189static int sirfsoc_pinmux_get_funcs_count(struct pinctrl_dev *pmxdev)
190{
191 return sirfsoc_pmxfunc_cnt;
192}
193
194static const char *sirfsoc_pinmux_get_func_name(struct pinctrl_dev *pctldev,
195 unsigned selector)
196{
197 return sirfsoc_pmx_functions[selector].name;
198}
199
200static int sirfsoc_pinmux_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
201 const char * const **groups,
202 unsigned * const num_groups)
203{
204 *groups = sirfsoc_pmx_functions[selector].groups;
205 *num_groups = sirfsoc_pmx_functions[selector].num_groups;
206 return 0;
207}
208
209static int sirfsoc_pinmux_request_gpio(struct pinctrl_dev *pmxdev,
210 struct pinctrl_gpio_range *range, unsigned offset)
211{
212 struct sirfsoc_pmx *spmx;
213
214 int group = range->id;
215
216 u32 muxval;
217
218 spmx = pinctrl_dev_get_drvdata(pmxdev);
219
220 if (!spmx->is_marco) {
221 muxval = readl(spmx->gpio_virtbase + SIRFSOC_GPIO_PAD_EN(group));
222 muxval = muxval | (1 << (offset - range->pin_base));
223 writel(muxval, spmx->gpio_virtbase + SIRFSOC_GPIO_PAD_EN(group));
224 } else {
225 writel(1 << (offset - range->pin_base), spmx->gpio_virtbase +
226 SIRFSOC_GPIO_PAD_EN(group));
227 }
228
229 return 0;
230}
231
232static struct pinmux_ops sirfsoc_pinmux_ops = {
233 .enable = sirfsoc_pinmux_enable,
234 .get_functions_count = sirfsoc_pinmux_get_funcs_count,
235 .get_function_name = sirfsoc_pinmux_get_func_name,
236 .get_function_groups = sirfsoc_pinmux_get_groups,
237 .gpio_request_enable = sirfsoc_pinmux_request_gpio,
238};
239
240static struct pinctrl_desc sirfsoc_pinmux_desc = {
241 .name = DRIVER_NAME,
242 .pctlops = &sirfsoc_pctrl_ops,
243 .pmxops = &sirfsoc_pinmux_ops,
244 .owner = THIS_MODULE,
245};
246
247static void __iomem *sirfsoc_rsc_of_iomap(void)
248{
249 const struct of_device_id rsc_ids[] = {
250 { .compatible = "sirf,prima2-rsc" },
251 { .compatible = "sirf,marco-rsc" },
252 {}
253 };
254 struct device_node *np;
255
256 np = of_find_matching_node(NULL, rsc_ids);
257 if (!np)
258 panic("unable to find compatible rsc node in dtb\n");
259
260 return of_iomap(np, 0);
261}
262
263static int sirfsoc_gpio_of_xlate(struct gpio_chip *gc,
264 const struct of_phandle_args *gpiospec,
265 u32 *flags)
266{
267 if (gpiospec->args[0] > SIRFSOC_GPIO_NO_OF_BANKS * SIRFSOC_GPIO_BANK_SIZE)
268 return -EINVAL;
269
270 if (flags)
271 *flags = gpiospec->args[1];
272
273 return gpiospec->args[0];
274}
275
276static const struct of_device_id pinmux_ids[] = {
277 { .compatible = "sirf,prima2-pinctrl", .data = &prima2_pinctrl_data, },
278 { .compatible = "sirf,atlas6-pinctrl", .data = &atlas6_pinctrl_data, },
279 { .compatible = "sirf,marco-pinctrl", .data = &prima2_pinctrl_data, },
280 {}
281};
282
283static int sirfsoc_pinmux_probe(struct platform_device *pdev)
284{
285 int ret;
286 struct sirfsoc_pmx *spmx;
287 struct device_node *np = pdev->dev.of_node;
288 const struct sirfsoc_pinctrl_data *pdata;
289
290
291 spmx = devm_kzalloc(&pdev->dev, sizeof(*spmx), GFP_KERNEL);
292 if (!spmx)
293 return -ENOMEM;
294
295 spmx->dev = &pdev->dev;
296
297 platform_set_drvdata(pdev, spmx);
298
299 spmx->gpio_virtbase = of_iomap(np, 0);
300 if (!spmx->gpio_virtbase) {
301 dev_err(&pdev->dev, "can't map gpio registers\n");
302 return -ENOMEM;
303 }
304
305 spmx->rsc_virtbase = sirfsoc_rsc_of_iomap();
306 if (!spmx->rsc_virtbase) {
307 ret = -ENOMEM;
308 dev_err(&pdev->dev, "can't map rsc registers\n");
309 goto out_no_rsc_remap;
310 }
311
312 if (of_device_is_compatible(np, "sirf,marco-pinctrl"))
313 spmx->is_marco = 1;
314
315 pdata = of_match_node(pinmux_ids, np)->data;
316 sirfsoc_pin_groups = pdata->grps;
317 sirfsoc_pingrp_cnt = pdata->grps_cnt;
318 sirfsoc_pmx_functions = pdata->funcs;
319 sirfsoc_pmxfunc_cnt = pdata->funcs_cnt;
320 sirfsoc_pinmux_desc.pins = pdata->pads;
321 sirfsoc_pinmux_desc.npins = pdata->pads_cnt;
322
323
324
325 spmx->pmx = pinctrl_register(&sirfsoc_pinmux_desc, &pdev->dev, spmx);
326 if (!spmx->pmx) {
327 dev_err(&pdev->dev, "could not register SIRFSOC pinmux driver\n");
328 ret = -EINVAL;
329 goto out_no_pmx;
330 }
331
332 dev_info(&pdev->dev, "initialized SIRFSOC pinmux driver\n");
333
334 return 0;
335
336out_no_pmx:
337 iounmap(spmx->rsc_virtbase);
338out_no_rsc_remap:
339 iounmap(spmx->gpio_virtbase);
340 return ret;
341}
342
343#ifdef CONFIG_PM_SLEEP
344static int sirfsoc_pinmux_suspend_noirq(struct device *dev)
345{
346 int i, j;
347 struct sirfsoc_pmx *spmx = dev_get_drvdata(dev);
348
349 for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
350 for (j = 0; j < SIRFSOC_GPIO_BANK_SIZE; j++) {
351 spmx->gpio_regs[i][j] = readl(spmx->gpio_virtbase +
352 SIRFSOC_GPIO_CTRL(i, j));
353 }
354 spmx->ints_regs[i] = readl(spmx->gpio_virtbase +
355 SIRFSOC_GPIO_INT_STATUS(i));
356 spmx->paden_regs[i] = readl(spmx->gpio_virtbase +
357 SIRFSOC_GPIO_PAD_EN(i));
358 }
359 spmx->dspen_regs = readl(spmx->gpio_virtbase + SIRFSOC_GPIO_DSP_EN0);
360
361 for (i = 0; i < 3; i++)
362 spmx->rsc_regs[i] = readl(spmx->rsc_virtbase + 4 * i);
363
364 return 0;
365}
366
367static int sirfsoc_pinmux_resume_noirq(struct device *dev)
368{
369 int i, j;
370 struct sirfsoc_pmx *spmx = dev_get_drvdata(dev);
371
372 for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
373 for (j = 0; j < SIRFSOC_GPIO_BANK_SIZE; j++) {
374 writel(spmx->gpio_regs[i][j], spmx->gpio_virtbase +
375 SIRFSOC_GPIO_CTRL(i, j));
376 }
377 writel(spmx->ints_regs[i], spmx->gpio_virtbase +
378 SIRFSOC_GPIO_INT_STATUS(i));
379 writel(spmx->paden_regs[i], spmx->gpio_virtbase +
380 SIRFSOC_GPIO_PAD_EN(i));
381 }
382 writel(spmx->dspen_regs, spmx->gpio_virtbase + SIRFSOC_GPIO_DSP_EN0);
383
384 for (i = 0; i < 3; i++)
385 writel(spmx->rsc_regs[i], spmx->rsc_virtbase + 4 * i);
386
387 return 0;
388}
389
390static const struct dev_pm_ops sirfsoc_pinmux_pm_ops = {
391 .suspend_noirq = sirfsoc_pinmux_suspend_noirq,
392 .resume_noirq = sirfsoc_pinmux_resume_noirq,
393 .freeze_noirq = sirfsoc_pinmux_suspend_noirq,
394 .restore_noirq = sirfsoc_pinmux_resume_noirq,
395};
396#endif
397
398static struct platform_driver sirfsoc_pinmux_driver = {
399 .driver = {
400 .name = DRIVER_NAME,
401 .owner = THIS_MODULE,
402 .of_match_table = pinmux_ids,
403#ifdef CONFIG_PM_SLEEP
404 .pm = &sirfsoc_pinmux_pm_ops,
405#endif
406 },
407 .probe = sirfsoc_pinmux_probe,
408};
409
410static int __init sirfsoc_pinmux_init(void)
411{
412 return platform_driver_register(&sirfsoc_pinmux_driver);
413}
414arch_initcall(sirfsoc_pinmux_init);
415
416static inline struct sirfsoc_gpio_chip *to_sirfsoc_gpio(struct gpio_chip *gc)
417{
418 return container_of(gc, struct sirfsoc_gpio_chip, chip.gc);
419}
420
421static inline struct sirfsoc_gpio_bank *
422sirfsoc_gpio_to_bank(struct sirfsoc_gpio_chip *sgpio, unsigned int offset)
423{
424 return &sgpio->sgpio_bank[offset / SIRFSOC_GPIO_BANK_SIZE];
425}
426
427static inline int sirfsoc_gpio_to_bankoff(unsigned int offset)
428{
429 return offset % SIRFSOC_GPIO_BANK_SIZE;
430}
431
432static void sirfsoc_gpio_irq_ack(struct irq_data *d)
433{
434 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
435 struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(gc);
436 struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, d->hwirq);
437 int idx = sirfsoc_gpio_to_bankoff(d->hwirq);
438 u32 val, offset;
439 unsigned long flags;
440
441 offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
442
443 spin_lock_irqsave(&sgpio_lock, flags);
444
445 val = readl(sgpio->chip.regs + offset);
446
447 writel(val, sgpio->chip.regs + offset);
448
449 spin_unlock_irqrestore(&sgpio_lock, flags);
450}
451
452static void __sirfsoc_gpio_irq_mask(struct sirfsoc_gpio_chip *sgpio,
453 struct sirfsoc_gpio_bank *bank,
454 int idx)
455{
456 u32 val, offset;
457 unsigned long flags;
458
459 offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
460
461 spin_lock_irqsave(&sgpio_lock, flags);
462
463 val = readl(sgpio->chip.regs + offset);
464 val &= ~SIRFSOC_GPIO_CTL_INTR_EN_MASK;
465 val &= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK;
466 writel(val, sgpio->chip.regs + offset);
467
468 spin_unlock_irqrestore(&sgpio_lock, flags);
469}
470
471static void sirfsoc_gpio_irq_mask(struct irq_data *d)
472{
473 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
474 struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(gc);
475 struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, d->hwirq);
476
477 __sirfsoc_gpio_irq_mask(sgpio, bank, d->hwirq % SIRFSOC_GPIO_BANK_SIZE);
478}
479
480static void sirfsoc_gpio_irq_unmask(struct irq_data *d)
481{
482 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
483 struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(gc);
484 struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, d->hwirq);
485 int idx = sirfsoc_gpio_to_bankoff(d->hwirq);
486 u32 val, offset;
487 unsigned long flags;
488
489 offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
490
491 spin_lock_irqsave(&sgpio_lock, flags);
492
493 val = readl(sgpio->chip.regs + offset);
494 val &= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK;
495 val |= SIRFSOC_GPIO_CTL_INTR_EN_MASK;
496 writel(val, sgpio->chip.regs + offset);
497
498 spin_unlock_irqrestore(&sgpio_lock, flags);
499}
500
501static int sirfsoc_gpio_irq_type(struct irq_data *d, unsigned type)
502{
503 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
504 struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(gc);
505 struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, d->hwirq);
506 int idx = sirfsoc_gpio_to_bankoff(d->hwirq);
507 u32 val, offset;
508 unsigned long flags;
509
510 offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
511
512 spin_lock_irqsave(&sgpio_lock, flags);
513
514 val = readl(sgpio->chip.regs + offset);
515 val &= ~(SIRFSOC_GPIO_CTL_INTR_STS_MASK | SIRFSOC_GPIO_CTL_OUT_EN_MASK);
516
517 switch (type) {
518 case IRQ_TYPE_NONE:
519 break;
520 case IRQ_TYPE_EDGE_RISING:
521 val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK;
522 val &= ~SIRFSOC_GPIO_CTL_INTR_LOW_MASK;
523 break;
524 case IRQ_TYPE_EDGE_FALLING:
525 val &= ~SIRFSOC_GPIO_CTL_INTR_HIGH_MASK;
526 val |= SIRFSOC_GPIO_CTL_INTR_LOW_MASK | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK;
527 break;
528 case IRQ_TYPE_EDGE_BOTH:
529 val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK | SIRFSOC_GPIO_CTL_INTR_LOW_MASK |
530 SIRFSOC_GPIO_CTL_INTR_TYPE_MASK;
531 break;
532 case IRQ_TYPE_LEVEL_LOW:
533 val &= ~(SIRFSOC_GPIO_CTL_INTR_HIGH_MASK | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK);
534 val |= SIRFSOC_GPIO_CTL_INTR_LOW_MASK;
535 break;
536 case IRQ_TYPE_LEVEL_HIGH:
537 val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK;
538 val &= ~(SIRFSOC_GPIO_CTL_INTR_LOW_MASK | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK);
539 break;
540 }
541
542 writel(val, sgpio->chip.regs + offset);
543
544 spin_unlock_irqrestore(&sgpio_lock, flags);
545
546 return 0;
547}
548
549static struct irq_chip sirfsoc_irq_chip = {
550 .name = "sirf-gpio-irq",
551 .irq_ack = sirfsoc_gpio_irq_ack,
552 .irq_mask = sirfsoc_gpio_irq_mask,
553 .irq_unmask = sirfsoc_gpio_irq_unmask,
554 .irq_set_type = sirfsoc_gpio_irq_type,
555};
556
557static void sirfsoc_gpio_handle_irq(unsigned int irq, struct irq_desc *desc)
558{
559 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
560 struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(gc);
561 struct sirfsoc_gpio_bank *bank;
562 u32 status, ctrl;
563 int idx = 0;
564 struct irq_chip *chip = irq_get_chip(irq);
565 int i;
566
567 for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
568 bank = &sgpio->sgpio_bank[i];
569 if (bank->parent_irq == irq)
570 break;
571 }
572 BUG_ON(i == SIRFSOC_GPIO_NO_OF_BANKS);
573
574 chained_irq_enter(chip, desc);
575
576 status = readl(sgpio->chip.regs + SIRFSOC_GPIO_INT_STATUS(bank->id));
577 if (!status) {
578 printk(KERN_WARNING
579 "%s: gpio id %d status %#x no interrupt is flaged\n",
580 __func__, bank->id, status);
581 handle_bad_irq(irq, desc);
582 return;
583 }
584
585 while (status) {
586 ctrl = readl(sgpio->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, idx));
587
588
589
590
591
592 if ((status & 0x1) && (ctrl & SIRFSOC_GPIO_CTL_INTR_EN_MASK)) {
593 pr_debug("%s: gpio id %d idx %d happens\n",
594 __func__, bank->id, idx);
595 generic_handle_irq(irq_find_mapping(gc->irqdomain, idx +
596 bank->id * SIRFSOC_GPIO_BANK_SIZE));
597 }
598
599 idx++;
600 status = status >> 1;
601 }
602
603 chained_irq_exit(chip, desc);
604}
605
606static inline void sirfsoc_gpio_set_input(struct sirfsoc_gpio_chip *sgpio,
607 unsigned ctrl_offset)
608{
609 u32 val;
610
611 val = readl(sgpio->chip.regs + ctrl_offset);
612 val &= ~SIRFSOC_GPIO_CTL_OUT_EN_MASK;
613 writel(val, sgpio->chip.regs + ctrl_offset);
614}
615
616static int sirfsoc_gpio_request(struct gpio_chip *chip, unsigned offset)
617{
618 struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(chip);
619 struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, offset);
620 unsigned long flags;
621
622 if (pinctrl_request_gpio(chip->base + offset))
623 return -ENODEV;
624
625 spin_lock_irqsave(&bank->lock, flags);
626
627
628
629
630
631 sirfsoc_gpio_set_input(sgpio, SIRFSOC_GPIO_CTRL(bank->id, offset));
632 __sirfsoc_gpio_irq_mask(sgpio, bank, offset);
633
634 spin_unlock_irqrestore(&bank->lock, flags);
635
636 return 0;
637}
638
639static void sirfsoc_gpio_free(struct gpio_chip *chip, unsigned offset)
640{
641 struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(chip);
642 struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, offset);
643 unsigned long flags;
644
645 spin_lock_irqsave(&bank->lock, flags);
646
647 __sirfsoc_gpio_irq_mask(sgpio, bank, offset);
648 sirfsoc_gpio_set_input(sgpio, SIRFSOC_GPIO_CTRL(bank->id, offset));
649
650 spin_unlock_irqrestore(&bank->lock, flags);
651
652 pinctrl_free_gpio(chip->base + offset);
653}
654
655static int sirfsoc_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
656{
657 struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(chip);
658 struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, gpio);
659 int idx = sirfsoc_gpio_to_bankoff(gpio);
660 unsigned long flags;
661 unsigned offset;
662
663 offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
664
665 spin_lock_irqsave(&bank->lock, flags);
666
667 sirfsoc_gpio_set_input(sgpio, offset);
668
669 spin_unlock_irqrestore(&bank->lock, flags);
670
671 return 0;
672}
673
674static inline void sirfsoc_gpio_set_output(struct sirfsoc_gpio_chip *sgpio,
675 struct sirfsoc_gpio_bank *bank,
676 unsigned offset,
677 int value)
678{
679 u32 out_ctrl;
680 unsigned long flags;
681
682 spin_lock_irqsave(&bank->lock, flags);
683
684 out_ctrl = readl(sgpio->chip.regs + offset);
685 if (value)
686 out_ctrl |= SIRFSOC_GPIO_CTL_DATAOUT_MASK;
687 else
688 out_ctrl &= ~SIRFSOC_GPIO_CTL_DATAOUT_MASK;
689
690 out_ctrl &= ~SIRFSOC_GPIO_CTL_INTR_EN_MASK;
691 out_ctrl |= SIRFSOC_GPIO_CTL_OUT_EN_MASK;
692 writel(out_ctrl, sgpio->chip.regs + offset);
693
694 spin_unlock_irqrestore(&bank->lock, flags);
695}
696
697static int sirfsoc_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, int value)
698{
699 struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(chip);
700 struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, gpio);
701 int idx = sirfsoc_gpio_to_bankoff(gpio);
702 u32 offset;
703 unsigned long flags;
704
705 offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
706
707 spin_lock_irqsave(&sgpio_lock, flags);
708
709 sirfsoc_gpio_set_output(sgpio, bank, offset, value);
710
711 spin_unlock_irqrestore(&sgpio_lock, flags);
712
713 return 0;
714}
715
716static int sirfsoc_gpio_get_value(struct gpio_chip *chip, unsigned offset)
717{
718 struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(chip);
719 struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, offset);
720 u32 val;
721 unsigned long flags;
722
723 spin_lock_irqsave(&bank->lock, flags);
724
725 val = readl(sgpio->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset));
726
727 spin_unlock_irqrestore(&bank->lock, flags);
728
729 return !!(val & SIRFSOC_GPIO_CTL_DATAIN_MASK);
730}
731
732static void sirfsoc_gpio_set_value(struct gpio_chip *chip, unsigned offset,
733 int value)
734{
735 struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(chip);
736 struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, offset);
737 u32 ctrl;
738 unsigned long flags;
739
740 spin_lock_irqsave(&bank->lock, flags);
741
742 ctrl = readl(sgpio->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset));
743 if (value)
744 ctrl |= SIRFSOC_GPIO_CTL_DATAOUT_MASK;
745 else
746 ctrl &= ~SIRFSOC_GPIO_CTL_DATAOUT_MASK;
747 writel(ctrl, sgpio->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset));
748
749 spin_unlock_irqrestore(&bank->lock, flags);
750}
751
752static void sirfsoc_gpio_set_pullup(struct sirfsoc_gpio_chip *sgpio,
753 const u32 *pullups)
754{
755 int i, n;
756 const unsigned long *p = (const unsigned long *)pullups;
757
758 for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
759 for_each_set_bit(n, p + i, BITS_PER_LONG) {
760 u32 offset = SIRFSOC_GPIO_CTRL(i, n);
761 u32 val = readl(sgpio->chip.regs + offset);
762 val |= SIRFSOC_GPIO_CTL_PULL_MASK;
763 val |= SIRFSOC_GPIO_CTL_PULL_HIGH;
764 writel(val, sgpio->chip.regs + offset);
765 }
766 }
767}
768
769static void sirfsoc_gpio_set_pulldown(struct sirfsoc_gpio_chip *sgpio,
770 const u32 *pulldowns)
771{
772 int i, n;
773 const unsigned long *p = (const unsigned long *)pulldowns;
774
775 for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
776 for_each_set_bit(n, p + i, BITS_PER_LONG) {
777 u32 offset = SIRFSOC_GPIO_CTRL(i, n);
778 u32 val = readl(sgpio->chip.regs + offset);
779 val |= SIRFSOC_GPIO_CTL_PULL_MASK;
780 val &= ~SIRFSOC_GPIO_CTL_PULL_HIGH;
781 writel(val, sgpio->chip.regs + offset);
782 }
783 }
784}
785
786static int sirfsoc_gpio_probe(struct device_node *np)
787{
788 int i, err = 0;
789 static struct sirfsoc_gpio_chip *sgpio;
790 struct sirfsoc_gpio_bank *bank;
791 void __iomem *regs;
792 struct platform_device *pdev;
793 bool is_marco = false;
794
795 u32 pullups[SIRFSOC_GPIO_NO_OF_BANKS], pulldowns[SIRFSOC_GPIO_NO_OF_BANKS];
796
797 pdev = of_find_device_by_node(np);
798 if (!pdev)
799 return -ENODEV;
800
801 sgpio = devm_kzalloc(&pdev->dev, sizeof(*sgpio), GFP_KERNEL);
802 if (!sgpio)
803 return -ENOMEM;
804
805 regs = of_iomap(np, 0);
806 if (!regs)
807 return -ENOMEM;
808
809 if (of_device_is_compatible(np, "sirf,marco-pinctrl"))
810 is_marco = 1;
811
812 sgpio->chip.gc.request = sirfsoc_gpio_request;
813 sgpio->chip.gc.free = sirfsoc_gpio_free;
814 sgpio->chip.gc.direction_input = sirfsoc_gpio_direction_input;
815 sgpio->chip.gc.get = sirfsoc_gpio_get_value;
816 sgpio->chip.gc.direction_output = sirfsoc_gpio_direction_output;
817 sgpio->chip.gc.set = sirfsoc_gpio_set_value;
818 sgpio->chip.gc.base = 0;
819 sgpio->chip.gc.ngpio = SIRFSOC_GPIO_BANK_SIZE * SIRFSOC_GPIO_NO_OF_BANKS;
820 sgpio->chip.gc.label = kstrdup(np->full_name, GFP_KERNEL);
821 sgpio->chip.gc.of_node = np;
822 sgpio->chip.gc.of_xlate = sirfsoc_gpio_of_xlate;
823 sgpio->chip.gc.of_gpio_n_cells = 2;
824 sgpio->chip.gc.dev = &pdev->dev;
825 sgpio->chip.regs = regs;
826 sgpio->is_marco = is_marco;
827
828 err = gpiochip_add(&sgpio->chip.gc);
829 if (err) {
830 dev_err(&pdev->dev, "%s: error in probe function with status %d\n",
831 np->full_name, err);
832 goto out;
833 }
834
835 err = gpiochip_irqchip_add(&sgpio->chip.gc,
836 &sirfsoc_irq_chip,
837 0, handle_level_irq,
838 IRQ_TYPE_NONE);
839 if (err) {
840 dev_err(&pdev->dev,
841 "could not connect irqchip to gpiochip\n");
842 goto out;
843 }
844
845 for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
846 bank = &sgpio->sgpio_bank[i];
847 spin_lock_init(&bank->lock);
848 bank->parent_irq = platform_get_irq(pdev, i);
849 if (bank->parent_irq < 0) {
850 err = bank->parent_irq;
851 goto out_banks;
852 }
853
854 gpiochip_set_chained_irqchip(&sgpio->chip.gc,
855 &sirfsoc_irq_chip,
856 bank->parent_irq,
857 sirfsoc_gpio_handle_irq);
858 }
859
860 err = gpiochip_add_pin_range(&sgpio->chip.gc, dev_name(&pdev->dev),
861 0, 0, SIRFSOC_GPIO_BANK_SIZE * SIRFSOC_GPIO_NO_OF_BANKS);
862 if (err) {
863 dev_err(&pdev->dev,
864 "could not add gpiochip pin range\n");
865 goto out_no_range;
866 }
867
868 if (!of_property_read_u32_array(np, "sirf,pullups", pullups,
869 SIRFSOC_GPIO_NO_OF_BANKS))
870 sirfsoc_gpio_set_pullup(sgpio, pullups);
871
872 if (!of_property_read_u32_array(np, "sirf,pulldowns", pulldowns,
873 SIRFSOC_GPIO_NO_OF_BANKS))
874 sirfsoc_gpio_set_pulldown(sgpio, pulldowns);
875
876 return 0;
877
878out_no_range:
879out_banks:
880 if (gpiochip_remove(&sgpio->chip.gc))
881 dev_err(&pdev->dev, "could not remove gpio chip\n");
882out:
883 iounmap(regs);
884 return err;
885}
886
887static int __init sirfsoc_gpio_init(void)
888{
889
890 struct device_node *np;
891
892 np = of_find_matching_node(NULL, pinmux_ids);
893
894 if (!np)
895 return -ENODEV;
896
897 return sirfsoc_gpio_probe(np);
898}
899subsys_initcall(sirfsoc_gpio_init);
900
901MODULE_AUTHOR("Rongjun Ying <rongjun.ying@csr.com>, "
902 "Yuping Luo <yuping.luo@csr.com>, "
903 "Barry Song <baohua.song@csr.com>");
904MODULE_DESCRIPTION("SIRFSOC pin control driver");
905MODULE_LICENSE("GPL");
906
