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19#ifndef _COMEDI_H
20#define _COMEDI_H
21
22#define COMEDI_MAJORVERSION 0
23#define COMEDI_MINORVERSION 7
24#define COMEDI_MICROVERSION 76
25#define VERSION "0.7.76"
26
27
28#define COMEDI_MAJOR 98
29
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34
35#define COMEDI_NDEVICES 16
36
37
38#define COMEDI_NDEVCONFOPTS 32
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48
49
50#define COMEDI_DEVCONF_AUX_DATA3_LENGTH 25
51#define COMEDI_DEVCONF_AUX_DATA2_LENGTH 26
52#define COMEDI_DEVCONF_AUX_DATA1_LENGTH 27
53#define COMEDI_DEVCONF_AUX_DATA0_LENGTH 28
54
55#define COMEDI_DEVCONF_AUX_DATA_HI 29
56
57#define COMEDI_DEVCONF_AUX_DATA_LO 30
58#define COMEDI_DEVCONF_AUX_DATA_LENGTH 31
59
60
61#define COMEDI_NAMELEN 20
62
63
64
65#define CR_PACK(chan, rng, aref) \
66 ((((aref)&0x3)<<24) | (((rng)&0xff)<<16) | (chan))
67#define CR_PACK_FLAGS(chan, range, aref, flags) \
68 (CR_PACK(chan, range, aref) | ((flags) & CR_FLAGS_MASK))
69
70#define CR_CHAN(a) ((a)&0xffff)
71#define CR_RANGE(a) (((a)>>16)&0xff)
72#define CR_AREF(a) (((a)>>24)&0x03)
73
74#define CR_FLAGS_MASK 0xfc000000
75#define CR_ALT_FILTER (1<<26)
76#define CR_DITHER CR_ALT_FILTER
77#define CR_DEGLITCH CR_ALT_FILTER
78#define CR_ALT_SOURCE (1<<27)
79#define CR_EDGE (1<<30)
80#define CR_INVERT (1<<31)
81
82#define AREF_GROUND 0x00
83#define AREF_COMMON 0x01
84#define AREF_DIFF 0x02
85#define AREF_OTHER 0x03
86
87
88#define GPCT_RESET 0x0001
89#define GPCT_SET_SOURCE 0x0002
90#define GPCT_SET_GATE 0x0004
91#define GPCT_SET_DIRECTION 0x0008
92#define GPCT_SET_OPERATION 0x0010
93#define GPCT_ARM 0x0020
94#define GPCT_DISARM 0x0040
95#define GPCT_GET_INT_CLK_FRQ 0x0080
96
97#define GPCT_INT_CLOCK 0x0001
98#define GPCT_EXT_PIN 0x0002
99#define GPCT_NO_GATE 0x0004
100#define GPCT_UP 0x0008
101#define GPCT_DOWN 0x0010
102#define GPCT_HWUD 0x0020
103#define GPCT_SIMPLE_EVENT 0x0040
104#define GPCT_SINGLE_PERIOD 0x0080
105#define GPCT_SINGLE_PW 0x0100
106#define GPCT_CONT_PULSE_OUT 0x0200
107#define GPCT_SINGLE_PULSE_OUT 0x0400
108
109
110
111#define INSN_MASK_WRITE 0x8000000
112#define INSN_MASK_READ 0x4000000
113#define INSN_MASK_SPECIAL 0x2000000
114
115#define INSN_READ (0 | INSN_MASK_READ)
116#define INSN_WRITE (1 | INSN_MASK_WRITE)
117#define INSN_BITS (2 | INSN_MASK_READ|INSN_MASK_WRITE)
118#define INSN_CONFIG (3 | INSN_MASK_READ|INSN_MASK_WRITE)
119#define INSN_GTOD (4 | INSN_MASK_READ|INSN_MASK_SPECIAL)
120#define INSN_WAIT (5 | INSN_MASK_WRITE|INSN_MASK_SPECIAL)
121#define INSN_INTTRIG (6 | INSN_MASK_WRITE|INSN_MASK_SPECIAL)
122
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124
125
126#define TRIG_BOGUS 0x0001
127#define TRIG_DITHER 0x0002
128#define TRIG_DEGLITCH 0x0004
129
130#define TRIG_CONFIG 0x0010
131#define TRIG_WAKE_EOS 0x0020
132
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136
137
138#define CMDF_PRIORITY 0x00000008
139
140#define TRIG_RT CMDF_PRIORITY
141
142#define CMDF_WRITE 0x00000040
143#define TRIG_WRITE CMDF_WRITE
144
145#define CMDF_RAWDATA 0x00000080
146
147#define COMEDI_EV_START 0x00040000
148#define COMEDI_EV_SCAN_BEGIN 0x00080000
149#define COMEDI_EV_CONVERT 0x00100000
150#define COMEDI_EV_SCAN_END 0x00200000
151#define COMEDI_EV_STOP 0x00400000
152
153#define TRIG_ROUND_MASK 0x00030000
154#define TRIG_ROUND_NEAREST 0x00000000
155#define TRIG_ROUND_DOWN 0x00010000
156#define TRIG_ROUND_UP 0x00020000
157#define TRIG_ROUND_UP_NEXT 0x00030000
158
159
160
161#define TRIG_ANY 0xffffffff
162#define TRIG_INVALID 0x00000000
163
164#define TRIG_NONE 0x00000001
165#define TRIG_NOW 0x00000002
166#define TRIG_FOLLOW 0x00000004
167#define TRIG_TIME 0x00000008
168#define TRIG_TIMER 0x00000010
169#define TRIG_COUNT 0x00000020
170#define TRIG_EXT 0x00000040
171#define TRIG_INT 0x00000080
172#define TRIG_OTHER 0x00000100
173
174
175
176#define SDF_BUSY 0x0001
177#define SDF_BUSY_OWNER 0x0002
178#define SDF_LOCKED 0x0004
179#define SDF_LOCK_OWNER 0x0008
180#define SDF_MAXDATA 0x0010
181#define SDF_FLAGS 0x0020
182#define SDF_RANGETYPE 0x0040
183#define SDF_MODE0 0x0080
184#define SDF_MODE1 0x0100
185#define SDF_MODE2 0x0200
186#define SDF_MODE3 0x0400
187#define SDF_MODE4 0x0800
188#define SDF_CMD 0x1000
189#define SDF_SOFT_CALIBRATED 0x2000
190#define SDF_CMD_WRITE 0x4000
191#define SDF_CMD_READ 0x8000
192
193
194#define SDF_READABLE 0x00010000
195
196#define SDF_WRITABLE 0x00020000
197#define SDF_WRITEABLE SDF_WRITABLE
198
199#define SDF_INTERNAL 0x00040000
200#define SDF_GROUND 0x00100000
201#define SDF_COMMON 0x00200000
202#define SDF_DIFF 0x00400000
203#define SDF_OTHER 0x00800000
204#define SDF_DITHER 0x01000000
205#define SDF_DEGLITCH 0x02000000
206#define SDF_MMAP 0x04000000
207#define SDF_RUNNING 0x08000000
208#define SDF_LSAMPL 0x10000000
209#define SDF_PACKED 0x20000000
210
211#define SDF_PWM_COUNTER SDF_MODE0
212#define SDF_PWM_HBRIDGE SDF_MODE1
213
214
215
216enum comedi_subdevice_type {
217 COMEDI_SUBD_UNUSED,
218 COMEDI_SUBD_AI,
219 COMEDI_SUBD_AO,
220 COMEDI_SUBD_DI,
221 COMEDI_SUBD_DO,
222 COMEDI_SUBD_DIO,
223 COMEDI_SUBD_COUNTER,
224 COMEDI_SUBD_TIMER,
225 COMEDI_SUBD_MEMORY,
226 COMEDI_SUBD_CALIB,
227 COMEDI_SUBD_PROC,
228 COMEDI_SUBD_SERIAL,
229 COMEDI_SUBD_PWM
230};
231
232
233
234enum configuration_ids {
235 INSN_CONFIG_DIO_INPUT = 0,
236 INSN_CONFIG_DIO_OUTPUT = 1,
237 INSN_CONFIG_DIO_OPENDRAIN = 2,
238 INSN_CONFIG_ANALOG_TRIG = 16,
239
240
241
242 INSN_CONFIG_ALT_SOURCE = 20,
243 INSN_CONFIG_DIGITAL_TRIG = 21,
244 INSN_CONFIG_BLOCK_SIZE = 22,
245 INSN_CONFIG_TIMER_1 = 23,
246 INSN_CONFIG_FILTER = 24,
247 INSN_CONFIG_CHANGE_NOTIFY = 25,
248
249 INSN_CONFIG_SERIAL_CLOCK = 26,
250 INSN_CONFIG_BIDIRECTIONAL_DATA = 27,
251 INSN_CONFIG_DIO_QUERY = 28,
252 INSN_CONFIG_PWM_OUTPUT = 29,
253 INSN_CONFIG_GET_PWM_OUTPUT = 30,
254 INSN_CONFIG_ARM = 31,
255 INSN_CONFIG_DISARM = 32,
256 INSN_CONFIG_GET_COUNTER_STATUS = 33,
257 INSN_CONFIG_RESET = 34,
258
259 INSN_CONFIG_GPCT_SINGLE_PULSE_GENERATOR = 1001,
260
261 INSN_CONFIG_GPCT_PULSE_TRAIN_GENERATOR = 1002,
262
263 INSN_CONFIG_GPCT_QUADRATURE_ENCODER = 1003,
264 INSN_CONFIG_SET_GATE_SRC = 2001,
265 INSN_CONFIG_GET_GATE_SRC = 2002,
266
267 INSN_CONFIG_SET_CLOCK_SRC = 2003,
268 INSN_CONFIG_GET_CLOCK_SRC = 2004,
269 INSN_CONFIG_SET_OTHER_SRC = 2005,
270
271
272
273 INSN_CONFIG_GET_HARDWARE_BUFFER_SIZE = 2006,
274 INSN_CONFIG_SET_COUNTER_MODE = 4097,
275
276 INSN_CONFIG_8254_SET_MODE = INSN_CONFIG_SET_COUNTER_MODE,
277 INSN_CONFIG_8254_READ_STATUS = 4098,
278 INSN_CONFIG_SET_ROUTING = 4099,
279 INSN_CONFIG_GET_ROUTING = 4109,
280
281 INSN_CONFIG_PWM_SET_PERIOD = 5000,
282 INSN_CONFIG_PWM_GET_PERIOD = 5001,
283 INSN_CONFIG_GET_PWM_STATUS = 5002,
284
285
286 INSN_CONFIG_PWM_SET_H_BRIDGE = 5003,
287
288 INSN_CONFIG_PWM_GET_H_BRIDGE = 5004
289};
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323enum comedi_digital_trig_op {
324 COMEDI_DIGITAL_TRIG_DISABLE = 0,
325 COMEDI_DIGITAL_TRIG_ENABLE_EDGES = 1,
326 COMEDI_DIGITAL_TRIG_ENABLE_LEVELS = 2
327};
328
329enum comedi_io_direction {
330 COMEDI_INPUT = 0,
331 COMEDI_OUTPUT = 1,
332 COMEDI_OPENDRAIN = 2
333};
334
335enum comedi_support_level {
336 COMEDI_UNKNOWN_SUPPORT = 0,
337 COMEDI_SUPPORTED,
338 COMEDI_UNSUPPORTED
339};
340
341
342
343#define CIO 'd'
344#define COMEDI_DEVCONFIG _IOW(CIO, 0, struct comedi_devconfig)
345#define COMEDI_DEVINFO _IOR(CIO, 1, struct comedi_devinfo)
346#define COMEDI_SUBDINFO _IOR(CIO, 2, struct comedi_subdinfo)
347#define COMEDI_CHANINFO _IOR(CIO, 3, struct comedi_chaninfo)
348#define COMEDI_TRIG _IOWR(CIO, 4, comedi_trig)
349#define COMEDI_LOCK _IO(CIO, 5)
350#define COMEDI_UNLOCK _IO(CIO, 6)
351#define COMEDI_CANCEL _IO(CIO, 7)
352#define COMEDI_RANGEINFO _IOR(CIO, 8, struct comedi_rangeinfo)
353#define COMEDI_CMD _IOR(CIO, 9, struct comedi_cmd)
354#define COMEDI_CMDTEST _IOR(CIO, 10, struct comedi_cmd)
355#define COMEDI_INSNLIST _IOR(CIO, 11, struct comedi_insnlist)
356#define COMEDI_INSN _IOR(CIO, 12, struct comedi_insn)
357#define COMEDI_BUFCONFIG _IOR(CIO, 13, struct comedi_bufconfig)
358#define COMEDI_BUFINFO _IOWR(CIO, 14, struct comedi_bufinfo)
359#define COMEDI_POLL _IO(CIO, 15)
360
361
362
363struct comedi_trig {
364 unsigned int subdev;
365 unsigned int mode;
366 unsigned int flags;
367 unsigned int n_chan;
368 unsigned int *chanlist;
369 short *data;
370 unsigned int n;
371 unsigned int trigsrc;
372 unsigned int trigvar;
373 unsigned int trigvar1;
374 unsigned int data_len;
375 unsigned int unused[3];
376};
377
378struct comedi_insn {
379 unsigned int insn;
380 unsigned int n;
381 unsigned int __user *data;
382 unsigned int subdev;
383 unsigned int chanspec;
384 unsigned int unused[3];
385};
386
387struct comedi_insnlist {
388 unsigned int n_insns;
389 struct comedi_insn __user *insns;
390};
391
392struct comedi_cmd {
393 unsigned int subdev;
394 unsigned int flags;
395
396 unsigned int start_src;
397 unsigned int start_arg;
398
399 unsigned int scan_begin_src;
400 unsigned int scan_begin_arg;
401
402 unsigned int convert_src;
403 unsigned int convert_arg;
404
405 unsigned int scan_end_src;
406 unsigned int scan_end_arg;
407
408 unsigned int stop_src;
409 unsigned int stop_arg;
410
411 unsigned int *chanlist;
412 unsigned int chanlist_len;
413
414 short __user *data;
415 unsigned int data_len;
416};
417
418struct comedi_chaninfo {
419 unsigned int subdev;
420 unsigned int __user *maxdata_list;
421 unsigned int __user *flaglist;
422 unsigned int __user *rangelist;
423 unsigned int unused[4];
424};
425
426struct comedi_rangeinfo {
427 unsigned int range_type;
428 void __user *range_ptr;
429};
430
431struct comedi_krange {
432 int min;
433 int max;
434 unsigned int flags;
435};
436
437struct comedi_subdinfo {
438 unsigned int type;
439 unsigned int n_chan;
440 unsigned int subd_flags;
441 unsigned int timer_type;
442 unsigned int len_chanlist;
443 unsigned int maxdata;
444 unsigned int flags;
445 unsigned int range_type;
446 unsigned int settling_time_0;
447
448 unsigned insn_bits_support;
449 unsigned int unused[8];
450};
451
452struct comedi_devinfo {
453 unsigned int version_code;
454 unsigned int n_subdevs;
455 char driver_name[COMEDI_NAMELEN];
456 char board_name[COMEDI_NAMELEN];
457 int read_subdevice;
458 int write_subdevice;
459 int unused[30];
460};
461
462struct comedi_devconfig {
463 char board_name[COMEDI_NAMELEN];
464 int options[COMEDI_NDEVCONFOPTS];
465};
466
467struct comedi_bufconfig {
468 unsigned int subdevice;
469 unsigned int flags;
470
471 unsigned int maximum_size;
472 unsigned int size;
473
474 unsigned int unused[4];
475};
476
477struct comedi_bufinfo {
478 unsigned int subdevice;
479 unsigned int bytes_read;
480
481 unsigned int buf_write_ptr;
482 unsigned int buf_read_ptr;
483 unsigned int buf_write_count;
484 unsigned int buf_read_count;
485
486 unsigned int bytes_written;
487
488 unsigned int unused[4];
489};
490
491
492
493#define __RANGE(a, b) ((((a)&0xffff)<<16)|((b)&0xffff))
494
495#define RANGE_OFFSET(a) (((a)>>16)&0xffff)
496#define RANGE_LENGTH(b) ((b)&0xffff)
497
498#define RF_UNIT(flags) ((flags)&0xff)
499#define RF_EXTERNAL (1<<8)
500
501#define UNIT_volt 0
502#define UNIT_mA 1
503#define UNIT_none 2
504
505#define COMEDI_MIN_SPEED ((unsigned int)0xffffffff)
506
507
508
509
510#define COMEDI_CB_EOS 1
511#define COMEDI_CB_EOA 2
512#define COMEDI_CB_BLOCK 4
513
514#define COMEDI_CB_EOBUF 8
515#define COMEDI_CB_ERROR 16
516#define COMEDI_CB_OVERFLOW 32
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541enum i8254_mode {
542 I8254_MODE0 = (0 << 1),
543 I8254_MODE1 = (1 << 1),
544 I8254_MODE2 = (2 << 1),
545 I8254_MODE3 = (3 << 1),
546 I8254_MODE4 = (4 << 1),
547 I8254_MODE5 = (5 << 1),
548
549 I8254_BCD = 1,
550
551 I8254_BINARY = 0
552};
553
554#define NI_USUAL_PFI_SELECT(x) (((x) < 10) ? (0x1 + (x)) : (0xb + (x)))
555#define NI_USUAL_RTSI_SELECT(x) (((x) < 7) ? (0xb + (x)) : 0x1b)
556
557
558
559#define NI_GPCT_COUNTING_MODE_SHIFT 16
560#define NI_GPCT_INDEX_PHASE_BITSHIFT 20
561#define NI_GPCT_COUNTING_DIRECTION_SHIFT 24
562enum ni_gpct_mode_bits {
563 NI_GPCT_GATE_ON_BOTH_EDGES_BIT = 0x4,
564 NI_GPCT_EDGE_GATE_MODE_MASK = 0x18,
565 NI_GPCT_EDGE_GATE_STARTS_STOPS_BITS = 0x0,
566 NI_GPCT_EDGE_GATE_STOPS_STARTS_BITS = 0x8,
567 NI_GPCT_EDGE_GATE_STARTS_BITS = 0x10,
568 NI_GPCT_EDGE_GATE_NO_STARTS_NO_STOPS_BITS = 0x18,
569 NI_GPCT_STOP_MODE_MASK = 0x60,
570 NI_GPCT_STOP_ON_GATE_BITS = 0x00,
571 NI_GPCT_STOP_ON_GATE_OR_TC_BITS = 0x20,
572 NI_GPCT_STOP_ON_GATE_OR_SECOND_TC_BITS = 0x40,
573 NI_GPCT_LOAD_B_SELECT_BIT = 0x80,
574 NI_GPCT_OUTPUT_MODE_MASK = 0x300,
575 NI_GPCT_OUTPUT_TC_PULSE_BITS = 0x100,
576 NI_GPCT_OUTPUT_TC_TOGGLE_BITS = 0x200,
577 NI_GPCT_OUTPUT_TC_OR_GATE_TOGGLE_BITS = 0x300,
578 NI_GPCT_HARDWARE_DISARM_MASK = 0xc00,
579 NI_GPCT_NO_HARDWARE_DISARM_BITS = 0x000,
580 NI_GPCT_DISARM_AT_TC_BITS = 0x400,
581 NI_GPCT_DISARM_AT_GATE_BITS = 0x800,
582 NI_GPCT_DISARM_AT_TC_OR_GATE_BITS = 0xc00,
583 NI_GPCT_LOADING_ON_TC_BIT = 0x1000,
584 NI_GPCT_LOADING_ON_GATE_BIT = 0x4000,
585 NI_GPCT_COUNTING_MODE_MASK = 0x7 << NI_GPCT_COUNTING_MODE_SHIFT,
586 NI_GPCT_COUNTING_MODE_NORMAL_BITS =
587 0x0 << NI_GPCT_COUNTING_MODE_SHIFT,
588 NI_GPCT_COUNTING_MODE_QUADRATURE_X1_BITS =
589 0x1 << NI_GPCT_COUNTING_MODE_SHIFT,
590 NI_GPCT_COUNTING_MODE_QUADRATURE_X2_BITS =
591 0x2 << NI_GPCT_COUNTING_MODE_SHIFT,
592 NI_GPCT_COUNTING_MODE_QUADRATURE_X4_BITS =
593 0x3 << NI_GPCT_COUNTING_MODE_SHIFT,
594 NI_GPCT_COUNTING_MODE_TWO_PULSE_BITS =
595 0x4 << NI_GPCT_COUNTING_MODE_SHIFT,
596 NI_GPCT_COUNTING_MODE_SYNC_SOURCE_BITS =
597 0x6 << NI_GPCT_COUNTING_MODE_SHIFT,
598 NI_GPCT_INDEX_PHASE_MASK = 0x3 << NI_GPCT_INDEX_PHASE_BITSHIFT,
599 NI_GPCT_INDEX_PHASE_LOW_A_LOW_B_BITS =
600 0x0 << NI_GPCT_INDEX_PHASE_BITSHIFT,
601 NI_GPCT_INDEX_PHASE_LOW_A_HIGH_B_BITS =
602 0x1 << NI_GPCT_INDEX_PHASE_BITSHIFT,
603 NI_GPCT_INDEX_PHASE_HIGH_A_LOW_B_BITS =
604 0x2 << NI_GPCT_INDEX_PHASE_BITSHIFT,
605 NI_GPCT_INDEX_PHASE_HIGH_A_HIGH_B_BITS =
606 0x3 << NI_GPCT_INDEX_PHASE_BITSHIFT,
607 NI_GPCT_INDEX_ENABLE_BIT = 0x400000,
608 NI_GPCT_COUNTING_DIRECTION_MASK =
609 0x3 << NI_GPCT_COUNTING_DIRECTION_SHIFT,
610 NI_GPCT_COUNTING_DIRECTION_DOWN_BITS =
611 0x00 << NI_GPCT_COUNTING_DIRECTION_SHIFT,
612 NI_GPCT_COUNTING_DIRECTION_UP_BITS =
613 0x1 << NI_GPCT_COUNTING_DIRECTION_SHIFT,
614 NI_GPCT_COUNTING_DIRECTION_HW_UP_DOWN_BITS =
615 0x2 << NI_GPCT_COUNTING_DIRECTION_SHIFT,
616 NI_GPCT_COUNTING_DIRECTION_HW_GATE_BITS =
617 0x3 << NI_GPCT_COUNTING_DIRECTION_SHIFT,
618 NI_GPCT_RELOAD_SOURCE_MASK = 0xc000000,
619 NI_GPCT_RELOAD_SOURCE_FIXED_BITS = 0x0,
620 NI_GPCT_RELOAD_SOURCE_SWITCHING_BITS = 0x4000000,
621 NI_GPCT_RELOAD_SOURCE_GATE_SELECT_BITS = 0x8000000,
622 NI_GPCT_OR_GATE_BIT = 0x10000000,
623 NI_GPCT_INVERT_OUTPUT_BIT = 0x20000000
624};
625
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627
628enum ni_gpct_clock_source_bits {
629 NI_GPCT_CLOCK_SRC_SELECT_MASK = 0x3f,
630 NI_GPCT_TIMEBASE_1_CLOCK_SRC_BITS = 0x0,
631 NI_GPCT_TIMEBASE_2_CLOCK_SRC_BITS = 0x1,
632 NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS = 0x2,
633 NI_GPCT_LOGIC_LOW_CLOCK_SRC_BITS = 0x3,
634 NI_GPCT_NEXT_GATE_CLOCK_SRC_BITS = 0x4,
635 NI_GPCT_NEXT_TC_CLOCK_SRC_BITS = 0x5,
636
637 NI_GPCT_SOURCE_PIN_i_CLOCK_SRC_BITS = 0x6,
638 NI_GPCT_PXI10_CLOCK_SRC_BITS = 0x7,
639 NI_GPCT_PXI_STAR_TRIGGER_CLOCK_SRC_BITS = 0x8,
640 NI_GPCT_ANALOG_TRIGGER_OUT_CLOCK_SRC_BITS = 0x9,
641 NI_GPCT_PRESCALE_MODE_CLOCK_SRC_MASK = 0x30000000,
642 NI_GPCT_NO_PRESCALE_CLOCK_SRC_BITS = 0x0,
643
644 NI_GPCT_PRESCALE_X2_CLOCK_SRC_BITS = 0x10000000,
645
646 NI_GPCT_PRESCALE_X8_CLOCK_SRC_BITS = 0x20000000,
647 NI_GPCT_INVERT_CLOCK_SRC_BIT = 0x80000000
648};
649
650
651#define NI_GPCT_SOURCE_PIN_CLOCK_SRC_BITS(x) (0x10 + (x))
652
653#define NI_GPCT_RTSI_CLOCK_SRC_BITS(x) (0x18 + (x))
654
655
656#define NI_GPCT_PFI_CLOCK_SRC_BITS(x) (0x20 + (x))
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660
661enum ni_gpct_gate_select {
662
663 NI_GPCT_TIMESTAMP_MUX_GATE_SELECT = 0x0,
664 NI_GPCT_AI_START2_GATE_SELECT = 0x12,
665 NI_GPCT_PXI_STAR_TRIGGER_GATE_SELECT = 0x13,
666 NI_GPCT_NEXT_OUT_GATE_SELECT = 0x14,
667 NI_GPCT_AI_START1_GATE_SELECT = 0x1c,
668 NI_GPCT_NEXT_SOURCE_GATE_SELECT = 0x1d,
669 NI_GPCT_ANALOG_TRIGGER_OUT_GATE_SELECT = 0x1e,
670 NI_GPCT_LOGIC_LOW_GATE_SELECT = 0x1f,
671
672 NI_GPCT_SOURCE_PIN_i_GATE_SELECT = 0x100,
673 NI_GPCT_GATE_PIN_i_GATE_SELECT = 0x101,
674
675 NI_GPCT_UP_DOWN_PIN_i_GATE_SELECT = 0x201,
676 NI_GPCT_SELECTED_GATE_GATE_SELECT = 0x21e,
677
678
679
680 NI_GPCT_DISABLED_GATE_SELECT = 0x8000,
681};
682
683#define NI_GPCT_GATE_PIN_GATE_SELECT(x) (0x102 + (x))
684#define NI_GPCT_RTSI_GATE_SELECT(x) NI_USUAL_RTSI_SELECT(x)
685#define NI_GPCT_PFI_GATE_SELECT(x) NI_USUAL_PFI_SELECT(x)
686#define NI_GPCT_UP_DOWN_PIN_GATE_SELECT(x) (0x202 + (x))
687
688
689
690enum ni_gpct_other_index {
691 NI_GPCT_SOURCE_ENCODER_A,
692 NI_GPCT_SOURCE_ENCODER_B,
693 NI_GPCT_SOURCE_ENCODER_Z
694};
695
696enum ni_gpct_other_select {
697
698
699 NI_GPCT_DISABLED_OTHER_SELECT = 0x8000,
700};
701
702#define NI_GPCT_PFI_OTHER_SELECT(x) NI_USUAL_PFI_SELECT(x)
703
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706enum ni_gpct_arm_source {
707 NI_GPCT_ARM_IMMEDIATE = 0x0,
708 NI_GPCT_ARM_PAIRED_IMMEDIATE = 0x1,
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716 NI_GPCT_ARM_UNKNOWN = 0x1000,
717};
718
719
720enum ni_gpct_filter_select {
721 NI_GPCT_FILTER_OFF = 0x0,
722 NI_GPCT_FILTER_TIMEBASE_3_SYNC = 0x1,
723 NI_GPCT_FILTER_100x_TIMEBASE_1 = 0x2,
724 NI_GPCT_FILTER_20x_TIMEBASE_1 = 0x3,
725 NI_GPCT_FILTER_10x_TIMEBASE_1 = 0x4,
726 NI_GPCT_FILTER_2x_TIMEBASE_1 = 0x5,
727 NI_GPCT_FILTER_2x_TIMEBASE_3 = 0x6
728};
729
730
731
732enum ni_pfi_filter_select {
733 NI_PFI_FILTER_OFF = 0x0,
734 NI_PFI_FILTER_125ns = 0x1,
735 NI_PFI_FILTER_6425ns = 0x2,
736 NI_PFI_FILTER_2550us = 0x3
737};
738
739
740enum ni_mio_clock_source {
741 NI_MIO_INTERNAL_CLOCK = 0,
742 NI_MIO_RTSI_CLOCK = 1,
743
744
745 NI_MIO_PLL_PXI_STAR_TRIGGER_CLOCK = 2,
746 NI_MIO_PLL_PXI10_CLOCK = 3,
747 NI_MIO_PLL_RTSI0_CLOCK = 4
748};
749
750#define NI_MIO_PLL_RTSI_CLOCK(x) (NI_MIO_PLL_RTSI0_CLOCK + (x))
751
752
753
754
755enum ni_rtsi_routing {
756 NI_RTSI_OUTPUT_ADR_START1 = 0,
757 NI_RTSI_OUTPUT_ADR_START2 = 1,
758 NI_RTSI_OUTPUT_SCLKG = 2,
759 NI_RTSI_OUTPUT_DACUPDN = 3,
760 NI_RTSI_OUTPUT_DA_START1 = 4,
761 NI_RTSI_OUTPUT_G_SRC0 = 5,
762 NI_RTSI_OUTPUT_G_GATE0 = 6,
763 NI_RTSI_OUTPUT_RGOUT0 = 7,
764 NI_RTSI_OUTPUT_RTSI_BRD_0 = 8,
765 NI_RTSI_OUTPUT_RTSI_OSC = 12
766
767};
768
769#define NI_RTSI_OUTPUT_RTSI_BRD(x) (NI_RTSI_OUTPUT_RTSI_BRD_0 + (x))
770
771
772
773
774
775
776enum ni_pfi_routing {
777 NI_PFI_OUTPUT_PFI_DEFAULT = 0,
778 NI_PFI_OUTPUT_AI_START1 = 1,
779 NI_PFI_OUTPUT_AI_START2 = 2,
780 NI_PFI_OUTPUT_AI_CONVERT = 3,
781 NI_PFI_OUTPUT_G_SRC1 = 4,
782 NI_PFI_OUTPUT_G_GATE1 = 5,
783 NI_PFI_OUTPUT_AO_UPDATE_N = 6,
784 NI_PFI_OUTPUT_AO_START1 = 7,
785 NI_PFI_OUTPUT_AI_START_PULSE = 8,
786 NI_PFI_OUTPUT_G_SRC0 = 9,
787 NI_PFI_OUTPUT_G_GATE0 = 10,
788 NI_PFI_OUTPUT_EXT_STROBE = 11,
789 NI_PFI_OUTPUT_AI_EXT_MUX_CLK = 12,
790 NI_PFI_OUTPUT_GOUT0 = 13,
791 NI_PFI_OUTPUT_GOUT1 = 14,
792 NI_PFI_OUTPUT_FREQ_OUT = 15,
793 NI_PFI_OUTPUT_PFI_DO = 16,
794 NI_PFI_OUTPUT_I_ATRIG = 17,
795 NI_PFI_OUTPUT_RTSI0 = 18,
796 NI_PFI_OUTPUT_PXI_STAR_TRIGGER_IN = 26,
797 NI_PFI_OUTPUT_SCXI_TRIG1 = 27,
798 NI_PFI_OUTPUT_DIO_CHANGE_DETECT_RTSI = 28,
799 NI_PFI_OUTPUT_CDI_SAMPLE = 29,
800 NI_PFI_OUTPUT_CDO_UPDATE = 30
801};
802
803#define NI_PFI_OUTPUT_RTSI(x) (NI_PFI_OUTPUT_RTSI0 + (x))
804
805
806
807
808
809
810
811enum ni_660x_pfi_routing {
812 NI_660X_PFI_OUTPUT_COUNTER = 1,
813 NI_660X_PFI_OUTPUT_DIO = 2,
814};
815
816
817
818
819#define NI_EXT_PFI(x) (NI_USUAL_PFI_SELECT(x) - 1)
820#define NI_EXT_RTSI(x) (NI_USUAL_RTSI_SELECT(x) - 1)
821
822
823enum comedi_counter_status_flags {
824 COMEDI_COUNTER_ARMED = 0x1,
825 COMEDI_COUNTER_COUNTING = 0x2,
826 COMEDI_COUNTER_TERMINAL_COUNT = 0x4,
827};
828
829
830
831
832enum ni_m_series_cdio_scan_begin_src {
833 NI_CDIO_SCAN_BEGIN_SRC_GROUND = 0,
834 NI_CDIO_SCAN_BEGIN_SRC_AI_START = 18,
835 NI_CDIO_SCAN_BEGIN_SRC_AI_CONVERT = 19,
836 NI_CDIO_SCAN_BEGIN_SRC_PXI_STAR_TRIGGER = 20,
837 NI_CDIO_SCAN_BEGIN_SRC_G0_OUT = 28,
838 NI_CDIO_SCAN_BEGIN_SRC_G1_OUT = 29,
839 NI_CDIO_SCAN_BEGIN_SRC_ANALOG_TRIGGER = 30,
840 NI_CDIO_SCAN_BEGIN_SRC_AO_UPDATE = 31,
841 NI_CDIO_SCAN_BEGIN_SRC_FREQ_OUT = 32,
842 NI_CDIO_SCAN_BEGIN_SRC_DIO_CHANGE_DETECT_IRQ = 33
843};
844
845#define NI_CDIO_SCAN_BEGIN_SRC_PFI(x) NI_USUAL_PFI_SELECT(x)
846#define NI_CDIO_SCAN_BEGIN_SRC_RTSI(x) NI_USUAL_RTSI_SELECT(x)
847
848
849
850
851#define NI_AO_SCAN_BEGIN_SRC_PFI(x) NI_USUAL_PFI_SELECT(x)
852#define NI_AO_SCAN_BEGIN_SRC_RTSI(x) NI_USUAL_RTSI_SELECT(x)
853
854
855
856enum ni_freq_out_clock_source_bits {
857 NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC,
858 NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC
859};
860
861
862
863enum amplc_dio_clock_source {
864 AMPLC_DIO_CLK_CLKN,
865
866
867
868 AMPLC_DIO_CLK_10MHZ,
869 AMPLC_DIO_CLK_1MHZ,
870 AMPLC_DIO_CLK_100KHZ,
871 AMPLC_DIO_CLK_10KHZ,
872 AMPLC_DIO_CLK_1KHZ,
873 AMPLC_DIO_CLK_OUTNM1,
874
875
876
877
878
879
880 AMPLC_DIO_CLK_EXT,
881
882 AMPLC_DIO_CLK_VCC,
883 AMPLC_DIO_CLK_GND,
884 AMPLC_DIO_CLK_PAT_PRESENT,
885 AMPLC_DIO_CLK_20MHZ
886};
887
888
889
890enum amplc_dio_ts_clock_src {
891 AMPLC_DIO_TS_CLK_1GHZ,
892 AMPLC_DIO_TS_CLK_1MHZ,
893 AMPLC_DIO_TS_CLK_1KHZ
894};
895
896
897
898enum amplc_dio_gate_source {
899 AMPLC_DIO_GAT_VCC,
900 AMPLC_DIO_GAT_GND,
901 AMPLC_DIO_GAT_GATN,
902 AMPLC_DIO_GAT_NOUTNM2,
903
904
905
906
907
908
909 AMPLC_DIO_GAT_RESERVED4,
910 AMPLC_DIO_GAT_RESERVED5,
911 AMPLC_DIO_GAT_RESERVED6,
912 AMPLC_DIO_GAT_RESERVED7,
913
914 AMPLC_DIO_GAT_NGATN = 6,
915 AMPLC_DIO_GAT_OUTNM2,
916
917 AMPLC_DIO_GAT_PAT_PRESENT,
918 AMPLC_DIO_GAT_PAT_OCCURRED,
919 AMPLC_DIO_GAT_PAT_GONE,
920 AMPLC_DIO_GAT_NPAT_PRESENT,
921 AMPLC_DIO_GAT_NPAT_OCCURRED,
922 AMPLC_DIO_GAT_NPAT_GONE
923};
924
925
926
927
928
929
930enum ke_counter_clock_source {
931 KE_CLK_20MHZ,
932 KE_CLK_4MHZ,
933 KE_CLK_EXT
934};
935
936#endif
937