1/* 2 * Copyright 2003 Digi International (www.digi.com) 3 * Scott H Kilau <Scott_Kilau at digi dot com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2, or (at your option) 8 * any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY, EXPRESS OR IMPLIED; without even the 12 * implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR 13 * PURPOSE. See the GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 18 * 19 * NOTE: THIS IS A SHARED HEADER. DO NOT CHANGE CODING STYLE!!! 20 * 21 */ 22 23#ifndef __DGNC_CLS_H 24#define __DGNC_CLS_H 25 26#include "dgnc_types.h" 27 28 29/************************************************************************ 30 * Per channel/port Classic UART structure * 31 ************************************************************************ 32 * Base Structure Entries Usage Meanings to Host * 33 * * 34 * W = read write R = read only * 35 * U = Unused. * 36 ************************************************************************/ 37 38struct cls_uart_struct { 39 u8 txrx; /* WR RHR/THR - Holding Reg */ 40 u8 ier; /* WR IER - Interrupt Enable Reg */ 41 u8 isr_fcr; /* WR ISR/FCR - Interrupt Status Reg/Fifo Control Reg */ 42 u8 lcr; /* WR LCR - Line Control Reg */ 43 u8 mcr; /* WR MCR - Modem Control Reg */ 44 u8 lsr; /* WR LSR - Line Status Reg */ 45 u8 msr; /* WR MSR - Modem Status Reg */ 46 u8 spr; /* WR SPR - Scratch Pad Reg */ 47}; 48 49/* Where to read the interrupt register (8bits) */ 50#define UART_CLASSIC_POLL_ADDR_OFFSET 0x40 51 52#define UART_EXAR654_ENHANCED_REGISTER_SET 0xBF 53 54#define UART_16654_FCR_TXTRIGGER_8 0x0 55#define UART_16654_FCR_TXTRIGGER_16 0x10 56#define UART_16654_FCR_TXTRIGGER_32 0x20 57#define UART_16654_FCR_TXTRIGGER_56 0x30 58 59#define UART_16654_FCR_RXTRIGGER_8 0x0 60#define UART_16654_FCR_RXTRIGGER_16 0x40 61#define UART_16654_FCR_RXTRIGGER_56 0x80 62#define UART_16654_FCR_RXTRIGGER_60 0xC0 63 64#define UART_IIR_CTSRTS 0x20 /* Received CTS/RTS change of state */ 65#define UART_IIR_RDI_TIMEOUT 0x0C /* Receiver data TIMEOUT */ 66 67/* 68 * These are the EXTENDED definitions for the Exar 654's Interrupt 69 * Enable Register. 70 */ 71#define UART_EXAR654_EFR_ECB 0x10 /* Enhanced control bit */ 72#define UART_EXAR654_EFR_IXON 0x2 /* Receiver compares Xon1/Xoff1 */ 73#define UART_EXAR654_EFR_IXOFF 0x8 /* Transmit Xon1/Xoff1 */ 74#define UART_EXAR654_EFR_RTSDTR 0x40 /* Auto RTS/DTR Flow Control Enable */ 75#define UART_EXAR654_EFR_CTSDSR 0x80 /* Auto CTS/DSR Flow COntrol Enable */ 76 77#define UART_EXAR654_XOFF_DETECT 0x1 /* Indicates whether chip saw an incoming XOFF char */ 78#define UART_EXAR654_XON_DETECT 0x2 /* Indicates whether chip saw an incoming XON char */ 79 80#define UART_EXAR654_IER_XOFF 0x20 /* Xoff Interrupt Enable */ 81#define UART_EXAR654_IER_RTSDTR 0x40 /* Output Interrupt Enable */ 82#define UART_EXAR654_IER_CTSDSR 0x80 /* Input Interrupt Enable */ 83 84/* 85 * Our Global Variables 86 */ 87extern struct board_ops dgnc_cls_ops; 88 89#endif 90