1/* 2 * Copyright © 2005 Agere Systems Inc. 3 * All rights reserved. 4 * http://www.agere.com 5 * 6 * SOFTWARE LICENSE 7 * 8 * This software is provided subject to the following terms and conditions, 9 * which you should read carefully before using the software. Using this 10 * software indicates your acceptance of these terms and conditions. If you do 11 * not agree with these terms and conditions, do not use the software. 12 * 13 * Copyright © 2005 Agere Systems Inc. 14 * All rights reserved. 15 * 16 * Redistribution and use in source or binary forms, with or without 17 * modifications, are permitted provided that the following conditions are met: 18 * 19 * . Redistributions of source code must retain the above copyright notice, this 20 * list of conditions and the following Disclaimer as comments in the code as 21 * well as in the documentation and/or other materials provided with the 22 * distribution. 23 * 24 * . Redistributions in binary form must reproduce the above copyright notice, 25 * this list of conditions and the following Disclaimer in the documentation 26 * and/or other materials provided with the distribution. 27 * 28 * . Neither the name of Agere Systems Inc. nor the names of the contributors 29 * may be used to endorse or promote products derived from this software 30 * without specific prior written permission. 31 * 32 * Disclaimer 33 * 34 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, 35 * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF 36 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY 37 * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN 38 * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY 39 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 40 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 41 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 42 * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT 43 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 44 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH 45 * DAMAGE. 46 * 47 */ 48 49#define DRIVER_NAME "et131x" 50#define DRIVER_VERSION "v2.0" 51 52/* EEPROM registers */ 53 54/* LBCIF Register Groups (addressed via 32-bit offsets) */ 55#define LBCIF_DWORD0_GROUP 0xAC 56#define LBCIF_DWORD1_GROUP 0xB0 57 58/* LBCIF Registers (addressed via 8-bit offsets) */ 59#define LBCIF_ADDRESS_REGISTER 0xAC 60#define LBCIF_DATA_REGISTER 0xB0 61#define LBCIF_CONTROL_REGISTER 0xB1 62#define LBCIF_STATUS_REGISTER 0xB2 63 64/* LBCIF Control Register Bits */ 65#define LBCIF_CONTROL_SEQUENTIAL_READ 0x01 66#define LBCIF_CONTROL_PAGE_WRITE 0x02 67#define LBCIF_CONTROL_EEPROM_RELOAD 0x08 68#define LBCIF_CONTROL_TWO_BYTE_ADDR 0x20 69#define LBCIF_CONTROL_I2C_WRITE 0x40 70#define LBCIF_CONTROL_LBCIF_ENABLE 0x80 71 72/* LBCIF Status Register Bits */ 73#define LBCIF_STATUS_PHY_QUEUE_AVAIL 0x01 74#define LBCIF_STATUS_I2C_IDLE 0x02 75#define LBCIF_STATUS_ACK_ERROR 0x04 76#define LBCIF_STATUS_GENERAL_ERROR 0x08 77#define LBCIF_STATUS_CHECKSUM_ERROR 0x40 78#define LBCIF_STATUS_EEPROM_PRESENT 0x80 79 80/* START OF GLOBAL REGISTER ADDRESS MAP */ 81 82/* 83 * 10bit registers 84 * 85 * Tx queue start address reg in global address map at address 0x0000 86 * tx queue end address reg in global address map at address 0x0004 87 * rx queue start address reg in global address map at address 0x0008 88 * rx queue end address reg in global address map at address 0x000C 89 */ 90 91/* 92 * structure for power management control status reg in global address map 93 * located at address 0x0010 94 * jagcore_rx_rdy bit 9 95 * jagcore_tx_rdy bit 8 96 * phy_lped_en bit 7 97 * phy_sw_coma bit 6 98 * rxclk_gate bit 5 99 * txclk_gate bit 4 100 * sysclk_gate bit 3 101 * jagcore_rx_en bit 2 102 * jagcore_tx_en bit 1 103 * gigephy_en bit 0 104 */ 105 106#define ET_PM_PHY_SW_COMA 0x40 107#define ET_PMCSR_INIT 0x38 108 109/* 110 * Interrupt status reg at address 0x0018 111 */ 112 113#define ET_INTR_TXDMA_ISR 0x00000008 114#define ET_INTR_TXDMA_ERR 0x00000010 115#define ET_INTR_RXDMA_XFR_DONE 0x00000020 116#define ET_INTR_RXDMA_FB_R0_LOW 0x00000040 117#define ET_INTR_RXDMA_FB_R1_LOW 0x00000080 118#define ET_INTR_RXDMA_STAT_LOW 0x00000100 119#define ET_INTR_RXDMA_ERR 0x00000200 120#define ET_INTR_WATCHDOG 0x00004000 121#define ET_INTR_WOL 0x00008000 122#define ET_INTR_PHY 0x00010000 123#define ET_INTR_TXMAC 0x00020000 124#define ET_INTR_RXMAC 0x00040000 125#define ET_INTR_MAC_STAT 0x00080000 126#define ET_INTR_SLV_TIMEOUT 0x00100000 127 128/* 129 * Interrupt mask register at address 0x001C 130 * Interrupt alias clear mask reg at address 0x0020 131 * Interrupt status alias reg at address 0x0024 132 * 133 * Same masks as above 134 */ 135 136/* 137 * Software reset reg at address 0x0028 138 * 0: txdma_sw_reset 139 * 1: rxdma_sw_reset 140 * 2: txmac_sw_reset 141 * 3: rxmac_sw_reset 142 * 4: mac_sw_reset 143 * 5: mac_stat_sw_reset 144 * 6: mmc_sw_reset 145 *31: selfclr_disable 146 */ 147 148#define ET_RESET_ALL 0x007F 149 150/* 151 * SLV Timer reg at address 0x002C (low 24 bits) 152 */ 153 154/* 155 * MSI Configuration reg at address 0x0030 156 */ 157 158#define ET_MSI_VECTOR 0x0000001F 159#define ET_MSI_TC 0x00070000 160 161/* 162 * Loopback reg located at address 0x0034 163 */ 164 165#define ET_LOOP_MAC 0x00000001 166#define ET_LOOP_DMA 0x00000002 167 168/* 169 * GLOBAL Module of JAGCore Address Mapping 170 * Located at address 0x0000 171 */ 172struct global_regs { /* Location: */ 173 u32 txq_start_addr; /* 0x0000 */ 174 u32 txq_end_addr; /* 0x0004 */ 175 u32 rxq_start_addr; /* 0x0008 */ 176 u32 rxq_end_addr; /* 0x000C */ 177 u32 pm_csr; /* 0x0010 */ 178 u32 unused; /* 0x0014 */ 179 u32 int_status; /* 0x0018 */ 180 u32 int_mask; /* 0x001C */ 181 u32 int_alias_clr_en; /* 0x0020 */ 182 u32 int_status_alias; /* 0x0024 */ 183 u32 sw_reset; /* 0x0028 */ 184 u32 slv_timer; /* 0x002C */ 185 u32 msi_config; /* 0x0030 */ 186 u32 loopback; /* 0x0034 */ 187 u32 watchdog_timer; /* 0x0038 */ 188}; 189 190 191/* START OF TXDMA REGISTER ADDRESS MAP */ 192 193/* 194 * txdma control status reg at address 0x1000 195 */ 196 197#define ET_TXDMA_CSR_HALT 0x00000001 198#define ET_TXDMA_DROP_TLP 0x00000002 199#define ET_TXDMA_CACHE_THRS 0x000000F0 200#define ET_TXDMA_CACHE_SHIFT 4 201#define ET_TXDMA_SNGL_EPKT 0x00000100 202#define ET_TXDMA_CLASS 0x00001E00 203 204/* 205 * structure for txdma packet ring base address hi reg in txdma address map 206 * located at address 0x1004 207 * Defined earlier (u32) 208 */ 209 210/* 211 * structure for txdma packet ring base address low reg in txdma address map 212 * located at address 0x1008 213 * Defined earlier (u32) 214 */ 215 216/* 217 * structure for txdma packet ring number of descriptor reg in txdma address 218 * map. Located at address 0x100C 219 * 220 * 31-10: unused 221 * 9-0: pr ndes 222 */ 223 224#define ET_DMA12_MASK 0x0FFF /* 12 bit mask for DMA12W types */ 225#define ET_DMA12_WRAP 0x1000 226#define ET_DMA10_MASK 0x03FF /* 10 bit mask for DMA10W types */ 227#define ET_DMA10_WRAP 0x0400 228#define ET_DMA4_MASK 0x000F /* 4 bit mask for DMA4W types */ 229#define ET_DMA4_WRAP 0x0010 230 231#define INDEX12(x) ((x) & ET_DMA12_MASK) 232#define INDEX10(x) ((x) & ET_DMA10_MASK) 233#define INDEX4(x) ((x) & ET_DMA4_MASK) 234 235/* 236 * 10bit DMA with wrap 237 * txdma tx queue write address reg in txdma address map at 0x1010 238 * txdma tx queue write address external reg in txdma address map at 0x1014 239 * txdma tx queue read address reg in txdma address map at 0x1018 240 * 241 * u32 242 * txdma status writeback address hi reg in txdma address map at0x101C 243 * txdma status writeback address lo reg in txdma address map at 0x1020 244 * 245 * 10bit DMA with wrap 246 * txdma service request reg in txdma address map at 0x1024 247 * structure for txdma service complete reg in txdma address map at 0x1028 248 * 249 * 4bit DMA with wrap 250 * txdma tx descriptor cache read index reg in txdma address map at 0x102C 251 * txdma tx descriptor cache write index reg in txdma address map at 0x1030 252 * 253 * txdma error reg in txdma address map at address 0x1034 254 * 0: PyldResend 255 * 1: PyldRewind 256 * 4: DescrResend 257 * 5: DescrRewind 258 * 8: WrbkResend 259 * 9: WrbkRewind 260 */ 261 262/* 263 * Tx DMA Module of JAGCore Address Mapping 264 * Located at address 0x1000 265 */ 266struct txdma_regs { /* Location: */ 267 u32 csr; /* 0x1000 */ 268 u32 pr_base_hi; /* 0x1004 */ 269 u32 pr_base_lo; /* 0x1008 */ 270 u32 pr_num_des; /* 0x100C */ 271 u32 txq_wr_addr; /* 0x1010 */ 272 u32 txq_wr_addr_ext; /* 0x1014 */ 273 u32 txq_rd_addr; /* 0x1018 */ 274 u32 dma_wb_base_hi; /* 0x101C */ 275 u32 dma_wb_base_lo; /* 0x1020 */ 276 u32 service_request; /* 0x1024 */ 277 u32 service_complete; /* 0x1028 */ 278 u32 cache_rd_index; /* 0x102C */ 279 u32 cache_wr_index; /* 0x1030 */ 280 u32 tx_dma_error; /* 0x1034 */ 281 u32 desc_abort_cnt; /* 0x1038 */ 282 u32 payload_abort_cnt; /* 0x103c */ 283 u32 writeback_abort_cnt; /* 0x1040 */ 284 u32 desc_timeout_cnt; /* 0x1044 */ 285 u32 payload_timeout_cnt; /* 0x1048 */ 286 u32 writeback_timeout_cnt; /* 0x104c */ 287 u32 desc_error_cnt; /* 0x1050 */ 288 u32 payload_error_cnt; /* 0x1054 */ 289 u32 writeback_error_cnt; /* 0x1058 */ 290 u32 dropped_tlp_cnt; /* 0x105c */ 291 u32 new_service_complete; /* 0x1060 */ 292 u32 ethernet_packet_cnt; /* 0x1064 */ 293}; 294 295/* END OF TXDMA REGISTER ADDRESS MAP */ 296 297 298/* START OF RXDMA REGISTER ADDRESS MAP */ 299 300/* 301 * structure for control status reg in rxdma address map 302 * Located at address 0x2000 303 * 304 * CSR 305 * 0: halt 306 * 1-3: tc 307 * 4: fbr_big_endian 308 * 5: psr_big_endian 309 * 6: pkt_big_endian 310 * 7: dma_big_endian 311 * 8-9: fbr0_size 312 * 10: fbr0_enable 313 * 11-12: fbr1_size 314 * 13: fbr1_enable 315 * 14: unused 316 * 15: pkt_drop_disable 317 * 16: pkt_done_flush 318 * 17: halt_status 319 * 18-31: unused 320 */ 321 322#define ET_RXDMA_CSR_HALT 0x0001 323#define ET_RXDMA_CSR_FBR0_SIZE_LO 0x0100 324#define ET_RXDMA_CSR_FBR0_SIZE_HI 0x0200 325#define ET_RXDMA_CSR_FBR0_ENABLE 0x0400 326#define ET_RXDMA_CSR_FBR1_SIZE_LO 0x0800 327#define ET_RXDMA_CSR_FBR1_SIZE_HI 0x1000 328#define ET_RXDMA_CSR_FBR1_ENABLE 0x2000 329#define ET_RXDMA_CSR_HALT_STATUS 0x00020000 330 331/* 332 * structure for dma writeback lo reg in rxdma address map 333 * located at address 0x2004 334 * Defined earlier (u32) 335 */ 336 337/* 338 * structure for dma writeback hi reg in rxdma address map 339 * located at address 0x2008 340 * Defined earlier (u32) 341 */ 342 343/* 344 * structure for number of packets done reg in rxdma address map 345 * located at address 0x200C 346 * 347 * 31-8: unused 348 * 7-0: num done 349 */ 350 351/* 352 * structure for max packet time reg in rxdma address map 353 * located at address 0x2010 354 * 355 * 31-18: unused 356 * 17-0: time done 357 */ 358 359/* 360 * structure for rx queue read address reg in rxdma address map 361 * located at address 0x2014 362 * Defined earlier (u32) 363 */ 364 365/* 366 * structure for rx queue read address external reg in rxdma address map 367 * located at address 0x2018 368 * Defined earlier (u32) 369 */ 370 371/* 372 * structure for rx queue write address reg in rxdma address map 373 * located at address 0x201C 374 * Defined earlier (u32) 375 */ 376 377/* 378 * structure for packet status ring base address lo reg in rxdma address map 379 * located at address 0x2020 380 * Defined earlier (u32) 381 */ 382 383/* 384 * structure for packet status ring base address hi reg in rxdma address map 385 * located at address 0x2024 386 * Defined earlier (u32) 387 */ 388 389/* 390 * structure for packet status ring number of descriptors reg in rxdma address 391 * map. Located at address 0x2028 392 * 393 * 31-12: unused 394 * 11-0: psr ndes 395 */ 396 397#define ET_RXDMA_PSR_NUM_DES_MASK 0xFFF 398 399/* 400 * structure for packet status ring available offset reg in rxdma address map 401 * located at address 0x202C 402 * 403 * 31-13: unused 404 * 12: psr avail wrap 405 * 11-0: psr avail 406 */ 407 408/* 409 * structure for packet status ring full offset reg in rxdma address map 410 * located at address 0x2030 411 * 412 * 31-13: unused 413 * 12: psr full wrap 414 * 11-0: psr full 415 */ 416 417/* 418 * structure for packet status ring access index reg in rxdma address map 419 * located at address 0x2034 420 * 421 * 31-5: unused 422 * 4-0: psr_ai 423 */ 424 425/* 426 * structure for packet status ring minimum descriptors reg in rxdma address 427 * map. Located at address 0x2038 428 * 429 * 31-12: unused 430 * 11-0: psr_min 431 */ 432 433/* 434 * structure for free buffer ring base lo address reg in rxdma address map 435 * located at address 0x203C 436 * Defined earlier (u32) 437 */ 438 439/* 440 * structure for free buffer ring base hi address reg in rxdma address map 441 * located at address 0x2040 442 * Defined earlier (u32) 443 */ 444 445/* 446 * structure for free buffer ring number of descriptors reg in rxdma address 447 * map. Located at address 0x2044 448 * 449 * 31-10: unused 450 * 9-0: fbr ndesc 451 */ 452 453/* 454 * structure for free buffer ring 0 available offset reg in rxdma address map 455 * located at address 0x2048 456 * Defined earlier (u32) 457 */ 458 459/* 460 * structure for free buffer ring 0 full offset reg in rxdma address map 461 * located at address 0x204C 462 * Defined earlier (u32) 463 */ 464 465/* 466 * structure for free buffer cache 0 full offset reg in rxdma address map 467 * located at address 0x2050 468 * 469 * 31-5: unused 470 * 4-0: fbc rdi 471 */ 472 473/* 474 * structure for free buffer ring 0 minimum descriptor reg in rxdma address map 475 * located at address 0x2054 476 * 477 * 31-10: unused 478 * 9-0: fbr min 479 */ 480 481/* 482 * structure for free buffer ring 1 base address lo reg in rxdma address map 483 * located at address 0x2058 - 0x205C 484 * Defined earlier (RXDMA_FBR_BASE_LO_t and RXDMA_FBR_BASE_HI_t) 485 */ 486 487/* 488 * structure for free buffer ring 1 number of descriptors reg in rxdma address 489 * map. Located at address 0x2060 490 * Defined earlier (RXDMA_FBR_NUM_DES_t) 491 */ 492 493/* 494 * structure for free buffer ring 1 available offset reg in rxdma address map 495 * located at address 0x2064 496 * Defined Earlier (RXDMA_FBR_AVAIL_OFFSET_t) 497 */ 498 499/* 500 * structure for free buffer ring 1 full offset reg in rxdma address map 501 * located at address 0x2068 502 * Defined Earlier (RXDMA_FBR_FULL_OFFSET_t) 503 */ 504 505/* 506 * structure for free buffer cache 1 read index reg in rxdma address map 507 * located at address 0x206C 508 * Defined Earlier (RXDMA_FBC_RD_INDEX_t) 509 */ 510 511/* 512 * structure for free buffer ring 1 minimum descriptor reg in rxdma address map 513 * located at address 0x2070 514 * Defined Earlier (RXDMA_FBR_MIN_DES_t) 515 */ 516 517/* 518 * Rx DMA Module of JAGCore Address Mapping 519 * Located at address 0x2000 520 */ 521struct rxdma_regs { /* Location: */ 522 u32 csr; /* 0x2000 */ 523 u32 dma_wb_base_lo; /* 0x2004 */ 524 u32 dma_wb_base_hi; /* 0x2008 */ 525 u32 num_pkt_done; /* 0x200C */ 526 u32 max_pkt_time; /* 0x2010 */ 527 u32 rxq_rd_addr; /* 0x2014 */ 528 u32 rxq_rd_addr_ext; /* 0x2018 */ 529 u32 rxq_wr_addr; /* 0x201C */ 530 u32 psr_base_lo; /* 0x2020 */ 531 u32 psr_base_hi; /* 0x2024 */ 532 u32 psr_num_des; /* 0x2028 */ 533 u32 psr_avail_offset; /* 0x202C */ 534 u32 psr_full_offset; /* 0x2030 */ 535 u32 psr_access_index; /* 0x2034 */ 536 u32 psr_min_des; /* 0x2038 */ 537 u32 fbr0_base_lo; /* 0x203C */ 538 u32 fbr0_base_hi; /* 0x2040 */ 539 u32 fbr0_num_des; /* 0x2044 */ 540 u32 fbr0_avail_offset; /* 0x2048 */ 541 u32 fbr0_full_offset; /* 0x204C */ 542 u32 fbr0_rd_index; /* 0x2050 */ 543 u32 fbr0_min_des; /* 0x2054 */ 544 u32 fbr1_base_lo; /* 0x2058 */ 545 u32 fbr1_base_hi; /* 0x205C */ 546 u32 fbr1_num_des; /* 0x2060 */ 547 u32 fbr1_avail_offset; /* 0x2064 */ 548 u32 fbr1_full_offset; /* 0x2068 */ 549 u32 fbr1_rd_index; /* 0x206C */ 550 u32 fbr1_min_des; /* 0x2070 */ 551}; 552 553/* END OF RXDMA REGISTER ADDRESS MAP */ 554 555 556/* START OF TXMAC REGISTER ADDRESS MAP */ 557 558/* 559 * structure for control reg in txmac address map 560 * located at address 0x3000 561 * 562 * bits 563 * 31-8: unused 564 * 7: cklseg_disable 565 * 6: ckbcnt_disable 566 * 5: cksegnum 567 * 4: async_disable 568 * 3: fc_disable 569 * 2: mcif_disable 570 * 1: mif_disable 571 * 0: txmac_en 572 */ 573 574#define ET_TX_CTRL_FC_DISABLE 0x0008 575#define ET_TX_CTRL_TXMAC_ENABLE 0x0001 576 577/* 578 * structure for shadow pointer reg in txmac address map 579 * located at address 0x3004 580 * 31-27: reserved 581 * 26-16: txq rd ptr 582 * 15-11: reserved 583 * 10-0: txq wr ptr 584 */ 585 586/* 587 * structure for error count reg in txmac address map 588 * located at address 0x3008 589 * 590 * 31-12: unused 591 * 11-8: reserved 592 * 7-4: txq_underrun 593 * 3-0: fifo_underrun 594 */ 595 596/* 597 * structure for max fill reg in txmac address map 598 * located at address 0x300C 599 * 31-12: unused 600 * 11-0: max fill 601 */ 602 603/* 604 * structure for cf parameter reg in txmac address map 605 * located at address 0x3010 606 * 31-16: cfep 607 * 15-0: cfpt 608 */ 609 610/* 611 * structure for tx test reg in txmac address map 612 * located at address 0x3014 613 * 31-17: unused 614 * 16: reserved 615 * 15: txtest_en 616 * 14-11: unused 617 * 10-0: txq test pointer 618 */ 619 620/* 621 * structure for error reg in txmac address map 622 * located at address 0x3018 623 * 624 * 31-9: unused 625 * 8: fifo_underrun 626 * 7-6: unused 627 * 5: ctrl2_err 628 * 4: txq_underrun 629 * 3: bcnt_err 630 * 2: lseg_err 631 * 1: segnum_err 632 * 0: seg0_err 633 */ 634 635/* 636 * structure for error interrupt reg in txmac address map 637 * located at address 0x301C 638 * 639 * 31-9: unused 640 * 8: fifo_underrun 641 * 7-6: unused 642 * 5: ctrl2_err 643 * 4: txq_underrun 644 * 3: bcnt_err 645 * 2: lseg_err 646 * 1: segnum_err 647 * 0: seg0_err 648 */ 649 650/* 651 * structure for error interrupt reg in txmac address map 652 * located at address 0x3020 653 * 654 * 31-2: unused 655 * 1: bp_req 656 * 0: bp_xonxoff 657 */ 658 659/* 660 * Tx MAC Module of JAGCore Address Mapping 661 */ 662struct txmac_regs { /* Location: */ 663 u32 ctl; /* 0x3000 */ 664 u32 shadow_ptr; /* 0x3004 */ 665 u32 err_cnt; /* 0x3008 */ 666 u32 max_fill; /* 0x300C */ 667 u32 cf_param; /* 0x3010 */ 668 u32 tx_test; /* 0x3014 */ 669 u32 err; /* 0x3018 */ 670 u32 err_int; /* 0x301C */ 671 u32 bp_ctrl; /* 0x3020 */ 672}; 673 674/* END OF TXMAC REGISTER ADDRESS MAP */ 675 676/* START OF RXMAC REGISTER ADDRESS MAP */ 677 678/* 679 * structure for rxmac control reg in rxmac address map 680 * located at address 0x4000 681 * 682 * 31-7: reserved 683 * 6: rxmac_int_disable 684 * 5: async_disable 685 * 4: mif_disable 686 * 3: wol_disable 687 * 2: pkt_filter_disable 688 * 1: mcif_disable 689 * 0: rxmac_en 690 */ 691 692#define ET_RX_CTRL_WOL_DISABLE 0x0008 693#define ET_RX_CTRL_RXMAC_ENABLE 0x0001 694 695/* 696 * structure for Wake On Lan Control and CRC 0 reg in rxmac address map 697 * located at address 0x4004 698 * 31-16: crc 699 * 15-12: reserved 700 * 11: ignore_pp 701 * 10: ignore_mp 702 * 9: clr_intr 703 * 8: ignore_link_chg 704 * 7: ignore_uni 705 * 6: ignore_multi 706 * 5: ignore_broad 707 * 4-0: valid_crc 4-0 708 */ 709 710/* 711 * structure for CRC 1 and CRC 2 reg in rxmac address map 712 * located at address 0x4008 713 * 714 * 31-16: crc2 715 * 15-0: crc1 716 */ 717 718/* 719 * structure for CRC 3 and CRC 4 reg in rxmac address map 720 * located at address 0x400C 721 * 722 * 31-16: crc4 723 * 15-0: crc3 724 */ 725 726/* 727 * structure for Wake On Lan Source Address Lo reg in rxmac address map 728 * located at address 0x4010 729 * 730 * 31-24: sa3 731 * 23-16: sa4 732 * 15-8: sa5 733 * 7-0: sa6 734 */ 735 736#define ET_RX_WOL_LO_SA3_SHIFT 24 737#define ET_RX_WOL_LO_SA4_SHIFT 16 738#define ET_RX_WOL_LO_SA5_SHIFT 8 739 740/* 741 * structure for Wake On Lan Source Address Hi reg in rxmac address map 742 * located at address 0x4014 743 * 744 * 31-16: reserved 745 * 15-8: sa1 746 * 7-0: sa2 747 */ 748 749#define ET_RX_WOL_HI_SA1_SHIFT 8 750 751/* 752 * structure for Wake On Lan mask reg in rxmac address map 753 * located at address 0x4018 - 0x4064 754 * Defined earlier (u32) 755 */ 756 757/* 758 * structure for Unicast Packet Filter Address 1 reg in rxmac address map 759 * located at address 0x4068 760 * 761 * 31-24: addr1_3 762 * 23-16: addr1_4 763 * 15-8: addr1_5 764 * 7-0: addr1_6 765 */ 766 767#define ET_RX_UNI_PF_ADDR1_3_SHIFT 24 768#define ET_RX_UNI_PF_ADDR1_4_SHIFT 16 769#define ET_RX_UNI_PF_ADDR1_5_SHIFT 8 770 771/* 772 * structure for Unicast Packet Filter Address 2 reg in rxmac address map 773 * located at address 0x406C 774 * 775 * 31-24: addr2_3 776 * 23-16: addr2_4 777 * 15-8: addr2_5 778 * 7-0: addr2_6 779 */ 780 781#define ET_RX_UNI_PF_ADDR2_3_SHIFT 24 782#define ET_RX_UNI_PF_ADDR2_4_SHIFT 16 783#define ET_RX_UNI_PF_ADDR2_5_SHIFT 8 784 785/* 786 * structure for Unicast Packet Filter Address 1 & 2 reg in rxmac address map 787 * located at address 0x4070 788 * 789 * 31-24: addr2_1 790 * 23-16: addr2_2 791 * 15-8: addr1_1 792 * 7-0: addr1_2 793 */ 794 795#define ET_RX_UNI_PF_ADDR2_1_SHIFT 24 796#define ET_RX_UNI_PF_ADDR2_2_SHIFT 16 797#define ET_RX_UNI_PF_ADDR1_1_SHIFT 8 798 799/* 800 * structure for Multicast Hash reg in rxmac address map 801 * located at address 0x4074 - 0x4080 802 * Defined earlier (u32) 803 */ 804 805/* 806 * structure for Packet Filter Control reg in rxmac address map 807 * located at address 0x4084 808 * 809 * 31-23: unused 810 * 22-16: min_pkt_size 811 * 15-4: unused 812 * 3: filter_frag_en 813 * 2: filter_uni_en 814 * 1: filter_multi_en 815 * 0: filter_broad_en 816 */ 817 818#define ET_RX_PFCTRL_MIN_PKT_SZ_SHIFT 16 819#define ET_RX_PFCTRL_FRAG_FILTER_ENABLE 0x0008 820#define ET_RX_PFCTRL_UNICST_FILTER_ENABLE 0x0004 821#define ET_RX_PFCTRL_MLTCST_FILTER_ENABLE 0x0002 822#define ET_RX_PFCTRL_BRDCST_FILTER_ENABLE 0x0001 823 824/* 825 * structure for Memory Controller Interface Control Max Segment reg in rxmac 826 * address map. Located at address 0x4088 827 * 828 * 31-10: reserved 829 * 9-2: max_size 830 * 1: fc_en 831 * 0: seg_en 832 */ 833 834#define ET_RX_MCIF_CTRL_MAX_SEG_SIZE_SHIFT 2 835#define ET_RX_MCIF_CTRL_MAX_SEG_FC_ENABLE 0x0002 836#define ET_RX_MCIF_CTRL_MAX_SEG_ENABLE 0x0001 837 838/* 839 * structure for Memory Controller Interface Water Mark reg in rxmac address 840 * map. Located at address 0x408C 841 * 842 * 31-26: unused 843 * 25-16: mark_hi 844 * 15-10: unused 845 * 9-0: mark_lo 846 */ 847 848/* 849 * structure for Rx Queue Dialog reg in rxmac address map. 850 * located at address 0x4090 851 * 852 * 31-26: reserved 853 * 25-16: rd_ptr 854 * 15-10: reserved 855 * 9-0: wr_ptr 856 */ 857 858/* 859 * structure for space available reg in rxmac address map. 860 * located at address 0x4094 861 * 862 * 31-17: reserved 863 * 16: space_avail_en 864 * 15-10: reserved 865 * 9-0: space_avail 866 */ 867 868/* 869 * structure for management interface reg in rxmac address map. 870 * located at address 0x4098 871 * 872 * 31-18: reserved 873 * 17: drop_pkt_en 874 * 16-0: drop_pkt_mask 875 */ 876 877/* 878 * structure for Error reg in rxmac address map. 879 * located at address 0x409C 880 * 881 * 31-4: unused 882 * 3: mif 883 * 2: async 884 * 1: pkt_filter 885 * 0: mcif 886 */ 887 888/* 889 * Rx MAC Module of JAGCore Address Mapping 890 */ 891struct rxmac_regs { /* Location: */ 892 u32 ctrl; /* 0x4000 */ 893 u32 crc0; /* 0x4004 */ 894 u32 crc12; /* 0x4008 */ 895 u32 crc34; /* 0x400C */ 896 u32 sa_lo; /* 0x4010 */ 897 u32 sa_hi; /* 0x4014 */ 898 u32 mask0_word0; /* 0x4018 */ 899 u32 mask0_word1; /* 0x401C */ 900 u32 mask0_word2; /* 0x4020 */ 901 u32 mask0_word3; /* 0x4024 */ 902 u32 mask1_word0; /* 0x4028 */ 903 u32 mask1_word1; /* 0x402C */ 904 u32 mask1_word2; /* 0x4030 */ 905 u32 mask1_word3; /* 0x4034 */ 906 u32 mask2_word0; /* 0x4038 */ 907 u32 mask2_word1; /* 0x403C */ 908 u32 mask2_word2; /* 0x4040 */ 909 u32 mask2_word3; /* 0x4044 */ 910 u32 mask3_word0; /* 0x4048 */ 911 u32 mask3_word1; /* 0x404C */ 912 u32 mask3_word2; /* 0x4050 */ 913 u32 mask3_word3; /* 0x4054 */ 914 u32 mask4_word0; /* 0x4058 */ 915 u32 mask4_word1; /* 0x405C */ 916 u32 mask4_word2; /* 0x4060 */ 917 u32 mask4_word3; /* 0x4064 */ 918 u32 uni_pf_addr1; /* 0x4068 */ 919 u32 uni_pf_addr2; /* 0x406C */ 920 u32 uni_pf_addr3; /* 0x4070 */ 921 u32 multi_hash1; /* 0x4074 */ 922 u32 multi_hash2; /* 0x4078 */ 923 u32 multi_hash3; /* 0x407C */ 924 u32 multi_hash4; /* 0x4080 */ 925 u32 pf_ctrl; /* 0x4084 */ 926 u32 mcif_ctrl_max_seg; /* 0x4088 */ 927 u32 mcif_water_mark; /* 0x408C */ 928 u32 rxq_diag; /* 0x4090 */ 929 u32 space_avail; /* 0x4094 */ 930 931 u32 mif_ctrl; /* 0x4098 */ 932 u32 err_reg; /* 0x409C */ 933}; 934 935/* END OF RXMAC REGISTER ADDRESS MAP */ 936 937/* START OF MAC REGISTER ADDRESS MAP */ 938 939/* 940 * structure for configuration #1 reg in mac address map. 941 * located at address 0x5000 942 * 943 * 31: soft reset 944 * 30: sim reset 945 * 29-20: reserved 946 * 19: reset rx mc 947 * 18: reset tx mc 948 * 17: reset rx func 949 * 16: reset tx fnc 950 * 15-9: reserved 951 * 8: loopback 952 * 7-6: reserved 953 * 5: rx flow 954 * 4: tx flow 955 * 3: syncd rx en 956 * 2: rx enable 957 * 1: syncd tx en 958 * 0: tx enable 959 */ 960 961#define ET_MAC_CFG1_SOFT_RESET 0x80000000 962#define ET_MAC_CFG1_SIM_RESET 0x40000000 963#define ET_MAC_CFG1_RESET_RXMC 0x00080000 964#define ET_MAC_CFG1_RESET_TXMC 0x00040000 965#define ET_MAC_CFG1_RESET_RXFUNC 0x00020000 966#define ET_MAC_CFG1_RESET_TXFUNC 0x00010000 967#define ET_MAC_CFG1_LOOPBACK 0x00000100 968#define ET_MAC_CFG1_RX_FLOW 0x00000020 969#define ET_MAC_CFG1_TX_FLOW 0x00000010 970#define ET_MAC_CFG1_RX_ENABLE 0x00000004 971#define ET_MAC_CFG1_TX_ENABLE 0x00000001 972#define ET_MAC_CFG1_WAIT 0x0000000A /* RX & TX syncd */ 973 974/* 975 * structure for configuration #2 reg in mac address map. 976 * located at address 0x5004 977 * 31-16: reserved 978 * 15-12: preamble 979 * 11-10: reserved 980 * 9-8: if mode 981 * 7-6: reserved 982 * 5: huge frame 983 * 4: length check 984 * 3: undefined 985 * 2: pad crc 986 * 1: crc enable 987 * 0: full duplex 988 */ 989 990#define ET_MAC_CFG2_PREAMBLE_SHIFT 12 991#define ET_MAC_CFG2_IFMODE_MASK 0x0300 992#define ET_MAC_CFG2_IFMODE_1000 0x0200 993#define ET_MAC_CFG2_IFMODE_100 0x0100 994#define ET_MAC_CFG2_IFMODE_HUGE_FRAME 0x0020 995#define ET_MAC_CFG2_IFMODE_LEN_CHECK 0x0010 996#define ET_MAC_CFG2_IFMODE_PAD_CRC 0x0004 997#define ET_MAC_CFG2_IFMODE_CRC_ENABLE 0x0002 998#define ET_MAC_CFG2_IFMODE_FULL_DPLX 0x0001 999 1000/*
1001 * structure for Interpacket gap reg in mac address map. 1002 * located at address 0x5008 1003 * 1004 * 31: reserved 1005 * 30-24: non B2B ipg 1 1006 * 23: undefined 1007 * 22-16: non B2B ipg 2 1008 * 15-8: Min ifg enforce 1009 * 7-0: B2B ipg 1010 * 1011 * structure for half duplex reg in mac address map. 1012 * located at address 0x500C 1013 * 31-24: reserved 1014 * 23-20: Alt BEB trunc 1015 * 19: Alt BEB enable 1016 * 18: BP no backoff 1017 * 17: no backoff 1018 * 16: excess defer 1019 * 15-12: re-xmit max 1020 * 11-10: reserved 1021 * 9-0: collision window 1022 */ 1023 1024/* 1025 * structure for Maximum Frame Length reg in mac address map. 1026 * located at address 0x5010: bits 0-15 hold the length. 1027 */ 1028 1029/* 1030 * structure for Reserve 1 reg in mac address map. 1031 * located at address 0x5014 - 0x5018 1032 * Defined earlier (u32) 1033 */ 1034 1035/* 1036 * structure for Test reg in mac address map. 1037 * located at address 0x501C 1038 * test: bits 0-2, rest unused 1039 */ 1040 1041/* 1042 * structure for MII Management Configuration reg in mac address map. 1043 * located at address 0x5020 1044 * 1045 * 31: reset MII mgmt 1046 * 30-6: unused 1047 * 5: scan auto increment 1048 * 4: preamble suppress 1049 * 3: undefined 1050 * 2-0: mgmt clock reset 1051 */ 1052 1053#define ET_MAC_MIIMGMT_CLK_RST 0x0007 1054 1055/* 1056 * structure for MII Management Command reg in mac address map. 1057 * located at address 0x5024 1058 * bit 1: scan cycle 1059 * bit 0: read cycle 1060 */ 1061 1062/* 1063 * structure for MII Management Address reg in mac address map. 1064 * located at address 0x5028 1065 * 31-13: reserved 1066 * 12-8: phy addr 1067 * 7-5: reserved 1068 * 4-0: register 1069 */ 1070 1071#define ET_MAC_MII_ADDR(phy, reg) ((phy) << 8 | (reg)) 1072 1073/* 1074 * structure for MII Management Control reg in mac address map. 1075 * located at address 0x502C 1076 * 31-16: reserved 1077 * 15-0: phy control 1078 */ 1079 1080/* 1081 * structure for MII Management Status reg in mac address map. 1082 * located at address 0x5030 1083 * 31-16: reserved 1084 * 15-0: phy control 1085 */ 1086 1087#define ET_MAC_MIIMGMT_STAT_PHYCRTL_MASK 0xFFFF 1088 1089/* 1090 * structure for MII Management Indicators reg in mac address map. 1091 * located at address 0x5034 1092 * 31-3: reserved 1093 * 2: not valid 1094 * 1: scanning 1095 * 0: busy 1096 */ 1097 1098#define ET_MAC_MGMT_BUSY 0x00000001 /* busy */ 1099#define ET_MAC_MGMT_WAIT 0x00000005 /* busy | not valid */ 1100 1101/* 1102 * structure for Interface Control reg in mac address map. 1103 * located at address 0x5038 1104 * 1105 * 31: reset if module 1106 * 30-28: reserved 1107 * 27: tbi mode 1108 * 26: ghd mode 1109 * 25: lhd mode 1110 * 24: phy mode 1111 * 23: reset per mii 1112 * 22-17: reserved 1113 * 16: speed 1114 * 15: reset pe100x 1115 * 14-11: reserved 1116 * 10: force quiet 1117 * 9: no cipher 1118 * 8: disable link fail 1119 * 7: reset gpsi 1120 * 6-1: reserved 1121 * 0: enable jabber protection 1122 */ 1123 1124#define ET_MAC_IFCTRL_GHDMODE (1 << 26) 1125#define ET_MAC_IFCTRL_PHYMODE (1 << 24) 1126 1127/* 1128 * structure for Interface Status reg in mac address map. 1129 * located at address 0x503C 1130 * 1131 * 31-10: reserved 1132 * 9: excess_defer 1133 * 8: clash 1134 * 7: phy_jabber 1135 * 6: phy_link_ok 1136 * 5: phy_full_duplex 1137 * 4: phy_speed 1138 * 3: pe100x_link_fail 1139 * 2: pe10t_loss_carrier 1140 * 1: pe10t_sqe_error 1141 * 0: pe10t_jabber 1142 */ 1143 1144/* 1145 * structure for Mac Station Address, Part 1 reg in mac address map. 1146 * located at address 0x5040 1147 * 1148 * 31-24: Octet6 1149 * 23-16: Octet5 1150 * 15-8: Octet4 1151 * 7-0: Octet3 1152 */ 1153 1154#define ET_MAC_STATION_ADDR1_OC6_SHIFT 24 1155#define ET_MAC_STATION_ADDR1_OC5_SHIFT 16 1156#define ET_MAC_STATION_ADDR1_OC4_SHIFT 8 1157 1158/* 1159 * structure for Mac Station Address, Part 2 reg in mac address map. 1160 * located at address 0x5044 1161 * 1162 * 31-24: Octet2 1163 * 23-16: Octet1 1164 * 15-0: reserved 1165 */ 1166 1167#define ET_MAC_STATION_ADDR2_OC2_SHIFT 24 1168#define ET_MAC_STATION_ADDR2_OC1_SHIFT 16 1169 1170/* 1171 * MAC Module of JAGCore Address Mapping 1172 */ 1173struct mac_regs { /* Location: */ 1174 u32 cfg1; /* 0x5000 */ 1175 u32 cfg2; /* 0x5004 */ 1176 u32 ipg; /* 0x5008 */ 1177 u32 hfdp; /* 0x500C */ 1178 u32 max_fm_len; /* 0x5010 */ 1179 u32 rsv1; /* 0x5014 */ 1180 u32 rsv2; /* 0x5018 */ 1181 u32 mac_test; /* 0x501C */ 1182 u32 mii_mgmt_cfg; /* 0x5020 */ 1183 u32 mii_mgmt_cmd; /* 0x5024 */ 1184 u32 mii_mgmt_addr; /* 0x5028 */ 1185 u32 mii_mgmt_ctrl; /* 0x502C */ 1186 u32 mii_mgmt_stat; /* 0x5030 */ 1187 u32 mii_mgmt_indicator; /* 0x5034 */ 1188 u32 if_ctrl; /* 0x5038 */ 1189 u32 if_stat; /* 0x503C */ 1190 u32 station_addr_1; /* 0x5040 */ 1191 u32 station_addr_2; /* 0x5044 */ 1192}; 1193 1194/* END OF MAC REGISTER ADDRESS MAP */ 1195 1196/* START OF MAC STAT REGISTER ADDRESS MAP */ 1197 1198/* 1199 * structure for Carry Register One and it's Mask Register reg located in mac 1200 * stat address map address 0x6130 and 0x6138. 1201 * 1202 * 31: tr64 1203 * 30: tr127 1204 * 29: tr255 1205 * 28: tr511 1206 * 27: tr1k 1207 * 26: trmax 1208 * 25: trmgv 1209 * 24-17: unused 1210 * 16: rbyt 1211 * 15: rpkt 1212 * 14: rfcs 1213 * 13: rmca 1214 * 12: rbca 1215 * 11: rxcf 1216 * 10: rxpf 1217 * 9: rxuo 1218 * 8: raln 1219 * 7: rflr 1220 * 6: rcde 1221 * 5: rcse 1222 * 4: rund 1223 * 3: rovr 1224 * 2: rfrg 1225 * 1: rjbr 1226 * 0: rdrp 1227 */ 1228 1229/* 1230 * structure for Carry Register Two Mask Register reg in mac stat address map. 1231 * located at address 0x613C 1232 * 1233 * 31-20: unused 1234 * 19: tjbr 1235 * 18: tfcs 1236 * 17: txcf 1237 * 16: tovr 1238 * 15: tund 1239 * 14: trfg 1240 * 13: tbyt 1241 * 12: tpkt 1242 * 11: tmca 1243 * 10: tbca 1244 * 9: txpf 1245 * 8: tdfr 1246 * 7: tedf 1247 * 6: tscl 1248 * 5: tmcl 1249 * 4: tlcl 1250 * 3: txcl 1251 * 2: tncl 1252 * 1: tpfh 1253 * 0: tdrp 1254 */ 1255 1256/* 1257 * MAC STATS Module of JAGCore Address Mapping 1258 */ 1259struct macstat_regs { /* Location: */ 1260 u32 pad[32]; /* 0x6000 - 607C */ 1261 1262 /* Tx/Rx 0-64 Byte Frame Counter */ 1263 u32 txrx_0_64_byte_frames; /* 0x6080 */ 1264 1265 /* Tx/Rx 65-127 Byte Frame Counter */ 1266 u32 txrx_65_127_byte_frames; /* 0x6084 */ 1267 1268 /* Tx/Rx 128-255 Byte Frame Counter */ 1269 u32 txrx_128_255_byte_frames; /* 0x6088 */ 1270 1271 /* Tx/Rx 256-511 Byte Frame Counter */ 1272 u32 txrx_256_511_byte_frames; /* 0x608C */ 1273 1274 /* Tx/Rx 512-1023 Byte Frame Counter */ 1275 u32 txrx_512_1023_byte_frames; /* 0x6090 */ 1276 1277 /* Tx/Rx 1024-1518 Byte Frame Counter */ 1278 u32 txrx_1024_1518_byte_frames; /* 0x6094 */ 1279 1280 /* Tx/Rx 1519-1522 Byte Good VLAN Frame Count */ 1281 u32 txrx_1519_1522_gvln_frames; /* 0x6098 */ 1282 1283 /* Rx Byte Counter */ 1284 u32 rx_bytes; /* 0x609C */ 1285 1286 /* Rx Packet Counter */ 1287 u32 rx_packets; /* 0x60A0 */ 1288 1289 /* Rx FCS Error Counter */ 1290 u32 rx_fcs_errs; /* 0x60A4 */ 1291 1292 /* Rx Multicast Packet Counter */ 1293 u32 rx_multicast_packets; /* 0x60A8 */ 1294 1295 /* Rx Broadcast Packet Counter */ 1296 u32 rx_broadcast_packets; /* 0x60AC */ 1297 1298 /* Rx Control Frame Packet Counter */ 1299 u32 rx_control_frames; /* 0x60B0 */ 1300 1301 /* Rx Pause Frame Packet Counter */ 1302 u32 rx_pause_frames; /* 0x60B4 */ 1303 1304 /* Rx Unknown OP Code Counter */ 1305 u32 rx_unknown_opcodes; /* 0x60B8 */ 1306 1307 /* Rx Alignment Error Counter */ 1308 u32 rx_align_errs; /* 0x60BC */ 1309 1310 /* Rx Frame Length Error Counter */ 1311 u32 rx_frame_len_errs; /* 0x60C0 */ 1312 1313 /* Rx Code Error Counter */ 1314 u32 rx_code_errs; /* 0x60C4 */ 1315 1316 /* Rx Carrier Sense Error Counter */ 1317 u32 rx_carrier_sense_errs; /* 0x60C8 */ 1318 1319 /* Rx Undersize Packet Counter */ 1320 u32 rx_undersize_packets; /* 0x60CC */ 1321 1322 /* Rx Oversize Packet Counter */ 1323 u32 rx_oversize_packets; /* 0x60D0 */ 1324 1325 /* Rx Fragment Counter */ 1326 u32 rx_fragment_packets; /* 0x60D4 */ 1327 1328 /* Rx Jabber Counter */ 1329 u32 rx_jabbers; /* 0x60D8 */ 1330 1331 /* Rx Drop */ 1332 u32 rx_drops; /* 0x60DC */ 1333 1334 /* Tx Byte Counter */ 1335 u32 tx_bytes; /* 0x60E0 */ 1336 1337 /* Tx Packet Counter */ 1338 u32 tx_packets; /* 0x60E4 */ 1339 1340 /* Tx Multicast Packet Counter */ 1341 u32 tx_multicast_packets; /* 0x60E8 */ 1342 1343 /* Tx Broadcast Packet Counter */ 1344 u32 tx_broadcast_packets; /* 0x60EC */ 1345 1346 /* Tx Pause Control Frame Counter */ 1347 u32 tx_pause_frames; /* 0x60F0 */ 1348 1349 /* Tx Deferral Packet Counter */ 1350 u32 tx_deferred; /* 0x60F4 */ 1351 1352 /* Tx Excessive Deferral Packet Counter */ 1353 u32 tx_excessive_deferred; /* 0x60F8 */ 1354 1355 /* Tx Single Collision Packet Counter */ 1356 u32 tx_single_collisions; /* 0x60FC */ 1357 1358 /* Tx Multiple Collision Packet Counter */ 1359 u32 tx_multiple_collisions; /* 0x6100 */ 1360 1361 /* Tx Late Collision Packet Counter */ 1362 u32 tx_late_collisions; /* 0x6104 */ 1363 1364 /* Tx Excessive Collision Packet Counter */ 1365 u32 tx_excessive_collisions; /* 0x6108 */ 1366 1367 /* Tx Total Collision Packet Counter */ 1368 u32 tx_total_collisions; /* 0x610C */ 1369 1370 /* Tx Pause Frame Honored Counter */ 1371 u32 tx_pause_honored_frames; /* 0x6110 */ 1372 1373 /* Tx Drop Frame Counter */ 1374 u32 tx_drops; /* 0x6114 */ 1375 1376 /* Tx Jabber Frame Counter */ 1377 u32 tx_jabbers; /* 0x6118 */ 1378 1379 /* Tx FCS Error Counter */ 1380 u32 tx_fcs_errs; /* 0x611C */ 1381 1382 /* Tx Control Frame Counter */ 1383 u32 tx_control_frames; /* 0x6120 */ 1384 1385 /* Tx Oversize Frame Counter */ 1386 u32 tx_oversize_frames; /* 0x6124 */ 1387 1388 /* Tx Undersize Frame Counter */ 1389 u32 tx_undersize_frames; /* 0x6128 */ 1390 1391 /* Tx Fragments Frame Counter */ 1392 u32 tx_fragments; /* 0x612C */ 1393 1394 /* Carry Register One Register */ 1395 u32 carry_reg1; /* 0x6130 */ 1396 1397 /* Carry Register Two Register */ 1398 u32 carry_reg2; /* 0x6134 */ 1399 1400 /* Carry Register One Mask Register */ 1401 u32 carry_reg1_mask; /* 0x6138 */ 1402 1403 /* Carry Register Two Mask Register */ 1404 u32 carry_reg2_mask; /* 0x613C */ 1405}; 1406 1407/* END OF MAC STAT REGISTER ADDRESS MAP */ 1408 1409/* START OF MMC REGISTER ADDRESS MAP */ 1410 1411/* 1412 * Main Memory Controller Control reg in mmc address map. 1413 * located at address 0x7000 1414 */ 1415 1416#define ET_MMC_ENABLE 1 1417#define ET_MMC_ARB_DISABLE 2 1418#define ET_MMC_RXMAC_DISABLE 4 1419#define ET_MMC_TXMAC_DISABLE 8 1420#define ET_MMC_TXDMA_DISABLE 16 1421#define ET_MMC_RXDMA_DISABLE 32 1422#define ET_MMC_FORCE_CE 64 1423 1424/* 1425 * Main Memory Controller Host Memory Access Address reg in mmc 1426 * address map. Located at address 0x7004. Top 16 bits hold the address bits 1427 */ 1428 1429#define ET_SRAM_REQ_ACCESS 1 1430#define ET_SRAM_WR_ACCESS 2 1431#define ET_SRAM_IS_CTRL 4 1432 1433/* 1434 * structure for Main Memory Controller Host Memory Access Data reg in mmc 1435 * address map. Located at address 0x7008 - 0x7014 1436 * Defined earlier (u32) 1437 */ 1438 1439/* 1440 * Memory Control Module of JAGCore Address Mapping 1441 */ 1442struct mmc_regs { /* Location: */ 1443 u32 mmc_ctrl; /* 0x7000 */ 1444 u32 sram_access; /* 0x7004 */ 1445 u32 sram_word1; /* 0x7008 */ 1446 u32 sram_word2; /* 0x700C */ 1447 u32 sram_word3; /* 0x7010 */ 1448 u32 sram_word4; /* 0x7014 */ 1449}; 1450 1451/* END OF MMC REGISTER ADDRESS MAP */ 1452 1453 1454/* 1455 * JAGCore Address Mapping 1456 */ 1457struct address_map { 1458 struct global_regs global; 1459 /* unused section of global address map */ 1460 u8 unused_global[4096 - sizeof(struct global_regs)]; 1461 struct txdma_regs txdma; 1462 /* unused section of txdma address map */ 1463 u8 unused_txdma[4096 - sizeof(struct txdma_regs)]; 1464 struct rxdma_regs rxdma; 1465 /* unused section of rxdma address map */ 1466 u8 unused_rxdma[4096 - sizeof(struct rxdma_regs)]; 1467 struct txmac_regs txmac; 1468 /* unused section of txmac address map */ 1469 u8 unused_txmac[4096 - sizeof(struct txmac_regs)]; 1470 struct rxmac_regs rxmac; 1471 /* unused section of rxmac address map */ 1472 u8 unused_rxmac[4096 - sizeof(struct rxmac_regs)]; 1473 struct mac_regs mac; 1474 /* unused section of mac address map */ 1475 u8 unused_mac[4096 - sizeof(struct mac_regs)]; 1476 struct macstat_regs macstat; 1477 /* unused section of mac stat address map */ 1478 u8 unused_mac_stat[4096 - sizeof(struct macstat_regs)]; 1479 struct mmc_regs mmc; 1480 /* unused section of mmc address map */ 1481 u8 unused_mmc[4096 - sizeof(struct mmc_regs)]; 1482 /* unused section of address map */ 1483 u8 unused_[1015808]; 1484 1485 u8 unused_exp_rom[4096]; /* MGS-size TBD */ 1486 u8 unused__[524288]; /* unused section of address map */ 1487}; 1488 1489/* 1490 * Defines for generic MII registers 0x00 -> 0x0F can be found in 1491 * include/linux/mii.h 1492 */ 1493 1494/* some defines for modem registers that seem to be 'reserved' */ 1495#define PHY_INDEX_REG 0x10 1496#define PHY_DATA_REG 0x11 1497#define PHY_MPHY_CONTROL_REG 0x12 1498 1499/* defines for specified registers */ 1500#define PHY_LOOPBACK_CONTROL 0x13 /* TRU_VMI_LOOPBACK_CONTROL_1_REG 19 */ 1501 /* TRU_VMI_LOOPBACK_CONTROL_2_REG 20 */ 1502#define PHY_REGISTER_MGMT_CONTROL 0x15 /* TRU_VMI_MI_SEQ_CONTROL_REG 21 */ 1503#define PHY_CONFIG 0x16 /* TRU_VMI_CONFIGURATION_REG 22 */ 1504#define PHY_PHY_CONTROL 0x17 /* TRU_VMI_PHY_CONTROL_REG 23 */ 1505#define PHY_INTERRUPT_MASK 0x18 /* TRU_VMI_INTERRUPT_MASK_REG 24 */ 1506#define PHY_INTERRUPT_STATUS 0x19 /* TRU_VMI_INTERRUPT_STATUS_REG 25 */ 1507#define PHY_PHY_STATUS 0x1A /* TRU_VMI_PHY_STATUS_REG 26 */ 1508#define PHY_LED_1 0x1B /* TRU_VMI_LED_CONTROL_1_REG 27 */ 1509#define PHY_LED_2 0x1C /* TRU_VMI_LED_CONTROL_2_REG 28 */ 1510 /* TRU_VMI_LINK_CONTROL_REG 29 */ 1511 /* TRU_VMI_TIMING_CONTROL_REG */ 1512 1513/* MI Register 10: Gigabit basic mode status reg(Reg 0x0A) */ 1514#define ET_1000BT_MSTR_SLV 0x4000 1515 1516/* MI Register 16 - 18: Reserved Reg(0x10-0x12) */ 1517 1518/* MI Register 19: Loopback Control Reg(0x13) 1519 * 15: mii_en 1520 * 14: pcs_en 1521 * 13: pmd_en 1522 * 12: all_digital_en 1523 * 11: replica_en 1524 * 10: line_driver_en 1525 * 9-0: reserved 1526 */ 1527 1528/* MI Register 20: Reserved Reg(0x14) */ 1529 1530/* MI Register 21: Management Interface Control Reg(0x15) 1531 * 15-11: reserved 1532 * 10-4: mi_error_count 1533 * 3: reserved 1534 * 2: ignore_10g_fr 1535 * 1: reserved 1536 * 0: preamble_suppress_en 1537 */ 1538 1539/* MI Register 22: PHY Configuration Reg(0x16) 1540 * 15: crs_tx_en 1541 * 14: reserved 1542 * 13-12: tx_fifo_depth 1543 * 11-10: speed_downshift 1544 * 9: pbi_detect 1545 * 8: tbi_rate 1546 * 7: alternate_np 1547 * 6: group_mdio_en 1548 * 5: tx_clock_en 1549 * 4: sys_clock_en 1550 * 3: reserved 1551 * 2-0: mac_if_mode 1552 */ 1553 1554#define ET_PHY_CONFIG_TX_FIFO_DEPTH 0x3000 1555 1556#define ET_PHY_CONFIG_FIFO_DEPTH_8 0x0000 1557#define ET_PHY_CONFIG_FIFO_DEPTH_16 0x1000 1558#define ET_PHY_CONFIG_FIFO_DEPTH_32 0x2000 1559#define ET_PHY_CONFIG_FIFO_DEPTH_64 0x3000 1560 1561/* MI Register 23: PHY CONTROL Reg(0x17) 1562 * 15: reserved 1563 * 14: tdr_en 1564 * 13: reserved 1565 * 12-11: downshift_attempts 1566 * 10-6: reserved 1567 * 5: jabber_10baseT 1568 * 4: sqe_10baseT 1569 * 3: tp_loopback_10baseT 1570 * 2: preamble_gen_en 1571 * 1: reserved 1572 * 0: force_int 1573 */ 1574 1575/* MI Register 24: Interrupt Mask Reg(0x18) 1576 * 15-10: reserved 1577 * 9: mdio_sync_lost 1578 * 8: autoneg_status 1579 * 7: hi_bit_err 1580 * 6: np_rx 1581 * 5: err_counter_full 1582 * 4: fifo_over_underflow 1583 * 3: rx_status 1584 * 2: link_status 1585 * 1: automatic_speed 1586 * 0: int_en 1587 */ 1588 1589/* MI Register 25: Interrupt Status Reg(0x19) 1590 * 15-10: reserved 1591 * 9: mdio_sync_lost 1592 * 8: autoneg_status 1593 * 7: hi_bit_err 1594 * 6: np_rx 1595 * 5: err_counter_full 1596 * 4: fifo_over_underflow 1597 * 3: rx_status 1598 * 2: link_status 1599 * 1: automatic_speed 1600 * 0: int_en 1601 */ 1602 1603/* MI Register 26: PHY Status Reg(0x1A) 1604 * 15: reserved 1605 * 14-13: autoneg_fault 1606 * 12: autoneg_status 1607 * 11: mdi_x_status 1608 * 10: polarity_status 1609 * 9-8: speed_status 1610 * 7: duplex_status 1611 * 6: link_status 1612 * 5: tx_status 1613 * 4: rx_status 1614 * 3: collision_status 1615 * 2: autoneg_en 1616 * 1: pause_en 1617 * 0: asymmetric_dir 1618 */ 1619#define ET_PHY_AUTONEG_STATUS 0x1000 1620#define ET_PHY_POLARITY_STATUS 0x0400 1621#define ET_PHY_SPEED_STATUS 0x0300 1622#define ET_PHY_DUPLEX_STATUS 0x0080 1623#define ET_PHY_LSTATUS 0x0040 1624#define ET_PHY_AUTONEG_ENABLE 0x0020 1625 1626/* MI Register 27: LED Control Reg 1(0x1B) 1627 * 15-14: reserved 1628 * 13-12: led_dup_indicate 1629 * 11-10: led_10baseT 1630 * 9-8: led_collision 1631 * 7-4: reserved 1632 * 3-2: pulse_dur 1633 * 1: pulse_stretch1 1634 * 0: pulse_stretch0 1635 */ 1636 1637/* MI Register 28: LED Control Reg 2(0x1C) 1638 * 15-12: led_link 1639 * 11-8: led_tx_rx 1640 * 7-4: led_100BaseTX 1641 * 3-0: led_1000BaseT 1642 */ 1643#define ET_LED2_LED_LINK 0xF000 1644#define ET_LED2_LED_TXRX 0x0F00 1645#define ET_LED2_LED_100TX 0x00F0 1646#define ET_LED2_LED_1000T 0x000F 1647 1648/* defines for LED control reg 2 values */ 1649#define LED_VAL_1000BT 0x0 1650#define LED_VAL_100BTX 0x1 1651#define LED_VAL_10BT 0x2 1652#define LED_VAL_1000BT_100BTX 0x3 /* 1000BT on, 100BTX blink */ 1653#define LED_VAL_LINKON 0x4 1654#define LED_VAL_TX 0x5 1655#define LED_VAL_RX 0x6 1656#define LED_VAL_TXRX 0x7 /* TX or RX */ 1657#define LED_VAL_DUPLEXFULL 0x8 1658#define LED_VAL_COLLISION 0x9 1659#define LED_VAL_LINKON_ACTIVE 0xA /* Link on, activity blink */ 1660#define LED_VAL_LINKON_RECV 0xB /* Link on, receive blink */ 1661#define LED_VAL_DUPLEXFULL_COLLISION 0xC /* Duplex on, collision blink */ 1662#define LED_VAL_BLINK 0xD 1663#define LED_VAL_ON 0xE 1664#define LED_VAL_OFF 0xF 1665 1666#define LED_LINK_SHIFT 12 1667#define LED_TXRX_SHIFT 8 1668#define LED_100TX_SHIFT 4 1669 1670/* MI Register 29 - 31: Reserved Reg(0x1D - 0x1E) */ 1671