LXR linux/include/linux/nvme.h

   1/*
   2 * Definitions for the NVM Express interface
   3 * Copyright (c) 2011-2014, Intel Corporation.
   4 *
   5 * This program is free software; you can redistribute it and/or modify it
   6 * under the terms and conditions of the GNU General Public License,
   7 * version 2, as published by the Free Software Foundation.
   8 *
   9 * This program is distributed in the hope it will be useful, but WITHOUT
  10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12 * more details.
  13 */
  14
  15#ifndef _LINUX_NVME_H
  16#define _LINUX_NVME_H
  17
  18#include <uapi/linux/nvme.h>
  19#include <linux/pci.h>
  20#include <linux/miscdevice.h>
  21#include <linux/kref.h>
  22
  23struct nvme_bar {
  24        __u64                   cap;    /* Controller Capabilities */
  25        __u32                   vs;     /* Version */
  26        __u32                   intms;  /* Interrupt Mask Set */
  27        __u32                   intmc;  /* Interrupt Mask Clear */
  28        __u32                   cc;     /* Controller Configuration */
  29        __u32                   rsvd1;  /* Reserved */
  30        __u32                   csts;   /* Controller Status */
  31        __u32                   rsvd2;  /* Reserved */
  32        __u32                   aqa;    /* Admin Queue Attributes */
  33        __u64                   asq;    /* Admin SQ Base Address */
  34        __u64                   acq;    /* Admin CQ Base Address */
  35};
  36
  37#define NVME_CAP_MQES(cap)      ((cap) & 0xffff)
  38#define NVME_CAP_TIMEOUT(cap)   (((cap) >> 24) & 0xff)
  39#define NVME_CAP_STRIDE(cap)    (((cap) >> 32) & 0xf)
  40#define NVME_CAP_MPSMIN(cap)    (((cap) >> 48) & 0xf)
  41
  42enum {
  43        NVME_CC_ENABLE          = 1 << 0,
  44        NVME_CC_CSS_NVM         = 0 << 4,
  45        NVME_CC_MPS_SHIFT       = 7,
  46        NVME_CC_ARB_RR          = 0 << 11,
  47        NVME_CC_ARB_WRRU        = 1 << 11,
  48        NVME_CC_ARB_VS          = 7 << 11,
  49        NVME_CC_SHN_NONE        = 0 << 14,
  50        NVME_CC_SHN_NORMAL      = 1 << 14,
  51        NVME_CC_SHN_ABRUPT      = 2 << 14,
  52        NVME_CC_SHN_MASK        = 3 << 14,
  53        NVME_CC_IOSQES          = 6 << 16,
  54        NVME_CC_IOCQES          = 4 << 20,
  55        NVME_CSTS_RDY           = 1 << 0,
  56        NVME_CSTS_CFS           = 1 << 1,
  57        NVME_CSTS_SHST_NORMAL   = 0 << 2,
  58        NVME_CSTS_SHST_OCCUR    = 1 << 2,
  59        NVME_CSTS_SHST_CMPLT    = 2 << 2,
  60        NVME_CSTS_SHST_MASK     = 3 << 2,
  61};
  62
  63#define NVME_VS(major, minor)   (major << 16 | minor)
  64
  65extern unsigned char nvme_io_timeout;
  66#define NVME_IO_TIMEOUT (nvme_io_timeout * HZ)
  67
  68/*
  69 * Represents an NVM Express device.  Each nvme_dev is a PCI function.
  70 */
  71struct nvme_dev {
  72        struct list_head node;
  73        struct nvme_queue __rcu **queues;
  74        unsigned short __percpu *io_queue;
  75        u32 __iomem *dbs;
  76        struct pci_dev *pci_dev;
  77        struct dma_pool *prp_page_pool;
  78        struct dma_pool *prp_small_pool;
  79        int instance;
  80        unsigned queue_count;
  81        unsigned online_queues;
  82        unsigned max_qid;
  83        int q_depth;
  84        u32 db_stride;
  85        u32 ctrl_config;
  86        struct msix_entry *entry;
  87        struct nvme_bar __iomem *bar;
  88        struct list_head namespaces;
  89        struct kref kref;
  90        struct miscdevice miscdev;
  91        work_func_t reset_workfn;
  92        struct work_struct reset_work;
  93        struct work_struct cpu_work;
  94        char name[12];
  95        char serial[20];
  96        char model[40];
  97        char firmware_rev[8];
  98        u32 max_hw_sectors;
  99        u32 stripe_size;
 100        u16 oncs;
 101        u16 abort_limit;
 102        u8 vwc;
 103        u8 initialized;
 104};
 105
 106/*
 107 * An NVM Express namespace is equivalent to a SCSI LUN
 108 */
 109struct nvme_ns {
 110        struct list_head list;
 111
 112        struct nvme_dev *dev;
 113        struct request_queue *queue;
 114        struct gendisk *disk;
 115
 116        unsigned ns_id;
 117        int lba_shift;
 118        int ms;
 119        u64 mode_select_num_blocks;
 120        u32 mode_select_block_len;
 121};
 122
 123/*
 124 * The nvme_iod describes the data in an I/O, including the list of PRP
 125 * entries.  You can't see it in this data structure because C doesn't let
 126 * me express that.  Use nvme_alloc_iod to ensure there's enough space
 127 * allocated to store the PRP list.
 128 */
 129struct nvme_iod {
 130        void *private;          /* For the use of the submitter of the I/O */
 131        int npages;             /* In the PRP list. 0 means small pool in use */
 132        int offset;             /* Of PRP list */
 133        int nents;              /* Used in scatterlist */
 134        int length;             /* Of data, in bytes */
 135        unsigned long start_time;
 136        dma_addr_t first_dma;
 137        struct list_head node;
 138        struct scatterlist sg[0];
 139};
 140
 141static inline u64 nvme_block_nr(struct nvme_ns *ns, sector_t sector)
 142{
 143        return (sector >> (ns->lba_shift - 9));
 144}
 145
 146/**
 147 * nvme_free_iod - frees an nvme_iod
 148 * @dev: The device that the I/O was submitted to
 149 * @iod: The memory to free
 150 */
 151void nvme_free_iod(struct nvme_dev *dev, struct nvme_iod *iod);
 152
 153int nvme_setup_prps(struct nvme_dev *, struct nvme_iod *, int , gfp_t);
 154struct nvme_iod *nvme_map_user_pages(struct nvme_dev *dev, int write,
 155                                unsigned long addr, unsigned length);
 156void nvme_unmap_user_pages(struct nvme_dev *dev, int write,
 157                        struct nvme_iod *iod);
 158int nvme_submit_io_cmd(struct nvme_dev *, struct nvme_command *, u32 *);
 159int nvme_submit_admin_cmd(struct nvme_dev *, struct nvme_command *,
 160                                                        u32 *result);
 161int nvme_identify(struct nvme_dev *, unsigned nsid, unsigned cns,
 162                                                        dma_addr_t dma_addr);
 163int nvme_get_features(struct nvme_dev *dev, unsigned fid, unsigned nsid,
 164                        dma_addr_t dma_addr, u32 *result);
 165int nvme_set_features(struct nvme_dev *dev, unsigned fid, unsigned dword11,
 166                        dma_addr_t dma_addr, u32 *result);
 167
 168struct sg_io_hdr;
 169
 170int nvme_sg_io(struct nvme_ns *ns, struct sg_io_hdr __user *u_hdr);
 171int nvme_sg_io32(struct nvme_ns *ns, unsigned long arg);
 172int nvme_sg_get_version_num(int __user *ip);
 173
 174#endif /* _LINUX_NVME_H */
 175