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19#include <linux/module.h>
20#include <linux/kernel.h>
21#include <linux/init.h>
22#include <linux/io.h>
23#include <linux/clk.h>
24
25#include <asm/tlb.h>
26#include <asm/mach/map.h>
27
28#include <linux/omap-dma.h>
29
30#include "omap_hwmod.h"
31#include "soc.h"
32#include "iomap.h"
33#include "voltage.h"
34#include "powerdomain.h"
35#include "clockdomain.h"
36#include "common.h"
37#include "clock.h"
38#include "clock2xxx.h"
39#include "clock3xxx.h"
40#include "clock44xx.h"
41#include "omap-pm.h"
42#include "sdrc.h"
43#include "control.h"
44#include "serial.h"
45#include "sram.h"
46#include "cm2xxx.h"
47#include "cm3xxx.h"
48#include "prm.h"
49#include "cm.h"
50#include "prcm_mpu44xx.h"
51#include "prminst44xx.h"
52#include "cminst44xx.h"
53#include "prm2xxx.h"
54#include "prm3xxx.h"
55#include "prm44xx.h"
56#include "opp2xxx.h"
57
58
59
60
61
62static int (*omap_clk_soc_init)(void);
63
64
65
66
67
68
69#if defined(CONFIG_SOC_OMAP2420) || defined(CONFIG_SOC_OMAP2430)
70static struct map_desc omap24xx_io_desc[] __initdata = {
71 {
72 .virtual = L3_24XX_VIRT,
73 .pfn = __phys_to_pfn(L3_24XX_PHYS),
74 .length = L3_24XX_SIZE,
75 .type = MT_DEVICE
76 },
77 {
78 .virtual = L4_24XX_VIRT,
79 .pfn = __phys_to_pfn(L4_24XX_PHYS),
80 .length = L4_24XX_SIZE,
81 .type = MT_DEVICE
82 },
83};
84
85#ifdef CONFIG_SOC_OMAP2420
86static struct map_desc omap242x_io_desc[] __initdata = {
87 {
88 .virtual = DSP_MEM_2420_VIRT,
89 .pfn = __phys_to_pfn(DSP_MEM_2420_PHYS),
90 .length = DSP_MEM_2420_SIZE,
91 .type = MT_DEVICE
92 },
93 {
94 .virtual = DSP_IPI_2420_VIRT,
95 .pfn = __phys_to_pfn(DSP_IPI_2420_PHYS),
96 .length = DSP_IPI_2420_SIZE,
97 .type = MT_DEVICE
98 },
99 {
100 .virtual = DSP_MMU_2420_VIRT,
101 .pfn = __phys_to_pfn(DSP_MMU_2420_PHYS),
102 .length = DSP_MMU_2420_SIZE,
103 .type = MT_DEVICE
104 },
105};
106
107#endif
108
109#ifdef CONFIG_SOC_OMAP2430
110static struct map_desc omap243x_io_desc[] __initdata = {
111 {
112 .virtual = L4_WK_243X_VIRT,
113 .pfn = __phys_to_pfn(L4_WK_243X_PHYS),
114 .length = L4_WK_243X_SIZE,
115 .type = MT_DEVICE
116 },
117 {
118 .virtual = OMAP243X_GPMC_VIRT,
119 .pfn = __phys_to_pfn(OMAP243X_GPMC_PHYS),
120 .length = OMAP243X_GPMC_SIZE,
121 .type = MT_DEVICE
122 },
123 {
124 .virtual = OMAP243X_SDRC_VIRT,
125 .pfn = __phys_to_pfn(OMAP243X_SDRC_PHYS),
126 .length = OMAP243X_SDRC_SIZE,
127 .type = MT_DEVICE
128 },
129 {
130 .virtual = OMAP243X_SMS_VIRT,
131 .pfn = __phys_to_pfn(OMAP243X_SMS_PHYS),
132 .length = OMAP243X_SMS_SIZE,
133 .type = MT_DEVICE
134 },
135};
136#endif
137#endif
138
139#ifdef CONFIG_ARCH_OMAP3
140static struct map_desc omap34xx_io_desc[] __initdata = {
141 {
142 .virtual = L3_34XX_VIRT,
143 .pfn = __phys_to_pfn(L3_34XX_PHYS),
144 .length = L3_34XX_SIZE,
145 .type = MT_DEVICE
146 },
147 {
148 .virtual = L4_34XX_VIRT,
149 .pfn = __phys_to_pfn(L4_34XX_PHYS),
150 .length = L4_34XX_SIZE,
151 .type = MT_DEVICE
152 },
153 {
154 .virtual = OMAP34XX_GPMC_VIRT,
155 .pfn = __phys_to_pfn(OMAP34XX_GPMC_PHYS),
156 .length = OMAP34XX_GPMC_SIZE,
157 .type = MT_DEVICE
158 },
159 {
160 .virtual = OMAP343X_SMS_VIRT,
161 .pfn = __phys_to_pfn(OMAP343X_SMS_PHYS),
162 .length = OMAP343X_SMS_SIZE,
163 .type = MT_DEVICE
164 },
165 {
166 .virtual = OMAP343X_SDRC_VIRT,
167 .pfn = __phys_to_pfn(OMAP343X_SDRC_PHYS),
168 .length = OMAP343X_SDRC_SIZE,
169 .type = MT_DEVICE
170 },
171 {
172 .virtual = L4_PER_34XX_VIRT,
173 .pfn = __phys_to_pfn(L4_PER_34XX_PHYS),
174 .length = L4_PER_34XX_SIZE,
175 .type = MT_DEVICE
176 },
177 {
178 .virtual = L4_EMU_34XX_VIRT,
179 .pfn = __phys_to_pfn(L4_EMU_34XX_PHYS),
180 .length = L4_EMU_34XX_SIZE,
181 .type = MT_DEVICE
182 },
183};
184#endif
185
186#ifdef CONFIG_SOC_TI81XX
187static struct map_desc omapti81xx_io_desc[] __initdata = {
188 {
189 .virtual = L4_34XX_VIRT,
190 .pfn = __phys_to_pfn(L4_34XX_PHYS),
191 .length = L4_34XX_SIZE,
192 .type = MT_DEVICE
193 }
194};
195#endif
196
197#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
198static struct map_desc omapam33xx_io_desc[] __initdata = {
199 {
200 .virtual = L4_34XX_VIRT,
201 .pfn = __phys_to_pfn(L4_34XX_PHYS),
202 .length = L4_34XX_SIZE,
203 .type = MT_DEVICE
204 },
205 {
206 .virtual = L4_WK_AM33XX_VIRT,
207 .pfn = __phys_to_pfn(L4_WK_AM33XX_PHYS),
208 .length = L4_WK_AM33XX_SIZE,
209 .type = MT_DEVICE
210 }
211};
212#endif
213
214#ifdef CONFIG_ARCH_OMAP4
215static struct map_desc omap44xx_io_desc[] __initdata = {
216 {
217 .virtual = L3_44XX_VIRT,
218 .pfn = __phys_to_pfn(L3_44XX_PHYS),
219 .length = L3_44XX_SIZE,
220 .type = MT_DEVICE,
221 },
222 {
223 .virtual = L4_44XX_VIRT,
224 .pfn = __phys_to_pfn(L4_44XX_PHYS),
225 .length = L4_44XX_SIZE,
226 .type = MT_DEVICE,
227 },
228 {
229 .virtual = L4_PER_44XX_VIRT,
230 .pfn = __phys_to_pfn(L4_PER_44XX_PHYS),
231 .length = L4_PER_44XX_SIZE,
232 .type = MT_DEVICE,
233 },
234};
235#endif
236
237#if defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX)
238static struct map_desc omap54xx_io_desc[] __initdata = {
239 {
240 .virtual = L3_54XX_VIRT,
241 .pfn = __phys_to_pfn(L3_54XX_PHYS),
242 .length = L3_54XX_SIZE,
243 .type = MT_DEVICE,
244 },
245 {
246 .virtual = L4_54XX_VIRT,
247 .pfn = __phys_to_pfn(L4_54XX_PHYS),
248 .length = L4_54XX_SIZE,
249 .type = MT_DEVICE,
250 },
251 {
252 .virtual = L4_WK_54XX_VIRT,
253 .pfn = __phys_to_pfn(L4_WK_54XX_PHYS),
254 .length = L4_WK_54XX_SIZE,
255 .type = MT_DEVICE,
256 },
257 {
258 .virtual = L4_PER_54XX_VIRT,
259 .pfn = __phys_to_pfn(L4_PER_54XX_PHYS),
260 .length = L4_PER_54XX_SIZE,
261 .type = MT_DEVICE,
262 },
263};
264#endif
265
266#ifdef CONFIG_SOC_OMAP2420
267void __init omap242x_map_io(void)
268{
269 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
270 iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc));
271}
272#endif
273
274#ifdef CONFIG_SOC_OMAP2430
275void __init omap243x_map_io(void)
276{
277 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
278 iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc));
279}
280#endif
281
282#ifdef CONFIG_ARCH_OMAP3
283void __init omap3_map_io(void)
284{
285 iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc));
286}
287#endif
288
289#ifdef CONFIG_SOC_TI81XX
290void __init ti81xx_map_io(void)
291{
292 iotable_init(omapti81xx_io_desc, ARRAY_SIZE(omapti81xx_io_desc));
293}
294#endif
295
296#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
297void __init am33xx_map_io(void)
298{
299 iotable_init(omapam33xx_io_desc, ARRAY_SIZE(omapam33xx_io_desc));
300}
301#endif
302
303#ifdef CONFIG_ARCH_OMAP4
304void __init omap4_map_io(void)
305{
306 iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc));
307 omap_barriers_init();
308}
309#endif
310
311#if defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX)
312void __init omap5_map_io(void)
313{
314 iotable_init(omap54xx_io_desc, ARRAY_SIZE(omap54xx_io_desc));
315 omap_barriers_init();
316}
317#endif
318
319
320
321
322
323
324
325
326
327
328static int __init _omap2_init_reprogram_sdrc(void)
329{
330 struct clk *dpll3_m2_ck;
331 int v = -EINVAL;
332 long rate;
333
334 if (!cpu_is_omap34xx())
335 return 0;
336
337 dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck");
338 if (IS_ERR(dpll3_m2_ck))
339 return -EINVAL;
340
341 rate = clk_get_rate(dpll3_m2_ck);
342 pr_info("Reprogramming SDRC clock to %ld Hz\n", rate);
343 v = clk_set_rate(dpll3_m2_ck, rate);
344 if (v)
345 pr_err("dpll3_m2_clk rate change failed: %d\n", v);
346
347 clk_put(dpll3_m2_ck);
348
349 return v;
350}
351
352static int _set_hwmod_postsetup_state(struct omap_hwmod *oh, void *data)
353{
354 return omap_hwmod_set_postsetup_state(oh, *(u8 *)data);
355}
356
357static void __init omap_hwmod_init_postsetup(void)
358{
359 u8 postsetup_state;
360
361
362#ifdef CONFIG_PM_RUNTIME
363 postsetup_state = _HWMOD_STATE_IDLE;
364#else
365 postsetup_state = _HWMOD_STATE_ENABLED;
366#endif
367 omap_hwmod_for_each(_set_hwmod_postsetup_state, &postsetup_state);
368
369 omap_pm_if_early_init();
370}
371
372static void __init __maybe_unused omap_common_late_init(void)
373{
374 omap_mux_late_init();
375 omap2_common_pm_late_init();
376 omap_soc_device_init();
377}
378
379#ifdef CONFIG_SOC_OMAP2420
380void __init omap2420_init_early(void)
381{
382 omap2_set_globals_tap(OMAP242X_CLASS, OMAP2_L4_IO_ADDRESS(0x48014000));
383 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE),
384 OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE));
385 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE),
386 NULL);
387 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP2420_PRM_BASE));
388 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP2420_CM_BASE), NULL);
389 omap2xxx_check_revision();
390 omap2xxx_prm_init();
391 omap2xxx_cm_init();
392 omap2xxx_voltagedomains_init();
393 omap242x_powerdomains_init();
394 omap242x_clockdomains_init();
395 omap2420_hwmod_init();
396 omap_hwmod_init_postsetup();
397 omap_clk_soc_init = omap2420_dt_clk_init;
398 rate_table = omap2420_rate_table;
399}
400
401void __init omap2420_init_late(void)
402{
403 omap_common_late_init();
404 omap2_pm_init();
405 omap2_clk_enable_autoidle_all();
406}
407#endif
408
409#ifdef CONFIG_SOC_OMAP2430
410void __init omap2430_init_early(void)
411{
412 omap2_set_globals_tap(OMAP243X_CLASS, OMAP2_L4_IO_ADDRESS(0x4900a000));
413 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE),
414 OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE));
415 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE),
416 NULL);
417 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP2430_PRM_BASE));
418 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP2430_CM_BASE), NULL);
419 omap2xxx_check_revision();
420 omap2xxx_prm_init();
421 omap2xxx_cm_init();
422 omap2xxx_voltagedomains_init();
423 omap243x_powerdomains_init();
424 omap243x_clockdomains_init();
425 omap2430_hwmod_init();
426 omap_hwmod_init_postsetup();
427 omap_clk_soc_init = omap2430_dt_clk_init;
428 rate_table = omap2430_rate_table;
429}
430
431void __init omap2430_init_late(void)
432{
433 omap_common_late_init();
434 omap2_pm_init();
435 omap2_clk_enable_autoidle_all();
436}
437#endif
438
439
440
441
442
443#ifdef CONFIG_ARCH_OMAP3
444void __init omap3_init_early(void)
445{
446 omap2_set_globals_tap(OMAP343X_CLASS, OMAP2_L4_IO_ADDRESS(0x4830A000));
447 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE),
448 OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE));
449 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE),
450 NULL);
451 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE));
452 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE), NULL);
453 omap3xxx_check_revision();
454 omap3xxx_check_features();
455 omap3xxx_prm_init();
456 omap3xxx_cm_init();
457 omap3xxx_voltagedomains_init();
458 omap3xxx_powerdomains_init();
459 omap3xxx_clockdomains_init();
460 omap3xxx_hwmod_init();
461 omap_hwmod_init_postsetup();
462 omap_clk_soc_init = omap3xxx_clk_init;
463}
464
465void __init omap3430_init_early(void)
466{
467 omap3_init_early();
468 if (of_have_populated_dt())
469 omap_clk_soc_init = omap3430_dt_clk_init;
470}
471
472void __init omap35xx_init_early(void)
473{
474 omap3_init_early();
475 if (of_have_populated_dt())
476 omap_clk_soc_init = omap3430_dt_clk_init;
477}
478
479void __init omap3630_init_early(void)
480{
481 omap3_init_early();
482 if (of_have_populated_dt())
483 omap_clk_soc_init = omap3630_dt_clk_init;
484}
485
486void __init am35xx_init_early(void)
487{
488 omap3_init_early();
489 if (of_have_populated_dt())
490 omap_clk_soc_init = am35xx_dt_clk_init;
491}
492
493void __init ti81xx_init_early(void)
494{
495 omap2_set_globals_tap(OMAP343X_CLASS,
496 OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE));
497 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(TI81XX_CTRL_BASE),
498 NULL);
499 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE));
500 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE), NULL);
501 omap3xxx_check_revision();
502 ti81xx_check_features();
503 omap3xxx_voltagedomains_init();
504 omap3xxx_powerdomains_init();
505 omap3xxx_clockdomains_init();
506 omap3xxx_hwmod_init();
507 omap_hwmod_init_postsetup();
508 if (of_have_populated_dt())
509 omap_clk_soc_init = ti81xx_dt_clk_init;
510 else
511 omap_clk_soc_init = omap3xxx_clk_init;
512}
513
514void __init omap3_init_late(void)
515{
516 omap_common_late_init();
517 omap3_pm_init();
518 omap2_clk_enable_autoidle_all();
519}
520
521void __init omap3430_init_late(void)
522{
523 omap_common_late_init();
524 omap3_pm_init();
525 omap2_clk_enable_autoidle_all();
526}
527
528void __init omap35xx_init_late(void)
529{
530 omap_common_late_init();
531 omap3_pm_init();
532 omap2_clk_enable_autoidle_all();
533}
534
535void __init omap3630_init_late(void)
536{
537 omap_common_late_init();
538 omap3_pm_init();
539 omap2_clk_enable_autoidle_all();
540}
541
542void __init am35xx_init_late(void)
543{
544 omap_common_late_init();
545 omap3_pm_init();
546 omap2_clk_enable_autoidle_all();
547}
548
549void __init ti81xx_init_late(void)
550{
551 omap_common_late_init();
552 omap3_pm_init();
553 omap2_clk_enable_autoidle_all();
554}
555#endif
556
557#ifdef CONFIG_SOC_AM33XX
558void __init am33xx_init_early(void)
559{
560 omap2_set_globals_tap(AM335X_CLASS,
561 AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE));
562 omap2_set_globals_control(AM33XX_L4_WK_IO_ADDRESS(AM33XX_CTRL_BASE),
563 NULL);
564 omap2_set_globals_prm(AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE));
565 omap2_set_globals_cm(AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE), NULL);
566 omap3xxx_check_revision();
567 am33xx_check_features();
568 am33xx_powerdomains_init();
569 am33xx_clockdomains_init();
570 am33xx_hwmod_init();
571 omap_hwmod_init_postsetup();
572 omap_clk_soc_init = am33xx_dt_clk_init;
573}
574
575void __init am33xx_init_late(void)
576{
577 omap_common_late_init();
578}
579#endif
580
581#ifdef CONFIG_SOC_AM43XX
582void __init am43xx_init_early(void)
583{
584 omap2_set_globals_tap(AM335X_CLASS,
585 AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE));
586 omap2_set_globals_control(AM33XX_L4_WK_IO_ADDRESS(AM33XX_CTRL_BASE),
587 NULL);
588 omap2_set_globals_prm(AM33XX_L4_WK_IO_ADDRESS(AM43XX_PRCM_BASE));
589 omap2_set_globals_cm(AM33XX_L4_WK_IO_ADDRESS(AM43XX_PRCM_BASE), NULL);
590 omap_prm_base_init();
591 omap_cm_base_init();
592 omap3xxx_check_revision();
593 am33xx_check_features();
594 am43xx_powerdomains_init();
595 am43xx_clockdomains_init();
596 am43xx_hwmod_init();
597 omap_hwmod_init_postsetup();
598 omap_l2_cache_init();
599 omap_clk_soc_init = am43xx_dt_clk_init;
600}
601
602void __init am43xx_init_late(void)
603{
604 omap_common_late_init();
605}
606#endif
607
608#ifdef CONFIG_ARCH_OMAP4
609void __init omap4430_init_early(void)
610{
611 omap2_set_globals_tap(OMAP443X_CLASS,
612 OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE));
613 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE),
614 OMAP2_L4_IO_ADDRESS(OMAP443X_CTRL_BASE));
615 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE));
616 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP4430_CM_BASE),
617 OMAP2_L4_IO_ADDRESS(OMAP4430_CM2_BASE));
618 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE));
619 omap_prm_base_init();
620 omap_cm_base_init();
621 omap4xxx_check_revision();
622 omap4xxx_check_features();
623 omap4_pm_init_early();
624 omap44xx_prm_init();
625 omap44xx_voltagedomains_init();
626 omap44xx_powerdomains_init();
627 omap44xx_clockdomains_init();
628 omap44xx_hwmod_init();
629 omap_hwmod_init_postsetup();
630 omap_l2_cache_init();
631 omap_clk_soc_init = omap4xxx_dt_clk_init;
632}
633
634void __init omap4430_init_late(void)
635{
636 omap_common_late_init();
637 omap4_pm_init();
638 omap2_clk_enable_autoidle_all();
639}
640#endif
641
642#ifdef CONFIG_SOC_OMAP5
643void __init omap5_init_early(void)
644{
645 omap2_set_globals_tap(OMAP54XX_CLASS,
646 OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE));
647 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE),
648 OMAP2_L4_IO_ADDRESS(OMAP54XX_CTRL_BASE));
649 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRM_BASE));
650 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_AON_BASE),
651 OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_BASE));
652 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
653 omap4_pm_init_early();
654 omap_prm_base_init();
655 omap_cm_base_init();
656 omap44xx_prm_init();
657 omap5xxx_check_revision();
658 omap54xx_voltagedomains_init();
659 omap54xx_powerdomains_init();
660 omap54xx_clockdomains_init();
661 omap54xx_hwmod_init();
662 omap_hwmod_init_postsetup();
663 omap_clk_soc_init = omap5xxx_dt_clk_init;
664}
665
666void __init omap5_init_late(void)
667{
668 omap_common_late_init();
669 omap4_pm_init();
670 omap2_clk_enable_autoidle_all();
671}
672#endif
673
674#ifdef CONFIG_SOC_DRA7XX
675void __init dra7xx_init_early(void)
676{
677 omap2_set_globals_tap(-1, OMAP2_L4_IO_ADDRESS(DRA7XX_TAP_BASE));
678 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE),
679 OMAP2_L4_IO_ADDRESS(DRA7XX_CTRL_BASE));
680 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRM_BASE));
681 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(DRA7XX_CM_CORE_AON_BASE),
682 OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_BASE));
683 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
684 omap4_pm_init_early();
685 omap_prm_base_init();
686 omap_cm_base_init();
687 omap44xx_prm_init();
688 dra7xxx_check_revision();
689 dra7xx_powerdomains_init();
690 dra7xx_clockdomains_init();
691 dra7xx_hwmod_init();
692 omap_hwmod_init_postsetup();
693 omap_clk_soc_init = dra7xx_dt_clk_init;
694}
695
696void __init dra7xx_init_late(void)
697{
698 omap_common_late_init();
699 omap4_pm_init();
700 omap2_clk_enable_autoidle_all();
701}
702#endif
703
704
705void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
706 struct omap_sdrc_params *sdrc_cs1)
707{
708 omap_sram_init();
709
710 if (cpu_is_omap24xx() || omap3_has_sdrc()) {
711 omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
712 _omap2_init_reprogram_sdrc();
713 }
714}
715
716int __init omap_clk_init(void)
717{
718 int ret = 0;
719
720 if (!omap_clk_soc_init)
721 return 0;
722
723 ti_clk_init_features();
724
725 ret = of_prcm_init();
726 if (ret)
727 return ret;
728
729 of_clk_init(NULL);
730
731 ti_dt_clk_init_retry_clks();
732
733 ti_dt_clockdomains_setup();
734
735 ret = omap_clk_soc_init();
736
737 return ret;
738}
739
