LXR linux/arch/arm/mach-omap2/omap-secure.c

   1/*
   2 * OMAP Secure API infrastructure.
   3 *
   4 * Copyright (C) 2011 Texas Instruments, Inc.
   5 *      Santosh Shilimkar <santosh.shilimkar@ti.com>
   6 * Copyright (C) 2012 Ivaylo Dimitrov <freemangordon@abv.bg>
   7 * Copyright (C) 2013 Pali Rohár <pali.rohar@gmail.com>
   8 *
   9 *
  10 * This program is free software,you can redistribute it and/or modify
  11 * it under the terms of the GNU General Public License version 2 as
  12 * published by the Free Software Foundation.
  13 */
  14
  15#include <linux/kernel.h>
  16#include <linux/init.h>
  17#include <linux/io.h>
  18#include <linux/memblock.h>
  19
  20#include <asm/cacheflush.h>
  21#include <asm/memblock.h>
  22
  23#include "omap-secure.h"
  24
  25static phys_addr_t omap_secure_memblock_base;
  26
  27/**
  28 * omap_sec_dispatcher: Routine to dispatch low power secure
  29 * service routines
  30 * @idx: The HAL API index
  31 * @flag: The flag indicating criticality of operation
  32 * @nargs: Number of valid arguments out of four.
  33 * @arg1, arg2, arg3 args4: Parameters passed to secure API
  34 *
  35 * Return the non-zero error value on failure.
  36 */
  37u32 omap_secure_dispatcher(u32 idx, u32 flag, u32 nargs, u32 arg1, u32 arg2,
  38                                                         u32 arg3, u32 arg4)
  39{
  40        u32 ret;
  41        u32 param[5];
  42
  43        param[0] = nargs;
  44        param[1] = arg1;
  45        param[2] = arg2;
  46        param[3] = arg3;
  47        param[4] = arg4;
  48
  49        /*
  50         * Secure API needs physical address
  51         * pointer for the parameters
  52         */
  53        flush_cache_all();
  54        outer_clean_range(__pa(param), __pa(param + 5));
  55        ret = omap_smc2(idx, flag, __pa(param));
  56
  57        return ret;
  58}
  59
  60/* Allocate the memory to save secure ram */
  61int __init omap_secure_ram_reserve_memblock(void)
  62{
  63        u32 size = OMAP_SECURE_RAM_STORAGE;
  64
  65        size = ALIGN(size, SECTION_SIZE);
  66        omap_secure_memblock_base = arm_memblock_steal(size, SECTION_SIZE);
  67
  68        return 0;
  69}
  70
  71phys_addr_t omap_secure_ram_mempool_base(void)
  72{
  73        return omap_secure_memblock_base;
  74}
  75
  76/**
  77 * rx51_secure_dispatcher: Routine to dispatch secure PPA API calls
  78 * @idx: The PPA API index
  79 * @process: Process ID
  80 * @flag: The flag indicating criticality of operation
  81 * @nargs: Number of valid arguments out of four.
  82 * @arg1, arg2, arg3 args4: Parameters passed to secure API
  83 *
  84 * Return the non-zero error value on failure.
  85 *
  86 * NOTE: rx51_secure_dispatcher differs from omap_secure_dispatcher because
  87 *       it calling omap_smc3() instead omap_smc2() and param[0] is nargs+1
  88 */
  89u32 rx51_secure_dispatcher(u32 idx, u32 process, u32 flag, u32 nargs,
  90                           u32 arg1, u32 arg2, u32 arg3, u32 arg4)
  91{
  92        u32 ret;
  93        u32 param[5];
  94
  95        param[0] = nargs+1; /* RX-51 needs number of arguments + 1 */
  96        param[1] = arg1;
  97        param[2] = arg2;
  98        param[3] = arg3;
  99        param[4] = arg4;
 100
 101        /*
 102         * Secure API needs physical address
 103         * pointer for the parameters
 104         */
 105        local_irq_disable();
 106        local_fiq_disable();
 107        flush_cache_all();
 108        outer_clean_range(__pa(param), __pa(param + 5));
 109        ret = omap_smc3(idx, process, flag, __pa(param));
 110        flush_cache_all();
 111        local_fiq_enable();
 112        local_irq_enable();
 113
 114        return ret;
 115}
 116
 117/**
 118 * rx51_secure_update_aux_cr: Routine to modify the contents of Auxiliary Control Register
 119 *  @set_bits: bits to set in ACR
 120 *  @clr_bits: bits to clear in ACR
 121 *
 122 * Return the non-zero error value on failure.
 123*/
 124u32 rx51_secure_update_aux_cr(u32 set_bits, u32 clear_bits)
 125{
 126        u32 acr;
 127
 128        /* Read ACR */
 129        asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
 130        acr &= ~clear_bits;
 131        acr |= set_bits;
 132
 133        return rx51_secure_dispatcher(RX51_PPA_WRITE_ACR,
 134                                      0,
 135                                      FLAG_START_CRITICAL,
 136                                      1, acr, 0, 0, 0);
 137}
 138
 139/**
 140 * rx51_secure_rng_call: Routine for HW random generator
 141 */
 142u32 rx51_secure_rng_call(u32 ptr, u32 count, u32 flag)
 143{
 144        return rx51_secure_dispatcher(RX51_PPA_HWRNG,
 145                                      0,
 146                                      NO_FLAG,
 147                                      3, ptr, count, flag, 0);
 148}
 149