LXR linux/arch/blackfin/mach-bf537/boards/dnp5370.c

   1/*
   2 * This is the configuration for SSV Dil/NetPC DNP/5370 board.
   3 *
   4 * DIL module:         http://www.dilnetpc.com/dnp0086.htm
   5 * SK28 (starter kit): http://www.dilnetpc.com/dnp0088.htm
   6 *
   7 * Copyright 2010 3ality Digital Systems
   8 * Copyright 2005 National ICT Australia (NICTA)
   9 * Copyright 2004-2006 Analog Devices Inc.
  10 *
  11 * Licensed under the GPL-2 or later.
  12 */
  13
  14#include <linux/device.h>
  15#include <linux/export.h>
  16#include <linux/kernel.h>
  17#include <linux/platform_device.h>
  18#include <linux/io.h>
  19#include <linux/mtd/mtd.h>
  20#include <linux/mtd/nand.h>
  21#include <linux/mtd/partitions.h>
  22#include <linux/mtd/plat-ram.h>
  23#include <linux/mtd/physmap.h>
  24#include <linux/spi/spi.h>
  25#include <linux/spi/flash.h>
  26#include <linux/irq.h>
  27#include <linux/interrupt.h>
  28#include <linux/i2c.h>
  29#include <linux/spi/mmc_spi.h>
  30#include <linux/phy.h>
  31#include <asm/dma.h>
  32#include <asm/bfin5xx_spi.h>
  33#include <asm/reboot.h>
  34#include <asm/portmux.h>
  35#include <asm/dpmc.h>
  36
  37/*
  38 * Name the Board for the /proc/cpuinfo
  39 */
  40const char bfin_board_name[] = "DNP/5370";
  41#define FLASH_MAC               0x202f0000
  42#define CONFIG_MTD_PHYSMAP_LEN  0x300000
  43
  44#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
  45static struct platform_device rtc_device = {
  46        .name = "rtc-bfin",
  47        .id   = -1,
  48};
  49#endif
  50
  51#if IS_ENABLED(CONFIG_BFIN_MAC)
  52#include <linux/bfin_mac.h>
  53static const unsigned short bfin_mac_peripherals[] = P_RMII0;
  54
  55static struct bfin_phydev_platform_data bfin_phydev_data[] = {
  56        {
  57                .addr = 1,
  58                .irq = PHY_POLL, /* IRQ_MAC_PHYINT */
  59        },
  60};
  61
  62static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
  63        .phydev_number   = 1,
  64        .phydev_data     = bfin_phydev_data,
  65        .phy_mode        = PHY_INTERFACE_MODE_RMII,
  66        .mac_peripherals = bfin_mac_peripherals,
  67};
  68
  69static struct platform_device bfin_mii_bus = {
  70        .name = "bfin_mii_bus",
  71        .dev = {
  72                .platform_data = &bfin_mii_bus_data,
  73        }
  74};
  75
  76static struct platform_device bfin_mac_device = {
  77        .name = "bfin_mac",
  78        .dev = {
  79                .platform_data = &bfin_mii_bus,
  80        }
  81};
  82#endif
  83
  84#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
  85static struct mtd_partition asmb_flash_partitions[] = {
  86        {
  87                .name       = "bootloader(nor)",
  88                .size       = 0x30000,
  89                .offset     = 0,
  90        }, {
  91                .name       = "linux kernel and rootfs(nor)",
  92                .size       = 0x300000 - 0x30000 - 0x10000,
  93                .offset     = MTDPART_OFS_APPEND,
  94        }, {
  95                .name       = "MAC address(nor)",
  96                .size       = 0x10000,
  97                .offset     = MTDPART_OFS_APPEND,
  98                .mask_flags = MTD_WRITEABLE,
  99        }
 100};
 101
 102static struct physmap_flash_data asmb_flash_data = {
 103        .width      = 1,
 104        .parts      = asmb_flash_partitions,
 105        .nr_parts   = ARRAY_SIZE(asmb_flash_partitions),
 106};
 107
 108static struct resource asmb_flash_resource = {
 109        .start = 0x20000000,
 110        .end   = 0x202fffff,
 111        .flags = IORESOURCE_MEM,
 112};
 113
 114/* 4 MB NOR flash attached to async memory banks 0-2,
 115 * therefore only 3 MB visible.
 116 */
 117static struct platform_device asmb_flash_device = {
 118        .name     = "physmap-flash",
 119        .id       = 0,
 120        .dev = {
 121                .platform_data = &asmb_flash_data,
 122        },
 123        .num_resources = 1,
 124        .resource      = &asmb_flash_resource,
 125};
 126#endif
 127
 128#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
 129
 130#if IS_ENABLED(CONFIG_MMC_SPI)
 131
 132static struct bfin5xx_spi_chip mmc_spi_chip_info = {
 133        .enable_dma    = 0,      /* use no dma transfer with this chip*/
 134};
 135
 136#endif
 137
 138#if IS_ENABLED(CONFIG_MTD_DATAFLASH)
 139/* This mapping is for at45db642 it has 1056 page size,
 140 * partition size and offset should be page aligned
 141 */
 142static struct mtd_partition bfin_spi_dataflash_partitions[] = {
 143        {
 144                .name   = "JFFS2 dataflash(nor)",
 145#ifdef CONFIG_MTD_PAGESIZE_1024
 146                .offset = 0x40000,
 147                .size   = 0x7C0000,
 148#else
 149                .offset = 0x0,
 150                .size   = 0x840000,
 151#endif
 152        }
 153};
 154
 155static struct flash_platform_data bfin_spi_dataflash_data = {
 156        .name     = "mtd_dataflash",
 157        .parts    = bfin_spi_dataflash_partitions,
 158        .nr_parts = ARRAY_SIZE(bfin_spi_dataflash_partitions),
 159        .type     = "mtd_dataflash",
 160};
 161
 162static struct bfin5xx_spi_chip spi_dataflash_chip_info = {
 163        .enable_dma    = 0,      /* use no dma transfer with this chip*/
 164};
 165#endif
 166
 167static struct spi_board_info bfin_spi_board_info[] __initdata = {
 168/* SD/MMC card reader at SPI bus */
 169#if IS_ENABLED(CONFIG_MMC_SPI)
 170        {
 171                .modalias        = "mmc_spi",
 172                .max_speed_hz    = 20000000,
 173                .bus_num         = 0,
 174                .chip_select     = 1,
 175                .controller_data = &mmc_spi_chip_info,
 176                .mode            = SPI_MODE_3,
 177        },
 178#endif
 179
 180/* 8 Megabyte Atmel NOR flash chip at SPI bus */
 181#if IS_ENABLED(CONFIG_MTD_DATAFLASH)
 182        {
 183        .modalias        = "mtd_dataflash",
 184        .max_speed_hz    = 16700000,
 185        .bus_num         = 0,
 186        .chip_select     = 2,
 187        .platform_data   = &bfin_spi_dataflash_data,
 188        .controller_data = &spi_dataflash_chip_info,
 189        .mode            = SPI_MODE_3, /* SPI_CPHA and SPI_CPOL */
 190        },
 191#endif
 192};
 193
 194/* SPI controller data */
 195/* SPI (0) */
 196static struct resource bfin_spi0_resource[] = {
 197        [0] = {
 198                .start = SPI0_REGBASE,
 199                .end   = SPI0_REGBASE + 0xFF,
 200                .flags = IORESOURCE_MEM,
 201        },
 202        [1] = {
 203                .start = CH_SPI,
 204                .end   = CH_SPI,
 205                .flags = IORESOURCE_DMA,
 206        },
 207        [2] = {
 208                .start = IRQ_SPI,
 209                .end   = IRQ_SPI,
 210                .flags = IORESOURCE_IRQ,
 211        },
 212};
 213
 214static struct bfin5xx_spi_master spi_bfin_master_info = {
 215        .num_chipselect = 8,
 216        .enable_dma     = 1,  /* master has the ability to do dma transfer */
 217        .pin_req        = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
 218};
 219
 220static struct platform_device spi_bfin_master_device = {
 221        .name          = "bfin-spi",
 222        .id            = 0, /* Bus number */
 223        .num_resources = ARRAY_SIZE(bfin_spi0_resource),
 224        .resource      = bfin_spi0_resource,
 225        .dev           = {
 226                .platform_data = &spi_bfin_master_info, /* Passed to driver */
 227        },
 228};
 229#endif
 230
 231#if IS_ENABLED(CONFIG_SERIAL_BFIN)
 232#ifdef CONFIG_SERIAL_BFIN_UART0
 233static struct resource bfin_uart0_resources[] = {
 234        {
 235                .start = UART0_THR,
 236                .end = UART0_GCTL+2,
 237                .flags = IORESOURCE_MEM,
 238        },
 239        {
 240                .start = IRQ_UART0_TX,
 241                .end = IRQ_UART0_TX,
 242                .flags = IORESOURCE_IRQ,
 243        },
 244        {
 245                .start = IRQ_UART0_RX,
 246                .end = IRQ_UART0_RX,
 247                .flags = IORESOURCE_IRQ,
 248        },
 249        {
 250                .start = IRQ_UART0_ERROR,
 251                .end = IRQ_UART0_ERROR,
 252                .flags = IORESOURCE_IRQ,
 253        },
 254        {
 255                .start = CH_UART0_TX,
 256                .end = CH_UART0_TX,
 257                .flags = IORESOURCE_DMA,
 258        },
 259        {
 260                .start = CH_UART0_RX,
 261                .end = CH_UART0_RX,
 262                .flags = IORESOURCE_DMA,
 263        },
 264};
 265
 266static unsigned short bfin_uart0_peripherals[] = {
 267        P_UART0_TX, P_UART0_RX, 0
 268};
 269
 270static struct platform_device bfin_uart0_device = {
 271        .name = "bfin-uart",
 272        .id = 0,
 273        .num_resources = ARRAY_SIZE(bfin_uart0_resources),
 274        .resource = bfin_uart0_resources,
 275        .dev = {
 276                .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
 277        },
 278};
 279#endif
 280
 281#ifdef CONFIG_SERIAL_BFIN_UART1
 282static struct resource bfin_uart1_resources[] = {
 283        {
 284                .start = UART1_THR,
 285                .end   = UART1_GCTL+2,
 286                .flags = IORESOURCE_MEM,
 287        },
 288        {
 289                .start = IRQ_UART1_TX,
 290                .end   = IRQ_UART1_TX,
 291                .flags = IORESOURCE_IRQ,
 292        },
 293        {
 294                .start = IRQ_UART1_RX,
 295                .end   = IRQ_UART1_RX,
 296                .flags = IORESOURCE_IRQ,
 297        },
 298        {
 299                .start = IRQ_UART1_ERROR,
 300                .end   = IRQ_UART1_ERROR,
 301                .flags = IORESOURCE_IRQ,
 302        },
 303        {
 304                .start = CH_UART1_TX,
 305                .end   = CH_UART1_TX,
 306                .flags = IORESOURCE_DMA,
 307        },
 308        {
 309                .start = CH_UART1_RX,
 310                .end   = CH_UART1_RX,
 311                .flags = IORESOURCE_DMA,
 312        },
 313};
 314
 315static unsigned short bfin_uart1_peripherals[] = {
 316        P_UART1_TX, P_UART1_RX, 0
 317};
 318
 319static struct platform_device bfin_uart1_device = {
 320        .name          = "bfin-uart",
 321        .id            = 1,
 322        .num_resources = ARRAY_SIZE(bfin_uart1_resources),
 323        .resource      = bfin_uart1_resources,
 324        .dev = {
 325                .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
 326        },
 327};
 328#endif
 329#endif
 330
 331#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
 332static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
 333
 334static struct resource bfin_twi0_resource[] = {
 335        [0] = {
 336                .start = TWI0_REGBASE,
 337                .end   = TWI0_REGBASE + 0xff,
 338                .flags = IORESOURCE_MEM,
 339        },
 340        [1] = {
 341                .start = IRQ_TWI,
 342                .end   = IRQ_TWI,
 343                .flags = IORESOURCE_IRQ,
 344        },
 345};
 346
 347static struct platform_device i2c_bfin_twi_device = {
 348        .name          = "i2c-bfin-twi",
 349        .id            = 0,
 350        .num_resources = ARRAY_SIZE(bfin_twi0_resource),
 351        .resource      = bfin_twi0_resource,
 352        .dev = {
 353                .platform_data = &bfin_twi0_pins,
 354        },
 355};
 356#endif
 357
 358static struct platform_device *dnp5370_devices[] __initdata = {
 359
 360#if IS_ENABLED(CONFIG_SERIAL_BFIN)
 361#ifdef CONFIG_SERIAL_BFIN_UART0
 362        &bfin_uart0_device,
 363#endif
 364#ifdef CONFIG_SERIAL_BFIN_UART1
 365        &bfin_uart1_device,
 366#endif
 367#endif
 368
 369#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
 370        &asmb_flash_device,
 371#endif
 372
 373#if IS_ENABLED(CONFIG_BFIN_MAC)
 374        &bfin_mii_bus,
 375        &bfin_mac_device,
 376#endif
 377
 378#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
 379        &spi_bfin_master_device,
 380#endif
 381
 382#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
 383        &i2c_bfin_twi_device,
 384#endif
 385
 386#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
 387        &rtc_device,
 388#endif
 389
 390};
 391
 392static int __init dnp5370_init(void)
 393{
 394        printk(KERN_INFO "DNP/5370: registering device resources\n");
 395        platform_add_devices(dnp5370_devices, ARRAY_SIZE(dnp5370_devices));
 396        printk(KERN_INFO "DNP/5370: registering %zu SPI slave devices\n",
 397               ARRAY_SIZE(bfin_spi_board_info));
 398        spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
 399        printk(KERN_INFO "DNP/5370: MAC %pM\n", (void *)FLASH_MAC);
 400        return 0;
 401}
 402arch_initcall(dnp5370_init);
 403
 404/*
 405 * Currently the MAC address is saved in Flash by U-Boot
 406 */
 407int bfin_get_ether_addr(char *addr)
 408{
 409        *(u32 *)(&(addr[0])) = bfin_read32(FLASH_MAC);
 410        *(u16 *)(&(addr[4])) = bfin_read16(FLASH_MAC + 4);
 411        return 0;
 412}
 413EXPORT_SYMBOL(bfin_get_ether_addr);
 414