LXR linux/arch/powerpc/include/asm/cputable.h

   1#ifndef __ASM_POWERPC_CPUTABLE_H
   2#define __ASM_POWERPC_CPUTABLE_H
   3
   4
   5#include <asm/asm-compat.h>
   6#include <asm/feature-fixups.h>
   7#include <uapi/asm/cputable.h>
   8
   9#ifndef __ASSEMBLY__
  10
  11/* This structure can grow, it's real size is used by head.S code
  12 * via the mkdefs mechanism.
  13 */
  14struct cpu_spec;
  15
  16typedef void (*cpu_setup_t)(unsigned long offset, struct cpu_spec* spec);
  17typedef void (*cpu_restore_t)(void);
  18
  19enum powerpc_oprofile_type {
  20        PPC_OPROFILE_INVALID = 0,
  21        PPC_OPROFILE_RS64 = 1,
  22        PPC_OPROFILE_POWER4 = 2,
  23        PPC_OPROFILE_G4 = 3,
  24        PPC_OPROFILE_FSL_EMB = 4,
  25        PPC_OPROFILE_CELL = 5,
  26        PPC_OPROFILE_PA6T = 6,
  27};
  28
  29enum powerpc_pmc_type {
  30        PPC_PMC_DEFAULT = 0,
  31        PPC_PMC_IBM = 1,
  32        PPC_PMC_PA6T = 2,
  33        PPC_PMC_G4 = 3,
  34};
  35
  36struct pt_regs;
  37
  38extern int machine_check_generic(struct pt_regs *regs);
  39extern int machine_check_4xx(struct pt_regs *regs);
  40extern int machine_check_440A(struct pt_regs *regs);
  41extern int machine_check_e500mc(struct pt_regs *regs);
  42extern int machine_check_e500(struct pt_regs *regs);
  43extern int machine_check_e200(struct pt_regs *regs);
  44extern int machine_check_47x(struct pt_regs *regs);
  45
  46/* NOTE WELL: Update identify_cpu() if fields are added or removed! */
  47struct cpu_spec {
  48        /* CPU is matched via (PVR & pvr_mask) == pvr_value */
  49        unsigned int    pvr_mask;
  50        unsigned int    pvr_value;
  51
  52        char            *cpu_name;
  53        unsigned long   cpu_features;           /* Kernel features */
  54        unsigned int    cpu_user_features;      /* Userland features */
  55        unsigned int    cpu_user_features2;     /* Userland features v2 */
  56        unsigned int    mmu_features;           /* MMU features */
  57
  58        /* cache line sizes */
  59        unsigned int    icache_bsize;
  60        unsigned int    dcache_bsize;
  61
  62        /* number of performance monitor counters */
  63        unsigned int    num_pmcs;
  64        enum powerpc_pmc_type pmc_type;
  65
  66        /* this is called to initialize various CPU bits like L1 cache,
  67         * BHT, SPD, etc... from head.S before branching to identify_machine
  68         */
  69        cpu_setup_t     cpu_setup;
  70        /* Used to restore cpu setup on secondary processors and at resume */
  71        cpu_restore_t   cpu_restore;
  72
  73        /* Used by oprofile userspace to select the right counters */
  74        char            *oprofile_cpu_type;
  75
  76        /* Processor specific oprofile operations */
  77        enum powerpc_oprofile_type oprofile_type;
  78
  79        /* Bit locations inside the mmcra change */
  80        unsigned long   oprofile_mmcra_sihv;
  81        unsigned long   oprofile_mmcra_sipr;
  82
  83        /* Bits to clear during an oprofile exception */
  84        unsigned long   oprofile_mmcra_clear;
  85
  86        /* Name of processor class, for the ELF AT_PLATFORM entry */
  87        char            *platform;
  88
  89        /* Processor specific machine check handling. Return negative
  90         * if the error is fatal, 1 if it was fully recovered and 0 to
  91         * pass up (not CPU originated) */
  92        int             (*machine_check)(struct pt_regs *regs);
  93
  94        /*
  95         * Processor specific early machine check handler which is
  96         * called in real mode to handle SLB and TLB errors.
  97         */
  98        long            (*machine_check_early)(struct pt_regs *regs);
  99
 100        /*
 101         * Processor specific routine to flush tlbs.
 102         */
 103        void            (*flush_tlb)(unsigned long inval_selector);
 104
 105};
 106
 107extern struct cpu_spec          *cur_cpu_spec;
 108
 109extern unsigned int __start___ftr_fixup, __stop___ftr_fixup;
 110
 111extern struct cpu_spec *identify_cpu(unsigned long offset, unsigned int pvr);
 112extern void do_feature_fixups(unsigned long value, void *fixup_start,
 113                              void *fixup_end);
 114
 115extern const char *powerpc_base_platform;
 116
 117#endif /* __ASSEMBLY__ */
 118
 119/* CPU kernel features */
 120
 121/* Retain the 32b definitions all use bottom half of word */
 122#define CPU_FTR_COHERENT_ICACHE         ASM_CONST(0x00000001)
 123#define CPU_FTR_L2CR                    ASM_CONST(0x00000002)
 124#define CPU_FTR_SPEC7450                ASM_CONST(0x00000004)
 125#define CPU_FTR_ALTIVEC                 ASM_CONST(0x00000008)
 126#define CPU_FTR_TAU                     ASM_CONST(0x00000010)
 127#define CPU_FTR_CAN_DOZE                ASM_CONST(0x00000020)
 128#define CPU_FTR_USE_TB                  ASM_CONST(0x00000040)
 129#define CPU_FTR_L2CSR                   ASM_CONST(0x00000080)
 130#define CPU_FTR_601                     ASM_CONST(0x00000100)
 131#define CPU_FTR_DBELL                   ASM_CONST(0x00000200)
 132#define CPU_FTR_CAN_NAP                 ASM_CONST(0x00000400)
 133#define CPU_FTR_L3CR                    ASM_CONST(0x00000800)
 134#define CPU_FTR_L3_DISABLE_NAP          ASM_CONST(0x00001000)
 135#define CPU_FTR_NAP_DISABLE_L2_PR       ASM_CONST(0x00002000)
 136#define CPU_FTR_DUAL_PLL_750FX          ASM_CONST(0x00004000)
 137#define CPU_FTR_NO_DPM                  ASM_CONST(0x00008000)
 138#define CPU_FTR_476_DD2                 ASM_CONST(0x00010000)
 139#define CPU_FTR_NEED_COHERENT           ASM_CONST(0x00020000)
 140#define CPU_FTR_NO_BTIC                 ASM_CONST(0x00040000)
 141#define CPU_FTR_DEBUG_LVL_EXC           ASM_CONST(0x00080000)
 142#define CPU_FTR_NODSISRALIGN            ASM_CONST(0x00100000)
 143#define CPU_FTR_PPC_LE                  ASM_CONST(0x00200000)
 144#define CPU_FTR_REAL_LE                 ASM_CONST(0x00400000)
 145#define CPU_FTR_FPU_UNAVAILABLE         ASM_CONST(0x00800000)
 146#define CPU_FTR_UNIFIED_ID_CACHE        ASM_CONST(0x01000000)
 147#define CPU_FTR_SPE                     ASM_CONST(0x02000000)
 148#define CPU_FTR_NEED_PAIRED_STWCX       ASM_CONST(0x04000000)
 149#define CPU_FTR_LWSYNC                  ASM_CONST(0x08000000)
 150#define CPU_FTR_NOEXECUTE               ASM_CONST(0x10000000)
 151#define CPU_FTR_INDEXED_DCR             ASM_CONST(0x20000000)
 152#define CPU_FTR_EMB_HV                  ASM_CONST(0x40000000)
 153
 154/*
 155 * Add the 64-bit processor unique features in the top half of the word;
 156 * on 32-bit, make the names available but defined to be 0.
 157 */
 158#ifdef __powerpc64__
 159#define LONG_ASM_CONST(x)               ASM_CONST(x)
 160#else
 161#define LONG_ASM_CONST(x)               0
 162#endif
 163
 164#define CPU_FTR_HVMODE                  LONG_ASM_CONST(0x0000000100000000)
 165#define CPU_FTR_ARCH_201                LONG_ASM_CONST(0x0000000200000000)
 166#define CPU_FTR_ARCH_206                LONG_ASM_CONST(0x0000000400000000)
 167#define CPU_FTR_ARCH_207S               LONG_ASM_CONST(0x0000000800000000)
 168#define CPU_FTR_IABR                    LONG_ASM_CONST(0x0000001000000000)
 169#define CPU_FTR_MMCRA                   LONG_ASM_CONST(0x0000002000000000)
 170#define CPU_FTR_CTRL                    LONG_ASM_CONST(0x0000004000000000)
 171#define CPU_FTR_SMT                     LONG_ASM_CONST(0x0000008000000000)
 172#define CPU_FTR_PAUSE_ZERO              LONG_ASM_CONST(0x0000010000000000)
 173#define CPU_FTR_PURR                    LONG_ASM_CONST(0x0000020000000000)
 174#define CPU_FTR_CELL_TB_BUG             LONG_ASM_CONST(0x0000040000000000)
 175#define CPU_FTR_SPURR                   LONG_ASM_CONST(0x0000080000000000)
 176#define CPU_FTR_DSCR                    LONG_ASM_CONST(0x0000100000000000)
 177#define CPU_FTR_VSX                     LONG_ASM_CONST(0x0000200000000000)
 178#define CPU_FTR_SAO                     LONG_ASM_CONST(0x0000400000000000)
 179#define CPU_FTR_CP_USE_DCBTZ            LONG_ASM_CONST(0x0000800000000000)
 180#define CPU_FTR_UNALIGNED_LD_STD        LONG_ASM_CONST(0x0001000000000000)
 181#define CPU_FTR_ASYM_SMT                LONG_ASM_CONST(0x0002000000000000)
 182#define CPU_FTR_STCX_CHECKS_ADDRESS     LONG_ASM_CONST(0x0004000000000000)
 183#define CPU_FTR_POPCNTB                 LONG_ASM_CONST(0x0008000000000000)
 184#define CPU_FTR_POPCNTD                 LONG_ASM_CONST(0x0010000000000000)
 185#define CPU_FTR_ICSWX                   LONG_ASM_CONST(0x0020000000000000)
 186#define CPU_FTR_VMX_COPY                LONG_ASM_CONST(0x0040000000000000)
 187#define CPU_FTR_TM                      LONG_ASM_CONST(0x0080000000000000)
 188#define CPU_FTR_CFAR                    LONG_ASM_CONST(0x0100000000000000)
 189#define CPU_FTR_HAS_PPR                 LONG_ASM_CONST(0x0200000000000000)
 190#define CPU_FTR_DAWR                    LONG_ASM_CONST(0x0400000000000000)
 191#define CPU_FTR_DABRX                   LONG_ASM_CONST(0x0800000000000000)
 192#define CPU_FTR_PMAO_BUG                LONG_ASM_CONST(0x1000000000000000)
 193
 194#ifndef __ASSEMBLY__
 195
 196#define CPU_FTR_PPCAS_ARCH_V2   (CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN)
 197
 198#define MMU_FTR_PPCAS_ARCH_V2   (MMU_FTR_TLBIEL | MMU_FTR_16M_PAGE)
 199
 200/* We only set the altivec features if the kernel was compiled with altivec
 201 * support
 202 */
 203#ifdef CONFIG_ALTIVEC
 204#define CPU_FTR_ALTIVEC_COMP    CPU_FTR_ALTIVEC
 205#define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
 206#else
 207#define CPU_FTR_ALTIVEC_COMP    0
 208#define PPC_FEATURE_HAS_ALTIVEC_COMP    0
 209#endif
 210
 211/* We only set the VSX features if the kernel was compiled with VSX
 212 * support
 213 */
 214#ifdef CONFIG_VSX
 215#define CPU_FTR_VSX_COMP        CPU_FTR_VSX
 216#define PPC_FEATURE_HAS_VSX_COMP PPC_FEATURE_HAS_VSX
 217#else
 218#define CPU_FTR_VSX_COMP        0
 219#define PPC_FEATURE_HAS_VSX_COMP    0
 220#endif
 221
 222/* We only set the spe features if the kernel was compiled with spe
 223 * support
 224 */
 225#ifdef CONFIG_SPE
 226#define CPU_FTR_SPE_COMP        CPU_FTR_SPE
 227#define PPC_FEATURE_HAS_SPE_COMP PPC_FEATURE_HAS_SPE
 228#define PPC_FEATURE_HAS_EFP_SINGLE_COMP PPC_FEATURE_HAS_EFP_SINGLE
 229#define PPC_FEATURE_HAS_EFP_DOUBLE_COMP PPC_FEATURE_HAS_EFP_DOUBLE
 230#else
 231#define CPU_FTR_SPE_COMP        0
 232#define PPC_FEATURE_HAS_SPE_COMP    0
 233#define PPC_FEATURE_HAS_EFP_SINGLE_COMP 0
 234#define PPC_FEATURE_HAS_EFP_DOUBLE_COMP 0
 235#endif
 236
 237/* We only set the TM feature if the kernel was compiled with TM supprt */
 238#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
 239#define CPU_FTR_TM_COMP         CPU_FTR_TM
 240#define PPC_FEATURE2_HTM_COMP   PPC_FEATURE2_HTM
 241#else
 242#define CPU_FTR_TM_COMP         0
 243#define PPC_FEATURE2_HTM_COMP   0
 244#endif
 245
 246/* We need to mark all pages as being coherent if we're SMP or we have a
 247 * 74[45]x and an MPC107 host bridge. Also 83xx and PowerQUICC II
 248 * require it for PCI "streaming/prefetch" to work properly.
 249 * This is also required by 52xx family.
 250 */
 251#if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE) \
 252        || defined(CONFIG_PPC_83xx) || defined(CONFIG_8260) \
 253        || defined(CONFIG_PPC_MPC52xx)
 254#define CPU_FTR_COMMON                  CPU_FTR_NEED_COHERENT
 255#else
 256#define CPU_FTR_COMMON                  0
 257#endif
 258
 259/* The powersave features NAP & DOZE seems to confuse BDI when
 260   debugging. So if a BDI is used, disable theses
 261 */
 262#ifndef CONFIG_BDI_SWITCH
 263#define CPU_FTR_MAYBE_CAN_DOZE  CPU_FTR_CAN_DOZE
 264#define CPU_FTR_MAYBE_CAN_NAP   CPU_FTR_CAN_NAP
 265#else
 266#define CPU_FTR_MAYBE_CAN_DOZE  0
 267#define CPU_FTR_MAYBE_CAN_NAP   0
 268#endif
 269
 270#define CPU_FTRS_PPC601 (CPU_FTR_COMMON | CPU_FTR_601 | \
 271        CPU_FTR_COHERENT_ICACHE | CPU_FTR_UNIFIED_ID_CACHE)
 272#define CPU_FTRS_603    (CPU_FTR_COMMON | \
 273            CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
 274            CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
 275#define CPU_FTRS_604    (CPU_FTR_COMMON | \
 276            CPU_FTR_USE_TB | CPU_FTR_PPC_LE)
 277#define CPU_FTRS_740_NOTAU      (CPU_FTR_COMMON | \
 278            CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
 279            CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
 280#define CPU_FTRS_740    (CPU_FTR_COMMON | \
 281            CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
 282            CPU_FTR_TAU | CPU_FTR_MAYBE_CAN_NAP | \
 283            CPU_FTR_PPC_LE)
 284#define CPU_FTRS_750    (CPU_FTR_COMMON | \
 285            CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
 286            CPU_FTR_TAU | CPU_FTR_MAYBE_CAN_NAP | \
 287            CPU_FTR_PPC_LE)
 288#define CPU_FTRS_750CL  (CPU_FTRS_750)
 289#define CPU_FTRS_750FX1 (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM)
 290#define CPU_FTRS_750FX2 (CPU_FTRS_750 | CPU_FTR_NO_DPM)
 291#define CPU_FTRS_750FX  (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX)
 292#define CPU_FTRS_750GX  (CPU_FTRS_750FX)
 293#define CPU_FTRS_7400_NOTAU     (CPU_FTR_COMMON | \
 294            CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
 295            CPU_FTR_ALTIVEC_COMP | \
 296            CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
 297#define CPU_FTRS_7400   (CPU_FTR_COMMON | \
 298            CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
 299            CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | \
 300            CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
 301#define CPU_FTRS_7450_20        (CPU_FTR_COMMON | \
 302            CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
 303            CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
 304            CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
 305#define CPU_FTRS_7450_21        (CPU_FTR_COMMON | \
 306            CPU_FTR_USE_TB | \
 307            CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
 308            CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
 309            CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
 310            CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
 311#define CPU_FTRS_7450_23        (CPU_FTR_COMMON | \
 312            CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
 313            CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
 314            CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
 315            CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
 316#define CPU_FTRS_7455_1 (CPU_FTR_COMMON | \
 317            CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
 318            CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | \
 319            CPU_FTR_SPEC7450 | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
 320#define CPU_FTRS_7455_20        (CPU_FTR_COMMON | \
 321            CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
 322            CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
 323            CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
 324            CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
 325            CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
 326#define CPU_FTRS_7455   (CPU_FTR_COMMON | \
 327            CPU_FTR_USE_TB | \
 328            CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
 329            CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
 330            CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
 331#define CPU_FTRS_7447_10        (CPU_FTR_COMMON | \
 332            CPU_FTR_USE_TB | \
 333            CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
 334            CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
 335            CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC | CPU_FTR_PPC_LE | \
 336            CPU_FTR_NEED_PAIRED_STWCX)
 337#define CPU_FTRS_7447   (CPU_FTR_COMMON | \
 338            CPU_FTR_USE_TB | \
 339            CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
 340            CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
 341            CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
 342#define CPU_FTRS_7447A  (CPU_FTR_COMMON | \
 343            CPU_FTR_USE_TB | \
 344            CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
 345            CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
 346            CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
 347#define CPU_FTRS_7448   (CPU_FTR_COMMON | \
 348            CPU_FTR_USE_TB | \
 349            CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
 350            CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
 351            CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
 352#define CPU_FTRS_82XX   (CPU_FTR_COMMON | \
 353            CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB)
 354#define CPU_FTRS_G2_LE  (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | \
 355            CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP)
 356#define CPU_FTRS_E300   (CPU_FTR_MAYBE_CAN_DOZE | \
 357            CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | \
 358            CPU_FTR_COMMON)
 359#define CPU_FTRS_E300C2 (CPU_FTR_MAYBE_CAN_DOZE | \
 360            CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | \
 361            CPU_FTR_COMMON | CPU_FTR_FPU_UNAVAILABLE)
 362#define CPU_FTRS_CLASSIC32      (CPU_FTR_COMMON | CPU_FTR_USE_TB)
 363#define CPU_FTRS_8XX    (CPU_FTR_USE_TB)
 364#define CPU_FTRS_40X    (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
 365#define CPU_FTRS_44X    (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
 366#define CPU_FTRS_440x6  (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE | \
 367            CPU_FTR_INDEXED_DCR)
 368#define CPU_FTRS_47X    (CPU_FTRS_440x6)
 369#define CPU_FTRS_E200   (CPU_FTR_USE_TB | CPU_FTR_SPE_COMP | \
 370            CPU_FTR_NODSISRALIGN | CPU_FTR_COHERENT_ICACHE | \
 371            CPU_FTR_UNIFIED_ID_CACHE | CPU_FTR_NOEXECUTE | \
 372            CPU_FTR_DEBUG_LVL_EXC)
 373#define CPU_FTRS_E500   (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
 374            CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NODSISRALIGN | \
 375            CPU_FTR_NOEXECUTE)
 376#define CPU_FTRS_E500_2 (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
 377            CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | \
 378            CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
 379#define CPU_FTRS_E500MC (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \
 380            CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
 381            CPU_FTR_DBELL | CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV)
 382/*
 383 * e5500/e6500 erratum A-006958 is a timebase bug that can use the
 384 * same workaround as CPU_FTR_CELL_TB_BUG.
 385 */
 386#define CPU_FTRS_E5500  (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \
 387            CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
 388            CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
 389            CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV | CPU_FTR_CELL_TB_BUG)
 390#define CPU_FTRS_E6500  (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \
 391            CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
 392            CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
 393            CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV | CPU_FTR_ALTIVEC_COMP | \
 394            CPU_FTR_CELL_TB_BUG | CPU_FTR_SMT)
 395#define CPU_FTRS_GENERIC_32     (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN)
 396
 397/* 64-bit CPUs */
 398#define CPU_FTRS_POWER4 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
 399            CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
 400            CPU_FTR_MMCRA | CPU_FTR_CP_USE_DCBTZ | \
 401            CPU_FTR_STCX_CHECKS_ADDRESS)
 402#define CPU_FTRS_PPC970 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
 403            CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_201 | \
 404            CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA | \
 405            CPU_FTR_CP_USE_DCBTZ | CPU_FTR_STCX_CHECKS_ADDRESS | \
 406            CPU_FTR_HVMODE | CPU_FTR_DABRX)
 407#define CPU_FTRS_POWER5 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
 408            CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
 409            CPU_FTR_MMCRA | CPU_FTR_SMT | \
 410            CPU_FTR_COHERENT_ICACHE | CPU_FTR_PURR | \
 411            CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_DABRX)
 412#define CPU_FTRS_POWER6 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
 413            CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
 414            CPU_FTR_MMCRA | CPU_FTR_SMT | \
 415            CPU_FTR_COHERENT_ICACHE | \
 416            CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
 417            CPU_FTR_DSCR | CPU_FTR_UNALIGNED_LD_STD | \
 418            CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_CFAR | \
 419            CPU_FTR_DABRX)
 420#define CPU_FTRS_POWER7 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
 421            CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
 422            CPU_FTR_MMCRA | CPU_FTR_SMT | \
 423            CPU_FTR_COHERENT_ICACHE | \
 424            CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
 425            CPU_FTR_DSCR | CPU_FTR_SAO  | CPU_FTR_ASYM_SMT | \
 426            CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
 427            CPU_FTR_ICSWX | CPU_FTR_CFAR | CPU_FTR_HVMODE | \
 428            CPU_FTR_VMX_COPY | CPU_FTR_HAS_PPR | CPU_FTR_DABRX)
 429#define CPU_FTRS_POWER8 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
 430            CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
 431            CPU_FTR_MMCRA | CPU_FTR_SMT | \
 432            CPU_FTR_COHERENT_ICACHE | \
 433            CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
 434            CPU_FTR_DSCR | CPU_FTR_SAO  | \
 435            CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
 436            CPU_FTR_ICSWX | CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \
 437            CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_DAWR | \
 438            CPU_FTR_ARCH_207S | CPU_FTR_TM_COMP)
 439#define CPU_FTRS_POWER8E (CPU_FTRS_POWER8 | CPU_FTR_PMAO_BUG)
 440#define CPU_FTRS_POWER8_DD1 (CPU_FTRS_POWER8 & ~CPU_FTR_DBELL)
 441#define CPU_FTRS_CELL   (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
 442            CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
 443            CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
 444            CPU_FTR_PAUSE_ZERO  | CPU_FTR_CELL_TB_BUG | CPU_FTR_CP_USE_DCBTZ | \
 445            CPU_FTR_UNALIGNED_LD_STD | CPU_FTR_DABRX)
 446#define CPU_FTRS_PA6T (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
 447            CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP | \
 448            CPU_FTR_PURR | CPU_FTR_REAL_LE | CPU_FTR_DABRX)
 449#define CPU_FTRS_COMPATIBLE     (CPU_FTR_USE_TB | CPU_FTR_PPCAS_ARCH_V2)
 450
 451#define CPU_FTRS_A2 (CPU_FTR_USE_TB | CPU_FTR_SMT | CPU_FTR_DBELL | \
 452                     CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN | \
 453                     CPU_FTR_ICSWX | CPU_FTR_DABRX )
 454
 455#ifdef __powerpc64__
 456#ifdef CONFIG_PPC_BOOK3E
 457#define CPU_FTRS_POSSIBLE       (CPU_FTRS_E6500 | CPU_FTRS_E5500 | CPU_FTRS_A2)
 458#else
 459#define CPU_FTRS_POSSIBLE       \
 460            (CPU_FTRS_POWER4 | CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | \
 461             CPU_FTRS_POWER6 | CPU_FTRS_POWER7 | CPU_FTRS_POWER8E | \
 462             CPU_FTRS_POWER8 | CPU_FTRS_POWER8_DD1 | CPU_FTRS_CELL | \
 463             CPU_FTRS_PA6T | CPU_FTR_VSX)
 464#endif
 465#else
 466enum {
 467        CPU_FTRS_POSSIBLE =
 468#ifdef CONFIG_PPC_BOOK3S_32
 469            CPU_FTRS_PPC601 | CPU_FTRS_603 | CPU_FTRS_604 | CPU_FTRS_740_NOTAU |
 470            CPU_FTRS_740 | CPU_FTRS_750 | CPU_FTRS_750FX1 |
 471            CPU_FTRS_750FX2 | CPU_FTRS_750FX | CPU_FTRS_750GX |
 472            CPU_FTRS_7400_NOTAU | CPU_FTRS_7400 | CPU_FTRS_7450_20 |
 473            CPU_FTRS_7450_21 | CPU_FTRS_7450_23 | CPU_FTRS_7455_1 |
 474            CPU_FTRS_7455_20 | CPU_FTRS_7455 | CPU_FTRS_7447_10 |
 475            CPU_FTRS_7447 | CPU_FTRS_7447A | CPU_FTRS_82XX |
 476            CPU_FTRS_G2_LE | CPU_FTRS_E300 | CPU_FTRS_E300C2 |
 477            CPU_FTRS_CLASSIC32 |
 478#else
 479            CPU_FTRS_GENERIC_32 |
 480#endif
 481#ifdef CONFIG_8xx
 482            CPU_FTRS_8XX |
 483#endif
 484#ifdef CONFIG_40x
 485            CPU_FTRS_40X |
 486#endif
 487#ifdef CONFIG_44x
 488            CPU_FTRS_44X | CPU_FTRS_440x6 |
 489#endif
 490#ifdef CONFIG_PPC_47x
 491            CPU_FTRS_47X | CPU_FTR_476_DD2 |
 492#endif
 493#ifdef CONFIG_E200
 494            CPU_FTRS_E200 |
 495#endif
 496#ifdef CONFIG_E500
 497            CPU_FTRS_E500 | CPU_FTRS_E500_2 |
 498#endif
 499#ifdef CONFIG_PPC_E500MC
 500            CPU_FTRS_E500MC | CPU_FTRS_E5500 | CPU_FTRS_E6500 |
 501#endif
 502            0,
 503};
 504#endif /* __powerpc64__ */
 505
 506#ifdef __powerpc64__
 507#ifdef CONFIG_PPC_BOOK3E
 508#define CPU_FTRS_ALWAYS         (CPU_FTRS_E6500 & CPU_FTRS_E5500 & CPU_FTRS_A2)
 509#else
 510#define CPU_FTRS_ALWAYS         \
 511            (CPU_FTRS_POWER4 & CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & \
 512             CPU_FTRS_POWER6 & CPU_FTRS_POWER7 & CPU_FTRS_CELL & \
 513             CPU_FTRS_PA6T & CPU_FTRS_POWER8 & CPU_FTRS_POWER8E & \
 514             CPU_FTRS_POWER8_DD1 & CPU_FTRS_POSSIBLE)
 515#endif
 516#else
 517enum {
 518        CPU_FTRS_ALWAYS =
 519#ifdef CONFIG_PPC_BOOK3S_32
 520            CPU_FTRS_PPC601 & CPU_FTRS_603 & CPU_FTRS_604 & CPU_FTRS_740_NOTAU &
 521            CPU_FTRS_740 & CPU_FTRS_750 & CPU_FTRS_750FX1 &
 522            CPU_FTRS_750FX2 & CPU_FTRS_750FX & CPU_FTRS_750GX &
 523            CPU_FTRS_7400_NOTAU & CPU_FTRS_7400 & CPU_FTRS_7450_20 &
 524            CPU_FTRS_7450_21 & CPU_FTRS_7450_23 & CPU_FTRS_7455_1 &
 525            CPU_FTRS_7455_20 & CPU_FTRS_7455 & CPU_FTRS_7447_10 &
 526            CPU_FTRS_7447 & CPU_FTRS_7447A & CPU_FTRS_82XX &
 527            CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_E300C2 &
 528            CPU_FTRS_CLASSIC32 &
 529#else
 530            CPU_FTRS_GENERIC_32 &
 531#endif
 532#ifdef CONFIG_8xx
 533            CPU_FTRS_8XX &
 534#endif
 535#ifdef CONFIG_40x
 536            CPU_FTRS_40X &
 537#endif
 538#ifdef CONFIG_44x
 539            CPU_FTRS_44X & CPU_FTRS_440x6 &
 540#endif
 541#ifdef CONFIG_E200
 542            CPU_FTRS_E200 &
 543#endif
 544#ifdef CONFIG_E500
 545            CPU_FTRS_E500 & CPU_FTRS_E500_2 &
 546#endif
 547#ifdef CONFIG_PPC_E500MC
 548            CPU_FTRS_E500MC & CPU_FTRS_E5500 & CPU_FTRS_E6500 &
 549#endif
 550            ~CPU_FTR_EMB_HV &   /* can be removed at runtime */
 551            CPU_FTRS_POSSIBLE,
 552};
 553#endif /* __powerpc64__ */
 554
 555static inline int cpu_has_feature(unsigned long feature)
 556{
 557        return (CPU_FTRS_ALWAYS & feature) ||
 558               (CPU_FTRS_POSSIBLE
 559                & cur_cpu_spec->cpu_features
 560                & feature);
 561}
 562
 563#define HBP_NUM 1
 564
 565#endif /* !__ASSEMBLY__ */
 566
 567#endif /* __ASM_POWERPC_CPUTABLE_H */
 568