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30#include <linux/delay.h>
31#include <linux/dw_apb_timer.h>
32#include <linux/errno.h>
33#include <linux/init.h>
34#include <linux/slab.h>
35#include <linux/pm.h>
36#include <linux/sfi.h>
37#include <linux/interrupt.h>
38#include <linux/cpu.h>
39#include <linux/irq.h>
40
41#include <asm/fixmap.h>
42#include <asm/apb_timer.h>
43#include <asm/intel-mid.h>
44#include <asm/time.h>
45
46#define APBT_CLOCKEVENT_RATING 110
47#define APBT_CLOCKSOURCE_RATING 250
48
49#define APBT_CLOCKEVENT0_NUM (0)
50#define APBT_CLOCKSOURCE_NUM (2)
51
52static phys_addr_t apbt_address;
53static int apb_timer_block_enabled;
54static void __iomem *apbt_virt_address;
55
56
57
58
59static unsigned long apbt_freq;
60
61struct apbt_dev {
62 struct dw_apb_clock_event_device *timer;
63 unsigned int num;
64 int cpu;
65 unsigned int irq;
66 char name[10];
67};
68
69static struct dw_apb_clocksource *clocksource_apbt;
70
71static inline void __iomem *adev_virt_addr(struct apbt_dev *adev)
72{
73 return apbt_virt_address + adev->num * APBTMRS_REG_SIZE;
74}
75
76static DEFINE_PER_CPU(struct apbt_dev, cpu_apbt_dev);
77
78#ifdef CONFIG_SMP
79static unsigned int apbt_num_timers_used;
80#endif
81
82static inline void apbt_set_mapping(void)
83{
84 struct sfi_timer_table_entry *mtmr;
85 int phy_cs_timer_id = 0;
86
87 if (apbt_virt_address) {
88 pr_debug("APBT base already mapped\n");
89 return;
90 }
91 mtmr = sfi_get_mtmr(APBT_CLOCKEVENT0_NUM);
92 if (mtmr == NULL) {
93 printk(KERN_ERR "Failed to get MTMR %d from SFI\n",
94 APBT_CLOCKEVENT0_NUM);
95 return;
96 }
97 apbt_address = (phys_addr_t)mtmr->phys_addr;
98 if (!apbt_address) {
99 printk(KERN_WARNING "No timer base from SFI, use default\n");
100 apbt_address = APBT_DEFAULT_BASE;
101 }
102 apbt_virt_address = ioremap_nocache(apbt_address, APBT_MMAP_SIZE);
103 if (!apbt_virt_address) {
104 pr_debug("Failed mapping APBT phy address at %lu\n",\
105 (unsigned long)apbt_address);
106 goto panic_noapbt;
107 }
108 apbt_freq = mtmr->freq_hz;
109 sfi_free_mtmr(mtmr);
110
111
112 mtmr = sfi_get_mtmr(APBT_CLOCKSOURCE_NUM);
113 if (mtmr == NULL)
114 goto panic_noapbt;
115
116
117 pr_debug("Use timer %d for clocksource\n",
118 (int)(mtmr->phys_addr & 0xff) / APBTMRS_REG_SIZE);
119 phy_cs_timer_id = (unsigned int)(mtmr->phys_addr & 0xff) /
120 APBTMRS_REG_SIZE;
121
122 clocksource_apbt = dw_apb_clocksource_init(APBT_CLOCKSOURCE_RATING,
123 "apbt0", apbt_virt_address + phy_cs_timer_id *
124 APBTMRS_REG_SIZE, apbt_freq);
125 return;
126
127panic_noapbt:
128 panic("Failed to setup APB system timer\n");
129
130}
131
132static inline void apbt_clear_mapping(void)
133{
134 iounmap(apbt_virt_address);
135 apbt_virt_address = NULL;
136}
137
138
139
140
141static inline int is_apbt_capable(void)
142{
143 return apbt_virt_address ? 1 : 0;
144}
145
146static int __init apbt_clockevent_register(void)
147{
148 struct sfi_timer_table_entry *mtmr;
149 struct apbt_dev *adev = this_cpu_ptr(&cpu_apbt_dev);
150
151 mtmr = sfi_get_mtmr(APBT_CLOCKEVENT0_NUM);
152 if (mtmr == NULL) {
153 printk(KERN_ERR "Failed to get MTMR %d from SFI\n",
154 APBT_CLOCKEVENT0_NUM);
155 return -ENODEV;
156 }
157
158 adev->num = smp_processor_id();
159 adev->timer = dw_apb_clockevent_init(smp_processor_id(), "apbt0",
160 intel_mid_timer_options == INTEL_MID_TIMER_LAPIC_APBT ?
161 APBT_CLOCKEVENT_RATING - 100 : APBT_CLOCKEVENT_RATING,
162 adev_virt_addr(adev), 0, apbt_freq);
163
164 adev->timer->eoi = NULL;
165
166 if (intel_mid_timer_options == INTEL_MID_TIMER_LAPIC_APBT) {
167 global_clock_event = &adev->timer->ced;
168 printk(KERN_DEBUG "%s clockevent registered as global\n",
169 global_clock_event->name);
170 }
171
172 dw_apb_clockevent_register(adev->timer);
173
174 sfi_free_mtmr(mtmr);
175 return 0;
176}
177
178#ifdef CONFIG_SMP
179
180static void apbt_setup_irq(struct apbt_dev *adev)
181{
182
183 if (adev->irq == 0)
184 return;
185
186 irq_modify_status(adev->irq, 0, IRQ_MOVE_PCNTXT);
187 irq_set_affinity(adev->irq, cpumask_of(adev->cpu));
188}
189
190
191void apbt_setup_secondary_clock(void)
192{
193 struct apbt_dev *adev;
194 int cpu;
195
196
197 cpu = smp_processor_id();
198 if (!cpu)
199 return;
200
201 adev = this_cpu_ptr(&cpu_apbt_dev);
202 if (!adev->timer) {
203 adev->timer = dw_apb_clockevent_init(cpu, adev->name,
204 APBT_CLOCKEVENT_RATING, adev_virt_addr(adev),
205 adev->irq, apbt_freq);
206 adev->timer->eoi = NULL;
207 } else {
208 dw_apb_clockevent_resume(adev->timer);
209 }
210
211 printk(KERN_INFO "Registering CPU %d clockevent device %s, cpu %08x\n",
212 cpu, adev->name, adev->cpu);
213
214 apbt_setup_irq(adev);
215 dw_apb_clockevent_register(adev->timer);
216
217 return;
218}
219
220
221
222
223
224
225
226
227
228
229
230static int apbt_cpuhp_notify(struct notifier_block *n,
231 unsigned long action, void *hcpu)
232{
233 unsigned long cpu = (unsigned long)hcpu;
234 struct apbt_dev *adev = &per_cpu(cpu_apbt_dev, cpu);
235
236 switch (action & 0xf) {
237 case CPU_DEAD:
238 dw_apb_clockevent_pause(adev->timer);
239 if (system_state == SYSTEM_RUNNING) {
240 pr_debug("skipping APBT CPU %lu offline\n", cpu);
241 } else {
242 pr_debug("APBT clockevent for cpu %lu offline\n", cpu);
243 dw_apb_clockevent_stop(adev->timer);
244 }
245 break;
246 default:
247 pr_debug("APBT notified %lu, no action\n", action);
248 }
249 return NOTIFY_OK;
250}
251
252static __init int apbt_late_init(void)
253{
254 if (intel_mid_timer_options == INTEL_MID_TIMER_LAPIC_APBT ||
255 !apb_timer_block_enabled)
256 return 0;
257
258 hotcpu_notifier(apbt_cpuhp_notify, -20);
259 return 0;
260}
261fs_initcall(apbt_late_init);
262#else
263
264void apbt_setup_secondary_clock(void) {}
265
266#endif
267
268static int apbt_clocksource_register(void)
269{
270 u64 start, now;
271 cycle_t t1;
272
273
274 dw_apb_clocksource_start(clocksource_apbt);
275
276
277 t1 = dw_apb_clocksource_read(clocksource_apbt);
278 rdtscll(start);
279
280
281
282
283
284
285
286 do {
287 rep_nop();
288 rdtscll(now);
289 } while ((now - start) < 200000UL);
290
291
292 if (t1 == dw_apb_clocksource_read(clocksource_apbt))
293 panic("APBT counter not counting. APBT disabled\n");
294
295 dw_apb_clocksource_register(clocksource_apbt);
296
297 return 0;
298}
299
300
301
302
303
304
305
306
307void __init apbt_time_init(void)
308{
309#ifdef CONFIG_SMP
310 int i;
311 struct sfi_timer_table_entry *p_mtmr;
312 struct apbt_dev *adev;
313#endif
314
315 if (apb_timer_block_enabled)
316 return;
317 apbt_set_mapping();
318 if (!apbt_virt_address)
319 goto out_noapbt;
320
321
322
323
324
325 if (apbt_freq < APBT_MIN_FREQ || apbt_freq > APBT_MAX_FREQ) {
326 pr_debug("APBT has invalid freq 0x%lx\n", apbt_freq);
327 goto out_noapbt;
328 }
329 if (apbt_clocksource_register()) {
330 pr_debug("APBT has failed to register clocksource\n");
331 goto out_noapbt;
332 }
333 if (!apbt_clockevent_register())
334 apb_timer_block_enabled = 1;
335 else {
336 pr_debug("APBT has failed to register clockevent\n");
337 goto out_noapbt;
338 }
339#ifdef CONFIG_SMP
340
341 if (intel_mid_timer_options == INTEL_MID_TIMER_LAPIC_APBT) {
342 printk(KERN_INFO "apbt: disabled per cpu timer\n");
343 return;
344 }
345 pr_debug("%s: %d CPUs online\n", __func__, num_online_cpus());
346 if (num_possible_cpus() <= sfi_mtimer_num)
347 apbt_num_timers_used = num_possible_cpus();
348 else
349 apbt_num_timers_used = 1;
350 pr_debug("%s: %d APB timers used\n", __func__, apbt_num_timers_used);
351
352
353 for (i = 0; i < apbt_num_timers_used; i++) {
354 adev = &per_cpu(cpu_apbt_dev, i);
355 adev->num = i;
356 adev->cpu = i;
357 p_mtmr = sfi_get_mtmr(i);
358 if (p_mtmr)
359 adev->irq = p_mtmr->irq;
360 else
361 printk(KERN_ERR "Failed to get timer for cpu %d\n", i);
362 snprintf(adev->name, sizeof(adev->name) - 1, "apbt%d", i);
363 }
364#endif
365
366 return;
367
368out_noapbt:
369 apbt_clear_mapping();
370 apb_timer_block_enabled = 0;
371 panic("failed to enable APB timer\n");
372}
373
374
375unsigned long apbt_quick_calibrate(void)
376{
377 int i, scale;
378 u64 old, new;
379 cycle_t t1, t2;
380 unsigned long khz = 0;
381 u32 loop, shift;
382
383 apbt_set_mapping();
384 dw_apb_clocksource_start(clocksource_apbt);
385
386
387 old = dw_apb_clocksource_read(clocksource_apbt);
388 i = 10000;
389 while (--i) {
390 if (old != dw_apb_clocksource_read(clocksource_apbt))
391 break;
392 }
393 if (!i)
394 goto failed;
395
396
397 loop = (apbt_freq / 1000) << 4;
398
399
400 dw_apb_clocksource_start(clocksource_apbt);
401
402 old = dw_apb_clocksource_read(clocksource_apbt);
403 old += loop;
404
405 t1 = __native_read_tsc();
406
407 do {
408 new = dw_apb_clocksource_read(clocksource_apbt);
409 } while (new < old);
410
411 t2 = __native_read_tsc();
412
413 shift = 5;
414 if (unlikely(loop >> shift == 0)) {
415 printk(KERN_INFO
416 "APBT TSC calibration failed, not enough resolution\n");
417 return 0;
418 }
419 scale = (int)div_u64((t2 - t1), loop >> shift);
420 khz = (scale * (apbt_freq / 1000)) >> shift;
421 printk(KERN_INFO "TSC freq calculated by APB timer is %lu khz\n", khz);
422 return khz;
423failed:
424 return 0;
425}
426