LXR linux/drivers/gpu/drm/msm/msm

   1/*
   2 * Copyright (C) 2013 Red Hat
   3 * Author: Rob Clark <robdclark@gmail.com>
   4 *
   5 * This program is free software; you can redistribute it and/or modify it
   6 * under the terms of the GNU General Public License version 2 as published by
   7 * the Free Software Foundation.
   8 *
   9 * This program is distributed in the hope that it will be useful, but WITHOUT
  10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12 * more details.
  13 *
  14 * You should have received a copy of the GNU General Public License along with
  15 * this program.  If not, see <http://www.gnu.org/licenses/>.
  16 */
  17
  18#ifndef __MSM_DRV_H__
  19#define __MSM_DRV_H__
  20
  21#include <linux/kernel.h>
  22#include <linux/clk.h>
  23#include <linux/cpufreq.h>
  24#include <linux/module.h>
  25#include <linux/component.h>
  26#include <linux/platform_device.h>
  27#include <linux/pm.h>
  28#include <linux/pm_runtime.h>
  29#include <linux/slab.h>
  30#include <linux/list.h>
  31#include <linux/iommu.h>
  32#include <linux/types.h>
  33#include <asm/sizes.h>
  34
  35
  36#if defined(CONFIG_COMPILE_TEST) && !defined(CONFIG_ARCH_QCOM)
  37/* stubs we need for compile-test: */
  38static inline struct device *msm_iommu_get_ctx(const char *ctx_name)
  39{
  40        return NULL;
  41}
  42#endif
  43
  44#ifndef CONFIG_OF
  45#include <mach/board.h>
  46#include <mach/socinfo.h>
  47#include <mach/iommu_domains.h>
  48#endif
  49
  50#include <drm/drmP.h>
  51#include <drm/drm_crtc_helper.h>
  52#include <drm/drm_fb_helper.h>
  53#include <drm/msm_drm.h>
  54#include <drm/drm_gem.h>
  55
  56struct msm_kms;
  57struct msm_gpu;
  58struct msm_mmu;
  59struct msm_rd_state;
  60struct msm_perf_state;
  61struct msm_gem_submit;
  62
  63#define NUM_DOMAINS 2    /* one for KMS, then one per gpu core (?) */
  64
  65struct msm_file_private {
  66        /* currently we don't do anything useful with this.. but when
  67         * per-context address spaces are supported we'd keep track of
  68         * the context's page-tables here.
  69         */
  70        int dummy;
  71};
  72
  73struct msm_drm_private {
  74
  75        struct msm_kms *kms;
  76
  77        /* subordinate devices, if present: */
  78        struct platform_device *hdmi_pdev, *gpu_pdev;
  79
  80        /* when we have more than one 'msm_gpu' these need to be an array: */
  81        struct msm_gpu *gpu;
  82        struct msm_file_private *lastctx;
  83
  84        struct drm_fb_helper *fbdev;
  85
  86        uint32_t next_fence, completed_fence;
  87        wait_queue_head_t fence_event;
  88
  89        struct msm_rd_state *rd;
  90        struct msm_perf_state *perf;
  91
  92        /* list of GEM objects: */
  93        struct list_head inactive_list;
  94
  95        struct workqueue_struct *wq;
  96
  97        /* callbacks deferred until bo is inactive: */
  98        struct list_head fence_cbs;
  99
 100        /* registered MMUs: */
 101        unsigned int num_mmus;
 102        struct msm_mmu *mmus[NUM_DOMAINS];
 103
 104        unsigned int num_planes;
 105        struct drm_plane *planes[8];
 106
 107        unsigned int num_crtcs;
 108        struct drm_crtc *crtcs[8];
 109
 110        unsigned int num_encoders;
 111        struct drm_encoder *encoders[8];
 112
 113        unsigned int num_bridges;
 114        struct drm_bridge *bridges[8];
 115
 116        unsigned int num_connectors;
 117        struct drm_connector *connectors[8];
 118
 119        /* VRAM carveout, used when no IOMMU: */
 120        struct {
 121                unsigned long size;
 122                dma_addr_t paddr;
 123                /* NOTE: mm managed at the page level, size is in # of pages
 124                 * and position mm_node->start is in # of pages:
 125                 */
 126                struct drm_mm mm;
 127        } vram;
 128};
 129
 130struct msm_format {
 131        uint32_t pixel_format;
 132};
 133
 134/* callback from wq once fence has passed: */
 135struct msm_fence_cb {
 136        struct work_struct work;
 137        uint32_t fence;
 138        void (*func)(struct msm_fence_cb *cb);
 139};
 140
 141void __msm_fence_worker(struct work_struct *work);
 142
 143#define INIT_FENCE_CB(_cb, _func)  do {                     \
 144                INIT_WORK(&(_cb)->work, __msm_fence_worker); \
 145                (_cb)->func = _func;                         \
 146        } while (0)
 147
 148int msm_register_mmu(struct drm_device *dev, struct msm_mmu *mmu);
 149
 150int msm_wait_fence_interruptable(struct drm_device *dev, uint32_t fence,
 151                struct timespec *timeout);
 152void msm_update_fence(struct drm_device *dev, uint32_t fence);
 153
 154int msm_ioctl_gem_submit(struct drm_device *dev, void *data,
 155                struct drm_file *file);
 156
 157int msm_gem_mmap(struct file *filp, struct vm_area_struct *vma);
 158int msm_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
 159uint64_t msm_gem_mmap_offset(struct drm_gem_object *obj);
 160int msm_gem_get_iova_locked(struct drm_gem_object *obj, int id,
 161                uint32_t *iova);
 162int msm_gem_get_iova(struct drm_gem_object *obj, int id, uint32_t *iova);
 163struct page **msm_gem_get_pages(struct drm_gem_object *obj);
 164void msm_gem_put_pages(struct drm_gem_object *obj);
 165void msm_gem_put_iova(struct drm_gem_object *obj, int id);
 166int msm_gem_dumb_create(struct drm_file *file, struct drm_device *dev,
 167                struct drm_mode_create_dumb *args);
 168int msm_gem_dumb_map_offset(struct drm_file *file, struct drm_device *dev,
 169                uint32_t handle, uint64_t *offset);
 170struct sg_table *msm_gem_prime_get_sg_table(struct drm_gem_object *obj);
 171void *msm_gem_prime_vmap(struct drm_gem_object *obj);
 172void msm_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
 173struct drm_gem_object *msm_gem_prime_import_sg_table(struct drm_device *dev,
 174                struct dma_buf_attachment *attach, struct sg_table *sg);
 175int msm_gem_prime_pin(struct drm_gem_object *obj);
 176void msm_gem_prime_unpin(struct drm_gem_object *obj);
 177void *msm_gem_vaddr_locked(struct drm_gem_object *obj);
 178void *msm_gem_vaddr(struct drm_gem_object *obj);
 179int msm_gem_queue_inactive_cb(struct drm_gem_object *obj,
 180                struct msm_fence_cb *cb);
 181void msm_gem_move_to_active(struct drm_gem_object *obj,
 182                struct msm_gpu *gpu, bool write, uint32_t fence);
 183void msm_gem_move_to_inactive(struct drm_gem_object *obj);
 184int msm_gem_cpu_prep(struct drm_gem_object *obj, uint32_t op,
 185                struct timespec *timeout);
 186int msm_gem_cpu_fini(struct drm_gem_object *obj);
 187void msm_gem_free_object(struct drm_gem_object *obj);
 188int msm_gem_new_handle(struct drm_device *dev, struct drm_file *file,
 189                uint32_t size, uint32_t flags, uint32_t *handle);
 190struct drm_gem_object *msm_gem_new(struct drm_device *dev,
 191                uint32_t size, uint32_t flags);
 192struct drm_gem_object *msm_gem_import(struct drm_device *dev,
 193                uint32_t size, struct sg_table *sgt);
 194
 195struct drm_gem_object *msm_framebuffer_bo(struct drm_framebuffer *fb, int plane);
 196const struct msm_format *msm_framebuffer_format(struct drm_framebuffer *fb);
 197struct drm_framebuffer *msm_framebuffer_init(struct drm_device *dev,
 198                struct drm_mode_fb_cmd2 *mode_cmd, struct drm_gem_object **bos);
 199struct drm_framebuffer *msm_framebuffer_create(struct drm_device *dev,
 200                struct drm_file *file, struct drm_mode_fb_cmd2 *mode_cmd);
 201
 202struct drm_fb_helper *msm_fbdev_init(struct drm_device *dev);
 203
 204struct hdmi;
 205struct hdmi *hdmi_init(struct drm_device *dev, struct drm_encoder *encoder);
 206irqreturn_t hdmi_irq(int irq, void *dev_id);
 207void __init hdmi_register(void);
 208void __exit hdmi_unregister(void);
 209
 210#ifdef CONFIG_DEBUG_FS
 211void msm_gem_describe(struct drm_gem_object *obj, struct seq_file *m);
 212void msm_gem_describe_objects(struct list_head *list, struct seq_file *m);
 213void msm_framebuffer_describe(struct drm_framebuffer *fb, struct seq_file *m);
 214int msm_debugfs_late_init(struct drm_device *dev);
 215int msm_rd_debugfs_init(struct drm_minor *minor);
 216void msm_rd_debugfs_cleanup(struct drm_minor *minor);
 217void msm_rd_dump_submit(struct msm_gem_submit *submit);
 218int msm_perf_debugfs_init(struct drm_minor *minor);
 219void msm_perf_debugfs_cleanup(struct drm_minor *minor);
 220#else
 221static inline int msm_debugfs_late_init(struct drm_device *dev) { return 0; }
 222static inline void msm_rd_dump_submit(struct msm_gem_submit *submit) {}
 223#endif
 224
 225void __iomem *msm_ioremap(struct platform_device *pdev, const char *name,
 226                const char *dbgname);
 227void msm_writel(u32 data, void __iomem *addr);
 228u32 msm_readl(const void __iomem *addr);
 229
 230#define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__)
 231#define VERB(fmt, ...) if (0) DRM_DEBUG(fmt"\n", ##__VA_ARGS__)
 232
 233static inline bool fence_completed(struct drm_device *dev, uint32_t fence)
 234{
 235        struct msm_drm_private *priv = dev->dev_private;
 236        return priv->completed_fence >= fence;
 237}
 238
 239static inline int align_pitch(int width, int bpp)
 240{
 241        int bytespp = (bpp + 7) / 8;
 242        /* adreno needs pitch aligned to 32 pixels: */
 243        return bytespp * ALIGN(width, 32);
 244}
 245
 246/* for the generated headers: */
 247#define INVALID_IDX(idx) ({BUG(); 0;})
 248#define fui(x)                ({BUG(); 0;})
 249#define util_float_to_half(x) ({BUG(); 0;})
 250
 251
 252#define FIELD(val, name) (((val) & name ## __MASK) >> name ## __SHIFT)
 253
 254/* for conditionally setting boolean flag(s): */
 255#define COND(bool, val) ((bool) ? (val) : 0)
 256
 257
 258#endif /* __MSM_DRV_H__ */
 259