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15#include <linux/export.h>
16#include <linux/module.h>
17#include <linux/types.h>
18#include <linux/errno.h>
19#include <linux/io.h>
20#include <linux/err.h>
21#include <linux/platform_device.h>
22
23#include <video/imx-ipu-v3.h>
24#include "ipu-prv.h"
25
26struct ipu_di {
27 void __iomem *base;
28 int id;
29 u32 module;
30 struct clk *clk_di;
31 struct clk *clk_ipu;
32 struct clk *clk_di_pixel;
33 bool inuse;
34 struct ipu_soc *ipu;
35};
36
37static DEFINE_MUTEX(di_mutex);
38
39struct di_sync_config {
40 int run_count;
41 int run_src;
42 int offset_count;
43 int offset_src;
44 int repeat_count;
45 int cnt_clr_src;
46 int cnt_polarity_gen_en;
47 int cnt_polarity_clr_src;
48 int cnt_polarity_trigger_src;
49 int cnt_up;
50 int cnt_down;
51};
52
53enum di_pins {
54 DI_PIN11 = 0,
55 DI_PIN12 = 1,
56 DI_PIN13 = 2,
57 DI_PIN14 = 3,
58 DI_PIN15 = 4,
59 DI_PIN16 = 5,
60 DI_PIN17 = 6,
61 DI_PIN_CS = 7,
62
63 DI_PIN_SER_CLK = 0,
64 DI_PIN_SER_RS = 1,
65};
66
67enum di_sync_wave {
68 DI_SYNC_NONE = 0,
69 DI_SYNC_CLK = 1,
70 DI_SYNC_INT_HSYNC = 2,
71 DI_SYNC_HSYNC = 3,
72 DI_SYNC_VSYNC = 4,
73 DI_SYNC_DE = 6,
74};
75
76#define SYNC_WAVE 0
77
78#define DI_GENERAL 0x0000
79#define DI_BS_CLKGEN0 0x0004
80#define DI_BS_CLKGEN1 0x0008
81#define DI_SW_GEN0(gen) (0x000c + 4 * ((gen) - 1))
82#define DI_SW_GEN1(gen) (0x0030 + 4 * ((gen) - 1))
83#define DI_STP_REP(gen) (0x0148 + 4 * (((gen) - 1)/2))
84#define DI_SYNC_AS_GEN 0x0054
85#define DI_DW_GEN(gen) (0x0058 + 4 * (gen))
86#define DI_DW_SET(gen, set) (0x0088 + 4 * ((gen) + 0xc * (set)))
87#define DI_SER_CONF 0x015c
88#define DI_SSC 0x0160
89#define DI_POL 0x0164
90#define DI_AW0 0x0168
91#define DI_AW1 0x016c
92#define DI_SCR_CONF 0x0170
93#define DI_STAT 0x0174
94
95#define DI_SW_GEN0_RUN_COUNT(x) ((x) << 19)
96#define DI_SW_GEN0_RUN_SRC(x) ((x) << 16)
97#define DI_SW_GEN0_OFFSET_COUNT(x) ((x) << 3)
98#define DI_SW_GEN0_OFFSET_SRC(x) ((x) << 0)
99
100#define DI_SW_GEN1_CNT_POL_GEN_EN(x) ((x) << 29)
101#define DI_SW_GEN1_CNT_CLR_SRC(x) ((x) << 25)
102#define DI_SW_GEN1_CNT_POL_TRIGGER_SRC(x) ((x) << 12)
103#define DI_SW_GEN1_CNT_POL_CLR_SRC(x) ((x) << 9)
104#define DI_SW_GEN1_CNT_DOWN(x) ((x) << 16)
105#define DI_SW_GEN1_CNT_UP(x) (x)
106#define DI_SW_GEN1_AUTO_RELOAD (0x10000000)
107
108#define DI_DW_GEN_ACCESS_SIZE_OFFSET 24
109#define DI_DW_GEN_COMPONENT_SIZE_OFFSET 16
110
111#define DI_GEN_POLARITY_1 (1 << 0)
112#define DI_GEN_POLARITY_2 (1 << 1)
113#define DI_GEN_POLARITY_3 (1 << 2)
114#define DI_GEN_POLARITY_4 (1 << 3)
115#define DI_GEN_POLARITY_5 (1 << 4)
116#define DI_GEN_POLARITY_6 (1 << 5)
117#define DI_GEN_POLARITY_7 (1 << 6)
118#define DI_GEN_POLARITY_8 (1 << 7)
119#define DI_GEN_POLARITY_DISP_CLK (1 << 17)
120#define DI_GEN_DI_CLK_EXT (1 << 20)
121#define DI_GEN_DI_VSYNC_EXT (1 << 21)
122
123#define DI_POL_DRDY_DATA_POLARITY (1 << 7)
124#define DI_POL_DRDY_POLARITY_15 (1 << 4)
125
126#define DI_VSYNC_SEL_OFFSET 13
127
128static inline u32 ipu_di_read(struct ipu_di *di, unsigned offset)
129{
130 return readl(di->base + offset);
131}
132
133static inline void ipu_di_write(struct ipu_di *di, u32 value, unsigned offset)
134{
135 writel(value, di->base + offset);
136}
137
138static void ipu_di_data_wave_config(struct ipu_di *di,
139 int wave_gen,
140 int access_size, int component_size)
141{
142 u32 reg;
143 reg = (access_size << DI_DW_GEN_ACCESS_SIZE_OFFSET) |
144 (component_size << DI_DW_GEN_COMPONENT_SIZE_OFFSET);
145 ipu_di_write(di, reg, DI_DW_GEN(wave_gen));
146}
147
148static void ipu_di_data_pin_config(struct ipu_di *di, int wave_gen, int di_pin,
149 int set, int up, int down)
150{
151 u32 reg;
152
153 reg = ipu_di_read(di, DI_DW_GEN(wave_gen));
154 reg &= ~(0x3 << (di_pin * 2));
155 reg |= set << (di_pin * 2);
156 ipu_di_write(di, reg, DI_DW_GEN(wave_gen));
157
158 ipu_di_write(di, (down << 16) | up, DI_DW_SET(wave_gen, set));
159}
160
161static void ipu_di_sync_config(struct ipu_di *di, struct di_sync_config *config,
162 int start, int count)
163{
164 u32 reg;
165 int i;
166
167 for (i = 0; i < count; i++) {
168 struct di_sync_config *c = &config[i];
169 int wave_gen = start + i + 1;
170
171 if ((c->run_count >= 0x1000) || (c->offset_count >= 0x1000) ||
172 (c->repeat_count >= 0x1000) ||
173 (c->cnt_up >= 0x400) ||
174 (c->cnt_down >= 0x400)) {
175 dev_err(di->ipu->dev, "DI%d counters out of range.\n",
176 di->id);
177 return;
178 }
179
180 reg = DI_SW_GEN0_RUN_COUNT(c->run_count) |
181 DI_SW_GEN0_RUN_SRC(c->run_src) |
182 DI_SW_GEN0_OFFSET_COUNT(c->offset_count) |
183 DI_SW_GEN0_OFFSET_SRC(c->offset_src);
184 ipu_di_write(di, reg, DI_SW_GEN0(wave_gen));
185
186 reg = DI_SW_GEN1_CNT_POL_GEN_EN(c->cnt_polarity_gen_en) |
187 DI_SW_GEN1_CNT_CLR_SRC(c->cnt_clr_src) |
188 DI_SW_GEN1_CNT_POL_TRIGGER_SRC(
189 c->cnt_polarity_trigger_src) |
190 DI_SW_GEN1_CNT_POL_CLR_SRC(c->cnt_polarity_clr_src) |
191 DI_SW_GEN1_CNT_DOWN(c->cnt_down) |
192 DI_SW_GEN1_CNT_UP(c->cnt_up);
193
194
195 if (c->repeat_count == 0)
196 reg |= DI_SW_GEN1_AUTO_RELOAD;
197
198 ipu_di_write(di, reg, DI_SW_GEN1(wave_gen));
199
200 reg = ipu_di_read(di, DI_STP_REP(wave_gen));
201 reg &= ~(0xffff << (16 * ((wave_gen - 1) & 0x1)));
202 reg |= c->repeat_count << (16 * ((wave_gen - 1) & 0x1));
203 ipu_di_write(di, reg, DI_STP_REP(wave_gen));
204 }
205}
206
207static void ipu_di_sync_config_interlaced(struct ipu_di *di,
208 struct ipu_di_signal_cfg *sig)
209{
210 u32 h_total = sig->width + sig->h_sync_width +
211 sig->h_start_width + sig->h_end_width;
212 u32 v_total = sig->height + sig->v_sync_width +
213 sig->v_start_width + sig->v_end_width;
214 u32 reg;
215 struct di_sync_config cfg[] = {
216 {
217 .run_count = h_total / 2 - 1,
218 .run_src = DI_SYNC_CLK,
219 }, {
220 .run_count = h_total - 11,
221 .run_src = DI_SYNC_CLK,
222 .cnt_down = 4,
223 }, {
224 .run_count = v_total * 2 - 1,
225 .run_src = DI_SYNC_INT_HSYNC,
226 .offset_count = 1,
227 .offset_src = DI_SYNC_INT_HSYNC,
228 .cnt_down = 4,
229 }, {
230 .run_count = v_total / 2 - 1,
231 .run_src = DI_SYNC_HSYNC,
232 .offset_count = sig->v_start_width,
233 .offset_src = DI_SYNC_HSYNC,
234 .repeat_count = 2,
235 .cnt_clr_src = DI_SYNC_VSYNC,
236 }, {
237 .run_src = DI_SYNC_HSYNC,
238 .repeat_count = sig->height / 2,
239 .cnt_clr_src = 4,
240 }, {
241 .run_count = v_total - 1,
242 .run_src = DI_SYNC_HSYNC,
243 }, {
244 .run_count = v_total / 2 - 1,
245 .run_src = DI_SYNC_HSYNC,
246 .offset_count = 9,
247 .offset_src = DI_SYNC_HSYNC,
248 .repeat_count = 2,
249 .cnt_clr_src = DI_SYNC_VSYNC,
250 }, {
251 .run_src = DI_SYNC_CLK,
252 .offset_count = sig->h_start_width,
253 .offset_src = DI_SYNC_CLK,
254 .repeat_count = sig->width,
255 .cnt_clr_src = 5,
256 }, {
257 .run_count = v_total - 1,
258 .run_src = DI_SYNC_INT_HSYNC,
259 .offset_count = v_total / 2,
260 .offset_src = DI_SYNC_INT_HSYNC,
261 .cnt_clr_src = DI_SYNC_HSYNC,
262 .cnt_down = 4,
263 }
264 };
265
266 ipu_di_sync_config(di, cfg, 0, ARRAY_SIZE(cfg));
267
268
269 reg = ipu_di_read(di, DI_SW_GEN1(9));
270 reg &= 0x1FFFFFFF;
271 reg |= (3 - 1) << 29 | 0x00008000;
272 ipu_di_write(di, reg, DI_SW_GEN1(9));
273
274 ipu_di_write(di, v_total / 2 - 1, DI_SCR_CONF);
275}
276
277static void ipu_di_sync_config_noninterlaced(struct ipu_di *di,
278 struct ipu_di_signal_cfg *sig, int div)
279{
280 u32 h_total = sig->width + sig->h_sync_width + sig->h_start_width +
281 sig->h_end_width;
282 u32 v_total = sig->height + sig->v_sync_width + sig->v_start_width +
283 sig->v_end_width;
284 struct di_sync_config cfg[] = {
285 {
286
287 .run_count = h_total - 1,
288 .run_src = DI_SYNC_CLK,
289 } , {
290
291 .run_count = h_total - 1,
292 .run_src = DI_SYNC_CLK,
293 .offset_count = div * sig->v_to_h_sync,
294 .offset_src = DI_SYNC_CLK,
295 .cnt_polarity_gen_en = 1,
296 .cnt_polarity_trigger_src = DI_SYNC_CLK,
297 .cnt_down = sig->h_sync_width * 2,
298 } , {
299
300 .run_count = v_total - 1,
301 .run_src = DI_SYNC_INT_HSYNC,
302 .cnt_polarity_gen_en = 1,
303 .cnt_polarity_trigger_src = DI_SYNC_INT_HSYNC,
304 .cnt_down = sig->v_sync_width * 2,
305 } , {
306
307 .run_src = DI_SYNC_HSYNC,
308 .offset_count = sig->v_sync_width + sig->v_start_width,
309 .offset_src = DI_SYNC_HSYNC,
310 .repeat_count = sig->height,
311 .cnt_clr_src = DI_SYNC_VSYNC,
312 } , {
313
314 .run_src = DI_SYNC_CLK,
315 .offset_count = sig->h_sync_width + sig->h_start_width,
316 .offset_src = DI_SYNC_CLK,
317 .repeat_count = sig->width,
318 .cnt_clr_src = 5,
319 } , {
320
321 } , {
322
323 } , {
324
325 } , {
326
327 },
328 };
329
330 struct di_sync_config cfg_vga[] = {
331 {
332
333 .run_count = h_total - 1,
334 .run_src = DI_SYNC_CLK,
335 } , {
336
337 .run_count = v_total - 1,
338 .run_src = DI_SYNC_INT_HSYNC,
339 } , {
340
341 .run_src = DI_SYNC_INT_HSYNC,
342 .offset_count = sig->v_sync_width + sig->v_start_width,
343 .offset_src = DI_SYNC_INT_HSYNC,
344 .repeat_count = sig->height,
345 .cnt_clr_src = 3 ,
346 } , {
347
348 .run_count = h_total - 1,
349 .run_src = DI_SYNC_CLK,
350 .offset_count = div * sig->v_to_h_sync + 18,
351 .offset_src = DI_SYNC_CLK,
352 .cnt_polarity_gen_en = 1,
353 .cnt_polarity_trigger_src = DI_SYNC_CLK,
354 .cnt_down = sig->h_sync_width * 2,
355 } , {
356
357 .run_src = DI_SYNC_CLK,
358 .offset_count = sig->h_sync_width + sig->h_start_width,
359 .offset_src = DI_SYNC_CLK,
360 .repeat_count = sig->width,
361 .cnt_clr_src = 4,
362 } , {
363
364 .run_count = v_total - 1,
365 .run_src = DI_SYNC_INT_HSYNC,
366 .offset_count = 1,
367 .offset_src = DI_SYNC_INT_HSYNC,
368 .cnt_polarity_gen_en = 1,
369 .cnt_polarity_trigger_src = DI_SYNC_INT_HSYNC,
370 .cnt_down = sig->v_sync_width * 2,
371 } , {
372
373 .run_count = h_total - 1,
374 .run_src = DI_SYNC_CLK,
375 .offset_count = div * sig->v_to_h_sync + 18,
376 .offset_src = DI_SYNC_CLK,
377 .cnt_polarity_gen_en = 1,
378 .cnt_polarity_trigger_src = DI_SYNC_CLK,
379 .cnt_down = sig->h_sync_width * 2,
380 } , {
381
382 .run_count = v_total - 1,
383 .run_src = DI_SYNC_INT_HSYNC,
384 .offset_count = 1,
385 .offset_src = DI_SYNC_INT_HSYNC,
386 .cnt_polarity_gen_en = 1,
387 .cnt_polarity_trigger_src = DI_SYNC_INT_HSYNC,
388 .cnt_down = sig->v_sync_width * 2,
389 } , {
390
391 },
392 };
393
394 ipu_di_write(di, v_total - 1, DI_SCR_CONF);
395 if (sig->hsync_pin == 2 && sig->vsync_pin == 3)
396 ipu_di_sync_config(di, cfg, 0, ARRAY_SIZE(cfg));
397 else
398 ipu_di_sync_config(di, cfg_vga, 0, ARRAY_SIZE(cfg_vga));
399}
400
401static void ipu_di_config_clock(struct ipu_di *di,
402 const struct ipu_di_signal_cfg *sig)
403{
404 struct clk *clk;
405 unsigned clkgen0;
406 uint32_t val;
407
408 if (sig->clkflags & IPU_DI_CLKMODE_EXT) {
409
410
411
412
413
414 clk = di->clk_di;
415
416 if (sig->clkflags & IPU_DI_CLKMODE_SYNC) {
417
418
419
420
421
422
423
424 clkgen0 = 1 << 4;
425 } else {
426
427
428
429
430
431
432
433 unsigned long in_rate;
434 unsigned div;
435
436 clk_set_rate(clk, sig->pixelclock);
437
438 in_rate = clk_get_rate(clk);
439 div = (in_rate + sig->pixelclock / 2) / sig->pixelclock;
440 if (div == 0)
441 div = 1;
442
443 clkgen0 = div << 4;
444 }
445 } else {
446
447
448
449
450
451
452
453 unsigned long rate, clkrate;
454 unsigned div, error;
455
456 clkrate = clk_get_rate(di->clk_ipu);
457 div = (clkrate + sig->pixelclock / 2) / sig->pixelclock;
458 rate = clkrate / div;
459
460 error = rate / (sig->pixelclock / 1000);
461
462 dev_dbg(di->ipu->dev, " IPU clock can give %lu with divider %u, error %d.%u%%\n",
463 rate, div, (signed)(error - 1000) / 10, error % 10);
464
465
466 if (error < 1010 && error >= 990) {
467 clk = di->clk_ipu;
468
469 clkgen0 = div << 4;
470 } else {
471 unsigned long in_rate;
472 unsigned div;
473
474 clk = di->clk_di;
475
476 clk_set_rate(clk, sig->pixelclock);
477
478 in_rate = clk_get_rate(clk);
479 div = (in_rate + sig->pixelclock / 2) / sig->pixelclock;
480 if (div == 0)
481 div = 1;
482
483 clkgen0 = div << 4;
484 }
485 }
486
487 di->clk_di_pixel = clk;
488
489
490 ipu_di_write(di, clkgen0, DI_BS_CLKGEN0);
491
492
493
494
495
496
497
498 ipu_di_write(di, (clkgen0 >> 4) << 16, DI_BS_CLKGEN1);
499
500
501 val = ipu_di_read(di, DI_GENERAL) & ~DI_GEN_DI_CLK_EXT;
502 if (clk == di->clk_di)
503 val |= DI_GEN_DI_CLK_EXT;
504 ipu_di_write(di, val, DI_GENERAL);
505
506 dev_dbg(di->ipu->dev, "Want %luHz IPU %luHz DI %luHz using %s, %luHz\n",
507 sig->pixelclock,
508 clk_get_rate(di->clk_ipu),
509 clk_get_rate(di->clk_di),
510 clk == di->clk_di ? "DI" : "IPU",
511 clk_get_rate(di->clk_di_pixel) / (clkgen0 >> 4));
512}
513
514int ipu_di_init_sync_panel(struct ipu_di *di, struct ipu_di_signal_cfg *sig)
515{
516 u32 reg;
517 u32 di_gen, vsync_cnt;
518 u32 div;
519 u32 h_total, v_total;
520
521 dev_dbg(di->ipu->dev, "disp %d: panel size = %d x %d\n",
522 di->id, sig->width, sig->height);
523
524 if ((sig->v_sync_width == 0) || (sig->h_sync_width == 0))
525 return -EINVAL;
526
527 h_total = sig->width + sig->h_sync_width + sig->h_start_width +
528 sig->h_end_width;
529 v_total = sig->height + sig->v_sync_width + sig->v_start_width +
530 sig->v_end_width;
531
532 dev_dbg(di->ipu->dev, "Clocks: IPU %luHz DI %luHz Needed %luHz\n",
533 clk_get_rate(di->clk_ipu),
534 clk_get_rate(di->clk_di),
535 sig->pixelclock);
536
537 mutex_lock(&di_mutex);
538
539 ipu_di_config_clock(di, sig);
540
541 div = ipu_di_read(di, DI_BS_CLKGEN0) & 0xfff;
542 div = div / 16;
543
544
545
546 ipu_di_write(di, (div << 16), DI_BS_CLKGEN1);
547
548 ipu_di_data_wave_config(di, SYNC_WAVE, div - 1, div - 1);
549 ipu_di_data_pin_config(di, SYNC_WAVE, DI_PIN15, 3, 0, div * 2);
550
551 di_gen = ipu_di_read(di, DI_GENERAL) & DI_GEN_DI_CLK_EXT;
552 di_gen |= DI_GEN_DI_VSYNC_EXT;
553
554 if (sig->interlaced) {
555 ipu_di_sync_config_interlaced(di, sig);
556
557
558 di_gen |= 0x10000000;
559 di_gen |= DI_GEN_POLARITY_5;
560 di_gen |= DI_GEN_POLARITY_8;
561
562 vsync_cnt = 7;
563
564 if (sig->Hsync_pol)
565 di_gen |= DI_GEN_POLARITY_3;
566 if (sig->Vsync_pol)
567 di_gen |= DI_GEN_POLARITY_2;
568 } else {
569 ipu_di_sync_config_noninterlaced(di, sig, div);
570
571 vsync_cnt = 3;
572 if (di->id == 1)
573
574
575
576
577 if (!(sig->hsync_pin == 2 && sig->vsync_pin == 3))
578 vsync_cnt = 6;
579
580 if (sig->Hsync_pol) {
581 if (sig->hsync_pin == 2)
582 di_gen |= DI_GEN_POLARITY_2;
583 else if (sig->hsync_pin == 4)
584 di_gen |= DI_GEN_POLARITY_4;
585 else if (sig->hsync_pin == 7)
586 di_gen |= DI_GEN_POLARITY_7;
587 }
588 if (sig->Vsync_pol) {
589 if (sig->vsync_pin == 3)
590 di_gen |= DI_GEN_POLARITY_3;
591 else if (sig->vsync_pin == 6)
592 di_gen |= DI_GEN_POLARITY_6;
593 else if (sig->vsync_pin == 8)
594 di_gen |= DI_GEN_POLARITY_8;
595 }
596 }
597
598 if (sig->clk_pol)
599 di_gen |= DI_GEN_POLARITY_DISP_CLK;
600
601 ipu_di_write(di, di_gen, DI_GENERAL);
602
603 ipu_di_write(di, (--vsync_cnt << DI_VSYNC_SEL_OFFSET) | 0x00000002,
604 DI_SYNC_AS_GEN);
605
606 reg = ipu_di_read(di, DI_POL);
607 reg &= ~(DI_POL_DRDY_DATA_POLARITY | DI_POL_DRDY_POLARITY_15);
608
609 if (sig->enable_pol)
610 reg |= DI_POL_DRDY_POLARITY_15;
611 if (sig->data_pol)
612 reg |= DI_POL_DRDY_DATA_POLARITY;
613
614 ipu_di_write(di, reg, DI_POL);
615
616 mutex_unlock(&di_mutex);
617
618 return 0;
619}
620EXPORT_SYMBOL_GPL(ipu_di_init_sync_panel);
621
622int ipu_di_enable(struct ipu_di *di)
623{
624 int ret;
625
626 WARN_ON(IS_ERR(di->clk_di_pixel));
627
628 ret = clk_prepare_enable(di->clk_di_pixel);
629 if (ret)
630 return ret;
631
632 ipu_module_enable(di->ipu, di->module);
633
634 return 0;
635}
636EXPORT_SYMBOL_GPL(ipu_di_enable);
637
638int ipu_di_disable(struct ipu_di *di)
639{
640 WARN_ON(IS_ERR(di->clk_di_pixel));
641
642 ipu_module_disable(di->ipu, di->module);
643
644 clk_disable_unprepare(di->clk_di_pixel);
645
646 return 0;
647}
648EXPORT_SYMBOL_GPL(ipu_di_disable);
649
650int ipu_di_get_num(struct ipu_di *di)
651{
652 return di->id;
653}
654EXPORT_SYMBOL_GPL(ipu_di_get_num);
655
656static DEFINE_MUTEX(ipu_di_lock);
657
658struct ipu_di *ipu_di_get(struct ipu_soc *ipu, int disp)
659{
660 struct ipu_di *di;
661
662 if (disp > 1)
663 return ERR_PTR(-EINVAL);
664
665 di = ipu->di_priv[disp];
666
667 mutex_lock(&ipu_di_lock);
668
669 if (di->inuse) {
670 di = ERR_PTR(-EBUSY);
671 goto out;
672 }
673
674 di->inuse = true;
675out:
676 mutex_unlock(&ipu_di_lock);
677
678 return di;
679}
680EXPORT_SYMBOL_GPL(ipu_di_get);
681
682void ipu_di_put(struct ipu_di *di)
683{
684 mutex_lock(&ipu_di_lock);
685
686 di->inuse = false;
687
688 mutex_unlock(&ipu_di_lock);
689}
690EXPORT_SYMBOL_GPL(ipu_di_put);
691
692int ipu_di_init(struct ipu_soc *ipu, struct device *dev, int id,
693 unsigned long base,
694 u32 module, struct clk *clk_ipu)
695{
696 struct ipu_di *di;
697
698 if (id > 1)
699 return -ENODEV;
700
701 di = devm_kzalloc(dev, sizeof(*di), GFP_KERNEL);
702 if (!di)
703 return -ENOMEM;
704
705 ipu->di_priv[id] = di;
706
707 di->clk_di = devm_clk_get(dev, id ? "di1" : "di0");
708 if (IS_ERR(di->clk_di))
709 return PTR_ERR(di->clk_di);
710
711 di->module = module;
712 di->id = id;
713 di->clk_ipu = clk_ipu;
714 di->base = devm_ioremap(dev, base, PAGE_SIZE);
715 if (!di->base)
716 return -ENOMEM;
717
718 ipu_di_write(di, 0x10, DI_BS_CLKGEN0);
719
720 dev_dbg(dev, "DI%d base: 0x%08lx remapped to %p\n",
721 id, base, di->base);
722 di->inuse = false;
723 di->ipu = ipu;
724
725 return 0;
726}
727
728void ipu_di_exit(struct ipu_soc *ipu, int id)
729{
730}
731