1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39#include <linux/pci.h>
40#include <linux/delay.h>
41#include <linux/module.h>
42#include <linux/firmware.h>
43
44#include "qib.h"
45#include "qib_7220.h"
46
47#define SD7220_FW_NAME "qlogic/sd7220.fw"
48MODULE_FIRMWARE(SD7220_FW_NAME);
49
50
51
52
53
54
55#define KREG_IDX(regname) (QIB_7220_##regname##_OFFS / sizeof(u64))
56#define kr_hwerrclear KREG_IDX(HwErrClear)
57#define kr_hwerrmask KREG_IDX(HwErrMask)
58#define kr_hwerrstatus KREG_IDX(HwErrStatus)
59#define kr_ibcstatus KREG_IDX(IBCStatus)
60#define kr_ibserdesctrl KREG_IDX(IBSerDesCtrl)
61#define kr_scratch KREG_IDX(Scratch)
62#define kr_xgxs_cfg KREG_IDX(XGXSCfg)
63
64#define kr_ibsd_epb_access_ctrl KREG_IDX(ibsd_epb_access_ctrl)
65#define kr_ibsd_epb_transaction_reg KREG_IDX(ibsd_epb_transaction_reg)
66#define kr_pciesd_epb_transaction_reg KREG_IDX(pciesd_epb_transaction_reg)
67#define kr_pciesd_epb_access_ctrl KREG_IDX(pciesd_epb_access_ctrl)
68#define kr_serdes_ddsrxeq0 KREG_IDX(SerDes_DDSRXEQ0)
69
70
71
72
73
74#define kr_serdes_maptable KREG_IDX(IBSerDesMappTable)
75
76
77
78
79
80#define PCIE_SERDES0 0
81#define PCIE_SERDES1 1
82
83
84
85
86
87#define EPB_ADDR_SHF 8
88#define EPB_LOC(chn, elt, reg) \
89 (((elt & 0xf) | ((chn & 7) << 4) | ((reg & 0x3f) << 9)) << \
90 EPB_ADDR_SHF)
91#define EPB_IB_QUAD0_CS_SHF (25)
92#define EPB_IB_QUAD0_CS (1U << EPB_IB_QUAD0_CS_SHF)
93#define EPB_IB_UC_CS_SHF (26)
94#define EPB_PCIE_UC_CS_SHF (27)
95#define EPB_GLOBAL_WR (1U << (EPB_ADDR_SHF + 8))
96
97
98static int qib_sd7220_reg_mod(struct qib_devdata *dd, int sdnum, u32 loc,
99 u32 data, u32 mask);
100static int ibsd_mod_allchnls(struct qib_devdata *dd, int loc, int val,
101 int mask);
102static int qib_sd_trimdone_poll(struct qib_devdata *dd);
103static void qib_sd_trimdone_monitor(struct qib_devdata *dd, const char *where);
104static int qib_sd_setvals(struct qib_devdata *dd);
105static int qib_sd_early(struct qib_devdata *dd);
106static int qib_sd_dactrim(struct qib_devdata *dd);
107static int qib_internal_presets(struct qib_devdata *dd);
108
109static int qib_sd_trimself(struct qib_devdata *dd, int val);
110static int epb_access(struct qib_devdata *dd, int sdnum, int claim);
111static int qib_sd7220_ib_load(struct qib_devdata *dd,
112 const struct firmware *fw);
113static int qib_sd7220_ib_vfy(struct qib_devdata *dd,
114 const struct firmware *fw);
115
116
117
118
119
120
121
122
123static int qib_ibsd_ucode_loaded(struct qib_pportdata *ppd,
124 const struct firmware *fw)
125{
126 struct qib_devdata *dd = ppd->dd;
127
128 if (!dd->cspec->serdes_first_init_done &&
129 qib_sd7220_ib_vfy(dd, fw) > 0)
130 dd->cspec->serdes_first_init_done = 1;
131 return dd->cspec->serdes_first_init_done;
132}
133
134
135#define QLOGIC_IB_HWE_IB_UC_MEMORYPARITYERR 0x0000004000000000ULL
136#define IB_MPREG5 (EPB_LOC(6, 0, 0xE) | (1L << EPB_IB_UC_CS_SHF))
137#define IB_MPREG6 (EPB_LOC(6, 0, 0xF) | (1U << EPB_IB_UC_CS_SHF))
138#define UC_PAR_CLR_D 8
139#define UC_PAR_CLR_M 0xC
140#define IB_CTRL2(chn) (EPB_LOC(chn, 7, 3) | EPB_IB_QUAD0_CS)
141#define START_EQ1(chan) EPB_LOC(chan, 7, 0x27)
142
143void qib_sd7220_clr_ibpar(struct qib_devdata *dd)
144{
145 int ret;
146
147
148 ret = qib_sd7220_reg_mod(dd, IB_7220_SERDES, IB_MPREG6,
149 UC_PAR_CLR_D, UC_PAR_CLR_M);
150 if (ret < 0) {
151 qib_dev_err(dd, "Failed clearing IBSerDes Parity err\n");
152 goto bail;
153 }
154 ret = qib_sd7220_reg_mod(dd, IB_7220_SERDES, IB_MPREG6, 0,
155 UC_PAR_CLR_M);
156
157 qib_read_kreg32(dd, kr_scratch);
158 udelay(4);
159 qib_write_kreg(dd, kr_hwerrclear,
160 QLOGIC_IB_HWE_IB_UC_MEMORYPARITYERR);
161 qib_read_kreg32(dd, kr_scratch);
162bail:
163 return;
164}
165
166
167
168
169
170
171#define IBSD_RESYNC_TRIES 3
172#define IB_PGUDP(chn) (EPB_LOC((chn), 2, 1) | EPB_IB_QUAD0_CS)
173#define IB_CMUDONE(chn) (EPB_LOC((chn), 7, 0xF) | EPB_IB_QUAD0_CS)
174
175static int qib_resync_ibepb(struct qib_devdata *dd)
176{
177 int ret, pat, tries, chn;
178 u32 loc;
179
180 ret = -1;
181 chn = 0;
182 for (tries = 0; tries < (4 * IBSD_RESYNC_TRIES); ++tries) {
183 loc = IB_PGUDP(chn);
184 ret = qib_sd7220_reg_mod(dd, IB_7220_SERDES, loc, 0, 0);
185 if (ret < 0) {
186 qib_dev_err(dd, "Failed read in resync\n");
187 continue;
188 }
189 if (ret != 0xF0 && ret != 0x55 && tries == 0)
190 qib_dev_err(dd, "unexpected pattern in resync\n");
191 pat = ret ^ 0xA5;
192 ret = qib_sd7220_reg_mod(dd, IB_7220_SERDES, loc, pat, 0xFF);
193 if (ret < 0) {
194 qib_dev_err(dd, "Failed write in resync\n");
195 continue;
196 }
197 ret = qib_sd7220_reg_mod(dd, IB_7220_SERDES, loc, 0, 0);
198 if (ret < 0) {
199 qib_dev_err(dd, "Failed re-read in resync\n");
200 continue;
201 }
202 if (ret != pat) {
203 qib_dev_err(dd, "Failed compare1 in resync\n");
204 continue;
205 }
206 loc = IB_CMUDONE(chn);
207 ret = qib_sd7220_reg_mod(dd, IB_7220_SERDES, loc, 0, 0);
208 if (ret < 0) {
209 qib_dev_err(dd, "Failed CMUDONE rd in resync\n");
210 continue;
211 }
212 if ((ret & 0x70) != ((chn << 4) | 0x40)) {
213 qib_dev_err(dd, "Bad CMUDONE value %02X, chn %d\n",
214 ret, chn);
215 continue;
216 }
217 if (++chn == 4)
218 break;
219 }
220 return (ret > 0) ? 0 : ret;
221}
222
223
224
225
226
227static int qib_ibsd_reset(struct qib_devdata *dd, int assert_rst)
228{
229 u64 rst_val;
230 int ret = 0;
231 unsigned long flags;
232
233 rst_val = qib_read_kreg64(dd, kr_ibserdesctrl);
234 if (assert_rst) {
235
236
237
238
239 spin_lock_irqsave(&dd->cspec->sdepb_lock, flags);
240 epb_access(dd, IB_7220_SERDES, 1);
241 rst_val |= 1ULL;
242
243 qib_write_kreg(dd, kr_hwerrmask,
244 dd->cspec->hwerrmask &
245 ~QLOGIC_IB_HWE_IB_UC_MEMORYPARITYERR);
246 qib_write_kreg(dd, kr_ibserdesctrl, rst_val);
247
248 qib_read_kreg32(dd, kr_scratch);
249 udelay(2);
250
251 epb_access(dd, IB_7220_SERDES, -1);
252 spin_unlock_irqrestore(&dd->cspec->sdepb_lock, flags);
253 } else {
254
255
256
257
258
259
260
261 u64 val;
262 rst_val &= ~(1ULL);
263 qib_write_kreg(dd, kr_hwerrmask,
264 dd->cspec->hwerrmask &
265 ~QLOGIC_IB_HWE_IB_UC_MEMORYPARITYERR);
266
267 ret = qib_resync_ibepb(dd);
268 if (ret < 0)
269 qib_dev_err(dd, "unable to re-sync IB EPB\n");
270
271
272 ret = qib_sd7220_reg_mod(dd, IB_7220_SERDES, IB_MPREG5, 1, 1);
273 if (ret < 0)
274 goto bail;
275
276 ret = qib_sd7220_reg_mod(dd, IB_7220_SERDES, IB_MPREG6, 0x80,
277 0x80);
278 if (ret < 0) {
279 qib_dev_err(dd, "Failed to set WDOG disable\n");
280 goto bail;
281 }
282 qib_write_kreg(dd, kr_ibserdesctrl, rst_val);
283
284 qib_read_kreg32(dd, kr_scratch);
285 udelay(1);
286
287 qib_sd7220_clr_ibpar(dd);
288 val = qib_read_kreg64(dd, kr_hwerrstatus);
289 if (val & QLOGIC_IB_HWE_IB_UC_MEMORYPARITYERR) {
290 qib_dev_err(dd, "IBUC Parity still set after RST\n");
291 dd->cspec->hwerrmask &=
292 ~QLOGIC_IB_HWE_IB_UC_MEMORYPARITYERR;
293 }
294 qib_write_kreg(dd, kr_hwerrmask,
295 dd->cspec->hwerrmask);
296 }
297
298bail:
299 return ret;
300}
301
302static void qib_sd_trimdone_monitor(struct qib_devdata *dd,
303 const char *where)
304{
305 int ret, chn, baduns;
306 u64 val;
307
308 if (!where)
309 where = "?";
310
311
312 udelay(2);
313
314 ret = qib_resync_ibepb(dd);
315 if (ret < 0)
316 qib_dev_err(dd, "not able to re-sync IB EPB (%s)\n", where);
317
318
319 ret = qib_sd7220_reg_mod(dd, IB_7220_SERDES, IB_CTRL2(0), 0, 0);
320 if (ret < 0)
321 qib_dev_err(dd, "Failed TRIMDONE 1st read, (%s)\n", where);
322
323
324 val = qib_read_kreg64(dd, kr_ibcstatus);
325 if (!(val & (1ULL << 11)))
326 qib_dev_err(dd, "IBCS TRIMDONE clear (%s)\n", where);
327
328
329
330
331 udelay(2);
332
333 ret = qib_sd7220_reg_mod(dd, IB_7220_SERDES, IB_MPREG6, 0x80, 0x80);
334 if (ret < 0)
335 qib_dev_err(dd, "Failed Dummy RMW, (%s)\n", where);
336 udelay(10);
337
338 baduns = 0;
339
340 for (chn = 3; chn >= 0; --chn) {
341
342 ret = qib_sd7220_reg_mod(dd, IB_7220_SERDES,
343 IB_CTRL2(chn), 0, 0);
344 if (ret < 0)
345 qib_dev_err(dd,
346 "Failed checking TRIMDONE, chn %d (%s)\n",
347 chn, where);
348
349 if (!(ret & 0x10)) {
350 int probe;
351
352 baduns |= (1 << chn);
353 qib_dev_err(dd,
354 "TRIMDONE cleared on chn %d (%02X). (%s)\n",
355 chn, ret, where);
356 probe = qib_sd7220_reg_mod(dd, IB_7220_SERDES,
357 IB_PGUDP(0), 0, 0);
358 qib_dev_err(dd, "probe is %d (%02X)\n",
359 probe, probe);
360 probe = qib_sd7220_reg_mod(dd, IB_7220_SERDES,
361 IB_CTRL2(chn), 0, 0);
362 qib_dev_err(dd, "re-read: %d (%02X)\n",
363 probe, probe);
364 ret = qib_sd7220_reg_mod(dd, IB_7220_SERDES,
365 IB_CTRL2(chn), 0x10, 0x10);
366 if (ret < 0)
367 qib_dev_err(dd,
368 "Err on TRIMDONE rewrite1\n");
369 }
370 }
371 for (chn = 3; chn >= 0; --chn) {
372
373 if (baduns & (1 << chn)) {
374 qib_dev_err(dd,
375 "Resetting TRIMDONE on chn %d (%s)\n",
376 chn, where);
377 ret = qib_sd7220_reg_mod(dd, IB_7220_SERDES,
378 IB_CTRL2(chn), 0x10, 0x10);
379 if (ret < 0)
380 qib_dev_err(dd,
381 "Failed re-setting TRIMDONE, chn %d (%s)\n",
382 chn, where);
383 }
384 }
385}
386
387
388
389
390
391
392
393int qib_sd7220_init(struct qib_devdata *dd)
394{
395 const struct firmware *fw;
396 int ret = 1;
397 int first_reset, was_reset;
398
399
400 was_reset = (qib_read_kreg64(dd, kr_ibserdesctrl) & 1);
401 if (!was_reset) {
402
403 qib_ibsd_reset(dd, 1);
404 qib_sd_trimdone_monitor(dd, "Driver-reload");
405 }
406
407 ret = request_firmware(&fw, SD7220_FW_NAME, &dd->pcidev->dev);
408 if (ret) {
409 qib_dev_err(dd, "Failed to load IB SERDES image\n");
410 goto done;
411 }
412
413
414 ret = qib_ibsd_ucode_loaded(dd->pport, fw);
415 if (ret < 0)
416 goto bail;
417
418 first_reset = !ret;
419
420
421
422
423 ret = qib_sd_early(dd);
424 if (ret < 0) {
425 qib_dev_err(dd, "Failed to set IB SERDES early defaults\n");
426 goto bail;
427 }
428
429
430
431
432
433 if (first_reset) {
434 ret = qib_sd_dactrim(dd);
435 if (ret < 0) {
436 qib_dev_err(dd, "Failed IB SERDES DAC trim\n");
437 goto bail;
438 }
439 }
440
441
442
443
444
445
446 ret = qib_internal_presets(dd);
447 if (ret < 0) {
448 qib_dev_err(dd, "Failed to set IB SERDES presets\n");
449 goto bail;
450 }
451 ret = qib_sd_trimself(dd, 0x80);
452 if (ret < 0) {
453 qib_dev_err(dd, "Failed to set IB SERDES TRIMSELF\n");
454 goto bail;
455 }
456
457
458 ret = 0;
459 if (first_reset) {
460 int vfy;
461 int trim_done;
462
463 ret = qib_sd7220_ib_load(dd, fw);
464 if (ret < 0) {
465 qib_dev_err(dd, "Failed to load IB SERDES image\n");
466 goto bail;
467 } else {
468
469 vfy = qib_sd7220_ib_vfy(dd, fw);
470 if (vfy != ret) {
471 qib_dev_err(dd, "SERDES PRAM VFY failed\n");
472 goto bail;
473 }
474 }
475
476
477
478
479
480 ret = 0;
481
482
483
484
485
486
487
488
489 ret = ibsd_mod_allchnls(dd, START_EQ1(0), 0, 0x38);
490 if (ret < 0) {
491 qib_dev_err(dd, "Failed clearing START_EQ1\n");
492 goto bail;
493 }
494
495 qib_ibsd_reset(dd, 0);
496
497
498
499
500 trim_done = qib_sd_trimdone_poll(dd);
501
502
503
504
505
506 qib_ibsd_reset(dd, 1);
507
508 if (!trim_done) {
509 qib_dev_err(dd, "No TRIMDONE seen\n");
510 goto bail;
511 }
512
513
514
515
516 qib_sd_trimdone_monitor(dd, "First-reset");
517
518 dd->cspec->serdes_first_init_done = 1;
519 }
520
521
522
523
524 ret = 0;
525 if (qib_sd_setvals(dd) >= 0)
526 goto done;
527bail:
528 ret = 1;
529done:
530
531 set_7220_relock_poll(dd, -1);
532
533 release_firmware(fw);
534 return ret;
535}
536
537#define EPB_ACC_REQ 1
538#define EPB_ACC_GNT 0x100
539#define EPB_DATA_MASK 0xFF
540#define EPB_RD (1ULL << 24)
541#define EPB_TRANS_RDY (1ULL << 31)
542#define EPB_TRANS_ERR (1ULL << 30)
543#define EPB_TRANS_TRIES 5
544
545
546
547
548
549
550
551static int epb_access(struct qib_devdata *dd, int sdnum, int claim)
552{
553 u16 acc;
554 u64 accval;
555 int owned = 0;
556 u64 oct_sel = 0;
557
558 switch (sdnum) {
559 case IB_7220_SERDES:
560
561
562
563
564 acc = kr_ibsd_epb_access_ctrl;
565 break;
566
567 case PCIE_SERDES0:
568 case PCIE_SERDES1:
569
570 acc = kr_pciesd_epb_access_ctrl;
571 oct_sel = (2 << (sdnum - PCIE_SERDES0));
572 break;
573
574 default:
575 return 0;
576 }
577
578
579 qib_read_kreg32(dd, kr_scratch);
580 udelay(15);
581
582 accval = qib_read_kreg32(dd, acc);
583
584 owned = !!(accval & EPB_ACC_GNT);
585 if (claim < 0) {
586
587 u64 pollval;
588
589
590
591
592 u64 newval = 0;
593 qib_write_kreg(dd, acc, newval);
594
595 pollval = qib_read_kreg32(dd, acc);
596 udelay(5);
597 pollval = qib_read_kreg32(dd, acc);
598 if (pollval & EPB_ACC_GNT)
599 owned = -1;
600 } else if (claim > 0) {
601
602 u64 pollval;
603 u64 newval = EPB_ACC_REQ | oct_sel;
604 qib_write_kreg(dd, acc, newval);
605
606 pollval = qib_read_kreg32(dd, acc);
607 udelay(5);
608 pollval = qib_read_kreg32(dd, acc);
609 if (!(pollval & EPB_ACC_GNT))
610 owned = -1;
611 }
612 return owned;
613}
614
615
616
617
618static int epb_trans(struct qib_devdata *dd, u16 reg, u64 i_val, u64 *o_vp)
619{
620 int tries;
621 u64 transval;
622
623 qib_write_kreg(dd, reg, i_val);
624
625 transval = qib_read_kreg64(dd, reg);
626
627 for (tries = EPB_TRANS_TRIES; tries; --tries) {
628 transval = qib_read_kreg32(dd, reg);
629 if (transval & EPB_TRANS_RDY)
630 break;
631 udelay(5);
632 }
633 if (transval & EPB_TRANS_ERR)
634 return -1;
635 if (tries > 0 && o_vp)
636 *o_vp = transval;
637 return tries;
638}
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653static int qib_sd7220_reg_mod(struct qib_devdata *dd, int sdnum, u32 loc,
654 u32 wd, u32 mask)
655{
656 u16 trans;
657 u64 transval;
658 int owned;
659 int tries, ret;
660 unsigned long flags;
661
662 switch (sdnum) {
663 case IB_7220_SERDES:
664 trans = kr_ibsd_epb_transaction_reg;
665 break;
666
667 case PCIE_SERDES0:
668 case PCIE_SERDES1:
669 trans = kr_pciesd_epb_transaction_reg;
670 break;
671
672 default:
673 return -1;
674 }
675
676
677
678
679
680 spin_lock_irqsave(&dd->cspec->sdepb_lock, flags);
681
682 owned = epb_access(dd, sdnum, 1);
683 if (owned < 0) {
684 spin_unlock_irqrestore(&dd->cspec->sdepb_lock, flags);
685 return -1;
686 }
687 ret = 0;
688 for (tries = EPB_TRANS_TRIES; tries; --tries) {
689 transval = qib_read_kreg32(dd, trans);
690 if (transval & EPB_TRANS_RDY)
691 break;
692 udelay(5);
693 }
694
695 if (tries > 0) {
696 tries = 1;
697 if (mask != 0xFF) {
698
699
700
701
702 transval = loc | EPB_RD;
703 tries = epb_trans(dd, trans, transval, &transval);
704 }
705 if (tries > 0 && mask != 0) {
706
707
708
709 wd = (wd & mask) | (transval & ~mask);
710 transval = loc | (wd & EPB_DATA_MASK);
711 tries = epb_trans(dd, trans, transval, &transval);
712 }
713 }
714
715
716
717
718
719 if (epb_access(dd, sdnum, -1) < 0)
720 ret = -1;
721 else
722 ret = transval & EPB_DATA_MASK;
723
724 spin_unlock_irqrestore(&dd->cspec->sdepb_lock, flags);
725 if (tries <= 0)
726 ret = -1;
727 return ret;
728}
729
730#define EPB_ROM_R (2)
731#define EPB_ROM_W (1)
732
733
734
735
736#define EPB_UC_CTL EPB_LOC(6, 0, 0)
737#define EPB_MADDRL EPB_LOC(6, 0, 2)
738#define EPB_MADDRH EPB_LOC(6, 0, 3)
739#define EPB_ROMDATA EPB_LOC(6, 0, 4)
740#define EPB_RAMDATA EPB_LOC(6, 0, 5)
741
742
743static int qib_sd7220_ram_xfer(struct qib_devdata *dd, int sdnum, u32 loc,
744 u8 *buf, int cnt, int rd_notwr)
745{
746 u16 trans;
747 u64 transval;
748 u64 csbit;
749 int owned;
750 int tries;
751 int sofar;
752 int addr;
753 int ret;
754 unsigned long flags;
755 const char *op;
756
757
758 switch (sdnum) {
759 case IB_7220_SERDES:
760 csbit = 1ULL << EPB_IB_UC_CS_SHF;
761 trans = kr_ibsd_epb_transaction_reg;
762 break;
763
764 case PCIE_SERDES0:
765 case PCIE_SERDES1:
766
767 csbit = 1ULL << EPB_PCIE_UC_CS_SHF;
768 trans = kr_pciesd_epb_transaction_reg;
769 break;
770
771 default:
772 return -1;
773 }
774
775 op = rd_notwr ? "Rd" : "Wr";
776 spin_lock_irqsave(&dd->cspec->sdepb_lock, flags);
777
778 owned = epb_access(dd, sdnum, 1);
779 if (owned < 0) {
780 spin_unlock_irqrestore(&dd->cspec->sdepb_lock, flags);
781 return -1;
782 }
783
784
785
786
787
788
789
790
791 addr = loc & 0x1FFF;
792 for (tries = EPB_TRANS_TRIES; tries; --tries) {
793 transval = qib_read_kreg32(dd, trans);
794 if (transval & EPB_TRANS_RDY)
795 break;
796 udelay(5);
797 }
798
799 sofar = 0;
800 if (tries > 0) {
801
802
803
804
805
806
807
808 transval = csbit | EPB_UC_CTL |
809 (rd_notwr ? EPB_ROM_R : EPB_ROM_W);
810 tries = epb_trans(dd, trans, transval, &transval);
811 while (tries > 0 && sofar < cnt) {
812 if (!sofar) {
813
814 int addrbyte = (addr + sofar) >> 8;
815 transval = csbit | EPB_MADDRH | addrbyte;
816 tries = epb_trans(dd, trans, transval,
817 &transval);
818 if (tries <= 0)
819 break;
820 addrbyte = (addr + sofar) & 0xFF;
821 transval = csbit | EPB_MADDRL | addrbyte;
822 tries = epb_trans(dd, trans, transval,
823 &transval);
824 if (tries <= 0)
825 break;
826 }
827
828 if (rd_notwr)
829 transval = csbit | EPB_ROMDATA | EPB_RD;
830 else
831 transval = csbit | EPB_ROMDATA | buf[sofar];
832 tries = epb_trans(dd, trans, transval, &transval);
833 if (tries <= 0)
834 break;
835 if (rd_notwr)
836 buf[sofar] = transval & EPB_DATA_MASK;
837 ++sofar;
838 }
839
840 transval = csbit | EPB_UC_CTL;
841 tries = epb_trans(dd, trans, transval, &transval);
842 }
843
844 ret = sofar;
845
846 if (epb_access(dd, sdnum, -1) < 0)
847 ret = -1;
848
849 spin_unlock_irqrestore(&dd->cspec->sdepb_lock, flags);
850 if (tries <= 0)
851 ret = -1;
852 return ret;
853}
854
855#define PROG_CHUNK 64
856
857static int qib_sd7220_prog_ld(struct qib_devdata *dd, int sdnum,
858 const u8 *img, int len, int offset)
859{
860 int cnt, sofar, req;
861
862 sofar = 0;
863 while (sofar < len) {
864 req = len - sofar;
865 if (req > PROG_CHUNK)
866 req = PROG_CHUNK;
867 cnt = qib_sd7220_ram_xfer(dd, sdnum, offset + sofar,
868 (u8 *)img + sofar, req, 0);
869 if (cnt < req) {
870 sofar = -1;
871 break;
872 }
873 sofar += req;
874 }
875 return sofar;
876}
877
878#define VFY_CHUNK 64
879#define SD_PRAM_ERROR_LIMIT 42
880
881static int qib_sd7220_prog_vfy(struct qib_devdata *dd, int sdnum,
882 const u8 *img, int len, int offset)
883{
884 int cnt, sofar, req, idx, errors;
885 unsigned char readback[VFY_CHUNK];
886
887 errors = 0;
888 sofar = 0;
889 while (sofar < len) {
890 req = len - sofar;
891 if (req > VFY_CHUNK)
892 req = VFY_CHUNK;
893 cnt = qib_sd7220_ram_xfer(dd, sdnum, sofar + offset,
894 readback, req, 1);
895 if (cnt < req) {
896
897 sofar = -1;
898 break;
899 }
900 for (idx = 0; idx < cnt; ++idx) {
901 if (readback[idx] != img[idx+sofar])
902 ++errors;
903 }
904 sofar += cnt;
905 }
906 return errors ? -errors : sofar;
907}
908
909static int
910qib_sd7220_ib_load(struct qib_devdata *dd, const struct firmware *fw)
911{
912 return qib_sd7220_prog_ld(dd, IB_7220_SERDES, fw->data, fw->size, 0);
913}
914
915static int
916qib_sd7220_ib_vfy(struct qib_devdata *dd, const struct firmware *fw)
917{
918 return qib_sd7220_prog_vfy(dd, IB_7220_SERDES, fw->data, fw->size, 0);
919}
920
921
922
923
924#define IB_SERDES_TRIM_DONE (1ULL << 11)
925#define TRIM_TMO (30)
926
927static int qib_sd_trimdone_poll(struct qib_devdata *dd)
928{
929 int trim_tmo, ret;
930 uint64_t val;
931
932
933
934
935
936 ret = 0;
937 for (trim_tmo = 0; trim_tmo < TRIM_TMO; ++trim_tmo) {
938 val = qib_read_kreg64(dd, kr_ibcstatus);
939 if (val & IB_SERDES_TRIM_DONE) {
940 ret = 1;
941 break;
942 }
943 msleep(10);
944 }
945 if (trim_tmo >= TRIM_TMO) {
946 qib_dev_err(dd, "No TRIMDONE in %d tries\n", trim_tmo);
947 ret = 0;
948 }
949 return ret;
950}
951
952#define TX_FAST_ELT (9)
953
954
955
956
957
958
959
960
961#define NUM_DDS_REGS 6
962#define DDS_REG_MAP 0x76A910
963
964#define DDS_VAL(amp_d, main_d, ipst_d, ipre_d, amp_s, main_s, ipst_s, ipre_s) \
965 { { ((amp_d & 0x1F) << 1) | 1, ((amp_s & 0x1F) << 1) | 1, \
966 (main_d << 3) | 4 | (ipre_d >> 2), \
967 (main_s << 3) | 4 | (ipre_s >> 2), \
968 ((ipst_d & 0xF) << 1) | ((ipre_d & 3) << 6) | 0x21, \
969 ((ipst_s & 0xF) << 1) | ((ipre_s & 3) << 6) | 0x21 } }
970
971static struct dds_init {
972 uint8_t reg_vals[NUM_DDS_REGS];
973} dds_init_vals[] = {
974
975
976#define DDS_3M 0
977 DDS_VAL(31, 19, 12, 0, 29, 22, 9, 0),
978 DDS_VAL(31, 12, 15, 4, 31, 15, 15, 1),
979 DDS_VAL(31, 13, 15, 3, 31, 16, 15, 0),
980 DDS_VAL(31, 14, 15, 2, 31, 17, 14, 0),
981 DDS_VAL(31, 15, 15, 1, 31, 18, 13, 0),
982 DDS_VAL(31, 16, 15, 0, 31, 19, 12, 0),
983 DDS_VAL(31, 17, 14, 0, 31, 20, 11, 0),
984 DDS_VAL(31, 18, 13, 0, 30, 21, 10, 0),
985 DDS_VAL(31, 20, 11, 0, 28, 23, 8, 0),
986 DDS_VAL(31, 21, 10, 0, 27, 24, 7, 0),
987 DDS_VAL(31, 22, 9, 0, 26, 25, 6, 0),
988 DDS_VAL(30, 23, 8, 0, 25, 26, 5, 0),
989 DDS_VAL(29, 24, 7, 0, 23, 27, 4, 0),
990
991#define DDS_1M 13
992 DDS_VAL(28, 25, 6, 0, 21, 28, 3, 0),
993 DDS_VAL(27, 26, 5, 0, 19, 29, 2, 0),
994 DDS_VAL(25, 27, 4, 0, 17, 30, 1, 0)
995};
996
997
998
999
1000
1001#define RXEQ_INIT_RDESC(elt, addr) (((elt) & 0xF) | ((addr) << 4))
1002#define RXEQ_VAL(elt, adr, val0, val1, val2, val3) \
1003 {RXEQ_INIT_RDESC((elt), (adr)), {(val0), (val1), (val2), (val3)} }
1004
1005#define RXEQ_VAL_ALL(elt, adr, val) \
1006 {RXEQ_INIT_RDESC((elt), (adr)), {(val), (val), (val), (val)} }
1007
1008#define RXEQ_SDR_DFELTH 0
1009#define RXEQ_SDR_TLTH 0
1010#define RXEQ_SDR_G1CNT_Z1CNT 0x11
1011#define RXEQ_SDR_ZCNT 23
1012
1013static struct rxeq_init {
1014 u16 rdesc;
1015 u8 rdata[4];
1016} rxeq_init_vals[] = {
1017
1018 RXEQ_VAL_ALL(7, 0x27, 0x10),
1019
1020 RXEQ_VAL(7, 8, 0, 0, 0, 0),
1021 RXEQ_VAL(7, 0x21, 0, 0, 0, 0),
1022
1023 RXEQ_VAL(7, 9, 2, 2, 2, 2),
1024 RXEQ_VAL(7, 0x23, 2, 2, 2, 2),
1025
1026 RXEQ_VAL(7, 0x1B, 12, 12, 12, 12),
1027 RXEQ_VAL(7, 0x1C, 12, 12, 12, 12),
1028
1029 RXEQ_VAL(7, 0x1E, 16, 16, 16, 16),
1030 RXEQ_VAL(7, 0x1F, 16, 16, 16, 16),
1031
1032 RXEQ_VAL_ALL(6, 6, 0x20),
1033 RXEQ_VAL_ALL(6, 6, 0),
1034};
1035
1036
1037#define DDS_ROWS (16)
1038#define RXEQ_ROWS ARRAY_SIZE(rxeq_init_vals)
1039
1040static int qib_sd_setvals(struct qib_devdata *dd)
1041{
1042 int idx, midx;
1043 int min_idx;
1044 uint32_t dds_reg_map;
1045 u64 __iomem *taddr, *iaddr;
1046 uint64_t data;
1047 uint64_t sdctl;
1048
1049 taddr = dd->kregbase + kr_serdes_maptable;
1050 iaddr = dd->kregbase + kr_serdes_ddsrxeq0;
1051
1052
1053
1054
1055
1056
1057 sdctl = qib_read_kreg64(dd, kr_ibserdesctrl);
1058 sdctl = (sdctl & ~(0x1f << 8)) | (NUM_DDS_REGS << 8);
1059 sdctl = (sdctl & ~(0x1f << 13)) | (RXEQ_ROWS << 13);
1060 qib_write_kreg(dd, kr_ibserdesctrl, sdctl);
1061
1062
1063
1064
1065 dds_reg_map = DDS_REG_MAP;
1066 for (idx = 0; idx < NUM_DDS_REGS; ++idx) {
1067 data = ((dds_reg_map & 0xF) << 4) | TX_FAST_ELT;
1068 writeq(data, iaddr + idx);
1069 mmiowb();
1070 qib_read_kreg32(dd, kr_scratch);
1071 dds_reg_map >>= 4;
1072 for (midx = 0; midx < DDS_ROWS; ++midx) {
1073 u64 __iomem *daddr = taddr + ((midx << 4) + idx);
1074 data = dds_init_vals[midx].reg_vals[idx];
1075 writeq(data, daddr);
1076 mmiowb();
1077 qib_read_kreg32(dd, kr_scratch);
1078 }
1079 }
1080
1081
1082
1083
1084
1085
1086
1087 min_idx = idx;
1088 taddr += 0x100;
1089
1090 for (idx = 0; idx < RXEQ_ROWS; ++idx) {
1091 int didx;
1092 int vidx;
1093
1094
1095 didx = idx + min_idx;
1096
1097 writeq(rxeq_init_vals[idx].rdesc, iaddr + didx);
1098 mmiowb();
1099 qib_read_kreg32(dd, kr_scratch);
1100
1101 for (vidx = 0; vidx < 4; vidx++) {
1102 data = rxeq_init_vals[idx].rdata[vidx];
1103 writeq(data, taddr + (vidx << 6) + idx);
1104 mmiowb();
1105 qib_read_kreg32(dd, kr_scratch);
1106 }
1107 }
1108 return 0;
1109}
1110
1111#define CMUCTRL5 EPB_LOC(7, 0, 0x15)
1112#define RXHSCTRL0(chan) EPB_LOC(chan, 6, 0)
1113#define VCDL_DAC2(chan) EPB_LOC(chan, 6, 5)
1114#define VCDL_CTRL0(chan) EPB_LOC(chan, 6, 6)
1115#define VCDL_CTRL2(chan) EPB_LOC(chan, 6, 8)
1116#define START_EQ2(chan) EPB_LOC(chan, 7, 0x28)
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128static int ibsd_mod_allchnls(struct qib_devdata *dd, int loc, int val,
1129 int mask)
1130{
1131 int ret = -1;
1132 int chnl;
1133
1134 if (loc & EPB_GLOBAL_WR) {
1135
1136
1137
1138
1139
1140
1141 loc |= (1U << EPB_IB_QUAD0_CS_SHF);
1142 chnl = (loc >> (4 + EPB_ADDR_SHF)) & 7;
1143 if (mask != 0xFF) {
1144 ret = qib_sd7220_reg_mod(dd, IB_7220_SERDES,
1145 loc & ~EPB_GLOBAL_WR, 0, 0);
1146 if (ret < 0) {
1147 int sloc = loc >> EPB_ADDR_SHF;
1148
1149 qib_dev_err(dd,
1150 "pre-read failed: elt %d, addr 0x%X, chnl %d\n",
1151 (sloc & 0xF),
1152 (sloc >> 9) & 0x3f, chnl);
1153 return ret;
1154 }
1155 val = (ret & ~mask) | (val & mask);
1156 }
1157 loc &= ~(7 << (4+EPB_ADDR_SHF));
1158 ret = qib_sd7220_reg_mod(dd, IB_7220_SERDES, loc, val, 0xFF);
1159 if (ret < 0) {
1160 int sloc = loc >> EPB_ADDR_SHF;
1161
1162 qib_dev_err(dd,
1163 "Global WR failed: elt %d, addr 0x%X, val %02X\n",
1164 (sloc & 0xF), (sloc >> 9) & 0x3f, val);
1165 }
1166 return ret;
1167 }
1168
1169 loc &= ~(7 << (4+EPB_ADDR_SHF));
1170 loc |= (1U << EPB_IB_QUAD0_CS_SHF);
1171 for (chnl = 0; chnl < 4; ++chnl) {
1172 int cloc = loc | (chnl << (4+EPB_ADDR_SHF));
1173
1174 ret = qib_sd7220_reg_mod(dd, IB_7220_SERDES, cloc, val, mask);
1175 if (ret < 0) {
1176 int sloc = loc >> EPB_ADDR_SHF;
1177
1178 qib_dev_err(dd,
1179 "Write failed: elt %d, addr 0x%X, chnl %d, val 0x%02X, mask 0x%02X\n",
1180 (sloc & 0xF), (sloc >> 9) & 0x3f, chnl,
1181 val & 0xFF, mask & 0xFF);
1182 break;
1183 }
1184 }
1185 return ret;
1186}
1187
1188
1189
1190
1191
1192static int set_dds_vals(struct qib_devdata *dd, struct dds_init *ddi)
1193{
1194 int ret;
1195 int idx, reg, data;
1196 uint32_t regmap;
1197
1198 regmap = DDS_REG_MAP;
1199 for (idx = 0; idx < NUM_DDS_REGS; ++idx) {
1200 reg = (regmap & 0xF);
1201 regmap >>= 4;
1202 data = ddi->reg_vals[idx];
1203
1204 ret = ibsd_mod_allchnls(dd, EPB_LOC(0, 9, reg), data, 0xFF);
1205 if (ret < 0)
1206 break;
1207 }
1208 return ret;
1209}
1210
1211
1212
1213
1214
1215static int set_rxeq_vals(struct qib_devdata *dd, int vsel)
1216{
1217 int ret;
1218 int ridx;
1219 int cnt = ARRAY_SIZE(rxeq_init_vals);
1220
1221 for (ridx = 0; ridx < cnt; ++ridx) {
1222 int elt, reg, val, loc;
1223
1224 elt = rxeq_init_vals[ridx].rdesc & 0xF;
1225 reg = rxeq_init_vals[ridx].rdesc >> 4;
1226 loc = EPB_LOC(0, elt, reg);
1227 val = rxeq_init_vals[ridx].rdata[vsel];
1228
1229 ret = ibsd_mod_allchnls(dd, loc, val, 0xFF);
1230 if (ret < 0)
1231 break;
1232 }
1233 return ret;
1234}
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245static unsigned qib_rxeq_set = 2;
1246module_param_named(rxeq_default_set, qib_rxeq_set, uint,
1247 S_IWUSR | S_IRUGO);
1248MODULE_PARM_DESC(rxeq_default_set,
1249 "Which set [0..3] of Rx Equalization values is default");
1250
1251static int qib_internal_presets(struct qib_devdata *dd)
1252{
1253 int ret = 0;
1254
1255 ret = set_dds_vals(dd, dds_init_vals + DDS_3M);
1256
1257 if (ret < 0)
1258 qib_dev_err(dd, "Failed to set default DDS values\n");
1259 ret = set_rxeq_vals(dd, qib_rxeq_set & 3);
1260 if (ret < 0)
1261 qib_dev_err(dd, "Failed to set default RXEQ values\n");
1262 return ret;
1263}
1264
1265int qib_sd7220_presets(struct qib_devdata *dd)
1266{
1267 int ret = 0;
1268
1269 if (!dd->cspec->presets_needed)
1270 return ret;
1271 dd->cspec->presets_needed = 0;
1272
1273 qib_ibsd_reset(dd, 1);
1274 udelay(2);
1275 qib_sd_trimdone_monitor(dd, "link-down");
1276
1277 ret = qib_internal_presets(dd);
1278 return ret;
1279}
1280
1281static int qib_sd_trimself(struct qib_devdata *dd, int val)
1282{
1283 int loc = CMUCTRL5 | (1U << EPB_IB_QUAD0_CS_SHF);
1284
1285 return qib_sd7220_reg_mod(dd, IB_7220_SERDES, loc, val, 0xFF);
1286}
1287
1288static int qib_sd_early(struct qib_devdata *dd)
1289{
1290 int ret;
1291
1292 ret = ibsd_mod_allchnls(dd, RXHSCTRL0(0) | EPB_GLOBAL_WR, 0xD4, 0xFF);
1293 if (ret < 0)
1294 goto bail;
1295 ret = ibsd_mod_allchnls(dd, START_EQ1(0) | EPB_GLOBAL_WR, 0x10, 0xFF);
1296 if (ret < 0)
1297 goto bail;
1298 ret = ibsd_mod_allchnls(dd, START_EQ2(0) | EPB_GLOBAL_WR, 0x30, 0xFF);
1299bail:
1300 return ret;
1301}
1302
1303#define BACTRL(chnl) EPB_LOC(chnl, 6, 0x0E)
1304#define LDOUTCTRL1(chnl) EPB_LOC(chnl, 7, 6)
1305#define RXHSSTATUS(chnl) EPB_LOC(chnl, 6, 0xF)
1306
1307static int qib_sd_dactrim(struct qib_devdata *dd)
1308{
1309 int ret;
1310
1311 ret = ibsd_mod_allchnls(dd, VCDL_DAC2(0) | EPB_GLOBAL_WR, 0x2D, 0xFF);
1312 if (ret < 0)
1313 goto bail;
1314
1315
1316 ret = ibsd_mod_allchnls(dd, VCDL_CTRL2(0), 3, 0xF);
1317 if (ret < 0)
1318 goto bail;
1319
1320 ret = ibsd_mod_allchnls(dd, BACTRL(0) | EPB_GLOBAL_WR, 0x40, 0xFF);
1321 if (ret < 0)
1322 goto bail;
1323
1324 ret = ibsd_mod_allchnls(dd, LDOUTCTRL1(0) | EPB_GLOBAL_WR, 0x04, 0xFF);
1325 if (ret < 0)
1326 goto bail;
1327
1328 ret = ibsd_mod_allchnls(dd, RXHSSTATUS(0) | EPB_GLOBAL_WR, 0x04, 0xFF);
1329 if (ret < 0)
1330 goto bail;
1331
1332
1333
1334
1335
1336 udelay(415);
1337
1338 ret = ibsd_mod_allchnls(dd, LDOUTCTRL1(0) | EPB_GLOBAL_WR, 0x00, 0xFF);
1339
1340bail:
1341 return ret;
1342}
1343
1344#define RELOCK_FIRST_MS 3
1345#define RXLSPPM(chan) EPB_LOC(chan, 0, 2)
1346void toggle_7220_rclkrls(struct qib_devdata *dd)
1347{
1348 int loc = RXLSPPM(0) | EPB_GLOBAL_WR;
1349 int ret;
1350
1351 ret = ibsd_mod_allchnls(dd, loc, 0, 0x80);
1352 if (ret < 0)
1353 qib_dev_err(dd, "RCLKRLS failed to clear D7\n");
1354 else {
1355 udelay(1);
1356 ibsd_mod_allchnls(dd, loc, 0x80, 0x80);
1357 }
1358
1359 udelay(1);
1360 ret = ibsd_mod_allchnls(dd, loc, 0, 0x80);
1361 if (ret < 0)
1362 qib_dev_err(dd, "RCLKRLS failed to clear D7\n");
1363 else {
1364 udelay(1);
1365 ibsd_mod_allchnls(dd, loc, 0x80, 0x80);
1366 }
1367
1368 dd->f_xgxs_reset(dd->pport);
1369}
1370
1371
1372
1373
1374
1375
1376
1377void shutdown_7220_relock_poll(struct qib_devdata *dd)
1378{
1379 if (dd->cspec->relock_timer_active)
1380 del_timer_sync(&dd->cspec->relock_timer);
1381}
1382
1383static unsigned qib_relock_by_timer = 1;
1384module_param_named(relock_by_timer, qib_relock_by_timer, uint,
1385 S_IWUSR | S_IRUGO);
1386MODULE_PARM_DESC(relock_by_timer, "Allow relock attempt if link not up");
1387
1388static void qib_run_relock(unsigned long opaque)
1389{
1390 struct qib_devdata *dd = (struct qib_devdata *)opaque;
1391 struct qib_pportdata *ppd = dd->pport;
1392 struct qib_chip_specific *cs = dd->cspec;
1393 int timeoff;
1394
1395
1396
1397
1398
1399
1400
1401 if ((dd->flags & QIB_INITTED) && !(ppd->lflags &
1402 (QIBL_IB_AUTONEG_INPROG | QIBL_LINKINIT | QIBL_LINKARMED |
1403 QIBL_LINKACTIVE))) {
1404 if (qib_relock_by_timer) {
1405 if (!(ppd->lflags & QIBL_IB_LINK_DISABLED))
1406 toggle_7220_rclkrls(dd);
1407 }
1408
1409 timeoff = cs->relock_interval << 1;
1410 if (timeoff > HZ)
1411 timeoff = HZ;
1412 cs->relock_interval = timeoff;
1413 } else
1414 timeoff = HZ;
1415 mod_timer(&cs->relock_timer, jiffies + timeoff);
1416}
1417
1418void set_7220_relock_poll(struct qib_devdata *dd, int ibup)
1419{
1420 struct qib_chip_specific *cs = dd->cspec;
1421
1422 if (ibup) {
1423
1424 if (cs->relock_timer_active) {
1425 cs->relock_interval = HZ;
1426 mod_timer(&cs->relock_timer, jiffies + HZ);
1427 }
1428 } else {
1429
1430 unsigned int timeout;
1431
1432 timeout = msecs_to_jiffies(RELOCK_FIRST_MS);
1433 if (timeout == 0)
1434 timeout = 1;
1435
1436 if (!cs->relock_timer_active) {
1437 cs->relock_timer_active = 1;
1438 init_timer(&cs->relock_timer);
1439 cs->relock_timer.function = qib_run_relock;
1440 cs->relock_timer.data = (unsigned long) dd;
1441 cs->relock_interval = timeout;
1442 cs->relock_timer.expires = jiffies + timeout;
1443 add_timer(&cs->relock_timer);
1444 } else {
1445 cs->relock_interval = timeout;
1446 mod_timer(&cs->relock_timer, jiffies + timeout);
1447 }
1448 }
1449}
1450