linux/drivers/media/platform/exynos4-is/fimc-core.c
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   1/*
   2 * Samsung S5P/EXYNOS4 SoC series FIMC (CAMIF) driver
   3 *
   4 * Copyright (C) 2010-2012 Samsung Electronics Co., Ltd.
   5 * Sylwester Nawrocki <s.nawrocki@samsung.com>
   6 *
   7 * This program is free software; you can redistribute it and/or modify
   8 * it under the terms of the GNU General Public License as published
   9 * by the Free Software Foundation, either version 2 of the License,
  10 * or (at your option) any later version.
  11 */
  12
  13#include <linux/module.h>
  14#include <linux/kernel.h>
  15#include <linux/types.h>
  16#include <linux/errno.h>
  17#include <linux/bug.h>
  18#include <linux/interrupt.h>
  19#include <linux/device.h>
  20#include <linux/platform_device.h>
  21#include <linux/pm_runtime.h>
  22#include <linux/list.h>
  23#include <linux/mfd/syscon.h>
  24#include <linux/io.h>
  25#include <linux/of.h>
  26#include <linux/of_device.h>
  27#include <linux/slab.h>
  28#include <linux/clk.h>
  29#include <media/v4l2-ioctl.h>
  30#include <media/videobuf2-core.h>
  31#include <media/videobuf2-dma-contig.h>
  32
  33#include "fimc-core.h"
  34#include "fimc-reg.h"
  35#include "media-dev.h"
  36
  37static char *fimc_clocks[MAX_FIMC_CLOCKS] = {
  38        "sclk_fimc", "fimc"
  39};
  40
  41static struct fimc_fmt fimc_formats[] = {
  42        {
  43                .name           = "RGB565",
  44                .fourcc         = V4L2_PIX_FMT_RGB565,
  45                .depth          = { 16 },
  46                .color          = FIMC_FMT_RGB565,
  47                .memplanes      = 1,
  48                .colplanes      = 1,
  49                .flags          = FMT_FLAGS_M2M,
  50        }, {
  51                .name           = "BGR666",
  52                .fourcc         = V4L2_PIX_FMT_BGR666,
  53                .depth          = { 32 },
  54                .color          = FIMC_FMT_RGB666,
  55                .memplanes      = 1,
  56                .colplanes      = 1,
  57                .flags          = FMT_FLAGS_M2M,
  58        }, {
  59                .name           = "BGRA8888, 32 bpp",
  60                .fourcc         = V4L2_PIX_FMT_BGR32,
  61                .depth          = { 32 },
  62                .color          = FIMC_FMT_RGB888,
  63                .memplanes      = 1,
  64                .colplanes      = 1,
  65                .flags          = FMT_FLAGS_M2M | FMT_HAS_ALPHA,
  66        }, {
  67                .name           = "ARGB1555",
  68                .fourcc         = V4L2_PIX_FMT_RGB555,
  69                .depth          = { 16 },
  70                .color          = FIMC_FMT_RGB555,
  71                .memplanes      = 1,
  72                .colplanes      = 1,
  73                .flags          = FMT_FLAGS_M2M_OUT | FMT_HAS_ALPHA,
  74        }, {
  75                .name           = "ARGB4444",
  76                .fourcc         = V4L2_PIX_FMT_RGB444,
  77                .depth          = { 16 },
  78                .color          = FIMC_FMT_RGB444,
  79                .memplanes      = 1,
  80                .colplanes      = 1,
  81                .flags          = FMT_FLAGS_M2M_OUT | FMT_HAS_ALPHA,
  82        }, {
  83                .name           = "YUV 4:4:4",
  84                .mbus_code      = V4L2_MBUS_FMT_YUV10_1X30,
  85                .flags          = FMT_FLAGS_WRITEBACK,
  86        }, {
  87                .name           = "YUV 4:2:2 packed, YCbYCr",
  88                .fourcc         = V4L2_PIX_FMT_YUYV,
  89                .depth          = { 16 },
  90                .color          = FIMC_FMT_YCBYCR422,
  91                .memplanes      = 1,
  92                .colplanes      = 1,
  93                .mbus_code      = V4L2_MBUS_FMT_YUYV8_2X8,
  94                .flags          = FMT_FLAGS_M2M | FMT_FLAGS_CAM,
  95        }, {
  96                .name           = "YUV 4:2:2 packed, CbYCrY",
  97                .fourcc         = V4L2_PIX_FMT_UYVY,
  98                .depth          = { 16 },
  99                .color          = FIMC_FMT_CBYCRY422,
 100                .memplanes      = 1,
 101                .colplanes      = 1,
 102                .mbus_code      = V4L2_MBUS_FMT_UYVY8_2X8,
 103                .flags          = FMT_FLAGS_M2M | FMT_FLAGS_CAM,
 104        }, {
 105                .name           = "YUV 4:2:2 packed, CrYCbY",
 106                .fourcc         = V4L2_PIX_FMT_VYUY,
 107                .depth          = { 16 },
 108                .color          = FIMC_FMT_CRYCBY422,
 109                .memplanes      = 1,
 110                .colplanes      = 1,
 111                .mbus_code      = V4L2_MBUS_FMT_VYUY8_2X8,
 112                .flags          = FMT_FLAGS_M2M | FMT_FLAGS_CAM,
 113        }, {
 114                .name           = "YUV 4:2:2 packed, YCrYCb",
 115                .fourcc         = V4L2_PIX_FMT_YVYU,
 116                .depth          = { 16 },
 117                .color          = FIMC_FMT_YCRYCB422,
 118                .memplanes      = 1,
 119                .colplanes      = 1,
 120                .mbus_code      = V4L2_MBUS_FMT_YVYU8_2X8,
 121                .flags          = FMT_FLAGS_M2M | FMT_FLAGS_CAM,
 122        }, {
 123                .name           = "YUV 4:2:2 planar, Y/Cb/Cr",
 124                .fourcc         = V4L2_PIX_FMT_YUV422P,
 125                .depth          = { 16 },
 126                .color          = FIMC_FMT_YCBYCR422,
 127                .memplanes      = 1,
 128                .colplanes      = 3,
 129                .flags          = FMT_FLAGS_M2M,
 130        }, {
 131                .name           = "YUV 4:2:2 planar, Y/CbCr",
 132                .fourcc         = V4L2_PIX_FMT_NV16,
 133                .depth          = { 16 },
 134                .color          = FIMC_FMT_YCBYCR422,
 135                .memplanes      = 1,
 136                .colplanes      = 2,
 137                .flags          = FMT_FLAGS_M2M,
 138        }, {
 139                .name           = "YUV 4:2:2 planar, Y/CrCb",
 140                .fourcc         = V4L2_PIX_FMT_NV61,
 141                .depth          = { 16 },
 142                .color          = FIMC_FMT_YCRYCB422,
 143                .memplanes      = 1,
 144                .colplanes      = 2,
 145                .flags          = FMT_FLAGS_M2M,
 146        }, {
 147                .name           = "YUV 4:2:0 planar, YCbCr",
 148                .fourcc         = V4L2_PIX_FMT_YUV420,
 149                .depth          = { 12 },
 150                .color          = FIMC_FMT_YCBCR420,
 151                .memplanes      = 1,
 152                .colplanes      = 3,
 153                .flags          = FMT_FLAGS_M2M,
 154        }, {
 155                .name           = "YUV 4:2:0 planar, Y/CbCr",
 156                .fourcc         = V4L2_PIX_FMT_NV12,
 157                .depth          = { 12 },
 158                .color          = FIMC_FMT_YCBCR420,
 159                .memplanes      = 1,
 160                .colplanes      = 2,
 161                .flags          = FMT_FLAGS_M2M,
 162        }, {
 163                .name           = "YUV 4:2:0 non-contig. 2p, Y/CbCr",
 164                .fourcc         = V4L2_PIX_FMT_NV12M,
 165                .color          = FIMC_FMT_YCBCR420,
 166                .depth          = { 8, 4 },
 167                .memplanes      = 2,
 168                .colplanes      = 2,
 169                .flags          = FMT_FLAGS_M2M,
 170        }, {
 171                .name           = "YUV 4:2:0 non-contig. 3p, Y/Cb/Cr",
 172                .fourcc         = V4L2_PIX_FMT_YUV420M,
 173                .color          = FIMC_FMT_YCBCR420,
 174                .depth          = { 8, 2, 2 },
 175                .memplanes      = 3,
 176                .colplanes      = 3,
 177                .flags          = FMT_FLAGS_M2M,
 178        }, {
 179                .name           = "YUV 4:2:0 non-contig. 2p, tiled",
 180                .fourcc         = V4L2_PIX_FMT_NV12MT,
 181                .color          = FIMC_FMT_YCBCR420,
 182                .depth          = { 8, 4 },
 183                .memplanes      = 2,
 184                .colplanes      = 2,
 185                .flags          = FMT_FLAGS_M2M,
 186        }, {
 187                .name           = "JPEG encoded data",
 188                .fourcc         = V4L2_PIX_FMT_JPEG,
 189                .color          = FIMC_FMT_JPEG,
 190                .depth          = { 8 },
 191                .memplanes      = 1,
 192                .colplanes      = 1,
 193                .mbus_code      = V4L2_MBUS_FMT_JPEG_1X8,
 194                .flags          = FMT_FLAGS_CAM | FMT_FLAGS_COMPRESSED,
 195        }, {
 196                .name           = "S5C73MX interleaved UYVY/JPEG",
 197                .fourcc         = V4L2_PIX_FMT_S5C_UYVY_JPG,
 198                .color          = FIMC_FMT_YUYV_JPEG,
 199                .depth          = { 8 },
 200                .memplanes      = 2,
 201                .colplanes      = 1,
 202                .mdataplanes    = 0x2, /* plane 1 holds frame meta data */
 203                .mbus_code      = V4L2_MBUS_FMT_S5C_UYVY_JPEG_1X8,
 204                .flags          = FMT_FLAGS_CAM | FMT_FLAGS_COMPRESSED,
 205        },
 206};
 207
 208struct fimc_fmt *fimc_get_format(unsigned int index)
 209{
 210        if (index >= ARRAY_SIZE(fimc_formats))
 211                return NULL;
 212
 213        return &fimc_formats[index];
 214}
 215
 216int fimc_check_scaler_ratio(struct fimc_ctx *ctx, int sw, int sh,
 217                            int dw, int dh, int rotation)
 218{
 219        if (rotation == 90 || rotation == 270)
 220                swap(dw, dh);
 221
 222        if (!ctx->scaler.enabled)
 223                return (sw == dw && sh == dh) ? 0 : -EINVAL;
 224
 225        if ((sw >= SCALER_MAX_HRATIO * dw) || (sh >= SCALER_MAX_VRATIO * dh))
 226                return -EINVAL;
 227
 228        return 0;
 229}
 230
 231static int fimc_get_scaler_factor(u32 src, u32 tar, u32 *ratio, u32 *shift)
 232{
 233        u32 sh = 6;
 234
 235        if (src >= 64 * tar)
 236                return -EINVAL;
 237
 238        while (sh--) {
 239                u32 tmp = 1 << sh;
 240                if (src >= tar * tmp) {
 241                        *shift = sh, *ratio = tmp;
 242                        return 0;
 243                }
 244        }
 245        *shift = 0, *ratio = 1;
 246        return 0;
 247}
 248
 249int fimc_set_scaler_info(struct fimc_ctx *ctx)
 250{
 251        const struct fimc_variant *variant = ctx->fimc_dev->variant;
 252        struct device *dev = &ctx->fimc_dev->pdev->dev;
 253        struct fimc_scaler *sc = &ctx->scaler;
 254        struct fimc_frame *s_frame = &ctx->s_frame;
 255        struct fimc_frame *d_frame = &ctx->d_frame;
 256        int tx, ty, sx, sy;
 257        int ret;
 258
 259        if (ctx->rotation == 90 || ctx->rotation == 270) {
 260                ty = d_frame->width;
 261                tx = d_frame->height;
 262        } else {
 263                tx = d_frame->width;
 264                ty = d_frame->height;
 265        }
 266        if (tx <= 0 || ty <= 0) {
 267                dev_err(dev, "Invalid target size: %dx%d\n", tx, ty);
 268                return -EINVAL;
 269        }
 270
 271        sx = s_frame->width;
 272        sy = s_frame->height;
 273        if (sx <= 0 || sy <= 0) {
 274                dev_err(dev, "Invalid source size: %dx%d\n", sx, sy);
 275                return -EINVAL;
 276        }
 277        sc->real_width = sx;
 278        sc->real_height = sy;
 279
 280        ret = fimc_get_scaler_factor(sx, tx, &sc->pre_hratio, &sc->hfactor);
 281        if (ret)
 282                return ret;
 283
 284        ret = fimc_get_scaler_factor(sy, ty,  &sc->pre_vratio, &sc->vfactor);
 285        if (ret)
 286                return ret;
 287
 288        sc->pre_dst_width = sx / sc->pre_hratio;
 289        sc->pre_dst_height = sy / sc->pre_vratio;
 290
 291        if (variant->has_mainscaler_ext) {
 292                sc->main_hratio = (sx << 14) / (tx << sc->hfactor);
 293                sc->main_vratio = (sy << 14) / (ty << sc->vfactor);
 294        } else {
 295                sc->main_hratio = (sx << 8) / (tx << sc->hfactor);
 296                sc->main_vratio = (sy << 8) / (ty << sc->vfactor);
 297
 298        }
 299
 300        sc->scaleup_h = (tx >= sx) ? 1 : 0;
 301        sc->scaleup_v = (ty >= sy) ? 1 : 0;
 302
 303        /* check to see if input and output size/format differ */
 304        if (s_frame->fmt->color == d_frame->fmt->color
 305                && s_frame->width == d_frame->width
 306                && s_frame->height == d_frame->height)
 307                sc->copy_mode = 1;
 308        else
 309                sc->copy_mode = 0;
 310
 311        return 0;
 312}
 313
 314static irqreturn_t fimc_irq_handler(int irq, void *priv)
 315{
 316        struct fimc_dev *fimc = priv;
 317        struct fimc_ctx *ctx;
 318
 319        fimc_hw_clear_irq(fimc);
 320
 321        spin_lock(&fimc->slock);
 322
 323        if (test_and_clear_bit(ST_M2M_PEND, &fimc->state)) {
 324                if (test_and_clear_bit(ST_M2M_SUSPENDING, &fimc->state)) {
 325                        set_bit(ST_M2M_SUSPENDED, &fimc->state);
 326                        wake_up(&fimc->irq_queue);
 327                        goto out;
 328                }
 329                ctx = v4l2_m2m_get_curr_priv(fimc->m2m.m2m_dev);
 330                if (ctx != NULL) {
 331                        spin_unlock(&fimc->slock);
 332                        fimc_m2m_job_finish(ctx, VB2_BUF_STATE_DONE);
 333
 334                        if (ctx->state & FIMC_CTX_SHUT) {
 335                                ctx->state &= ~FIMC_CTX_SHUT;
 336                                wake_up(&fimc->irq_queue);
 337                        }
 338                        return IRQ_HANDLED;
 339                }
 340        } else if (test_bit(ST_CAPT_PEND, &fimc->state)) {
 341                int last_buf = test_bit(ST_CAPT_JPEG, &fimc->state) &&
 342                                fimc->vid_cap.reqbufs_count == 1;
 343                fimc_capture_irq_handler(fimc, !last_buf);
 344        }
 345out:
 346        spin_unlock(&fimc->slock);
 347        return IRQ_HANDLED;
 348}
 349
 350/* The color format (colplanes, memplanes) must be already configured. */
 351int fimc_prepare_addr(struct fimc_ctx *ctx, struct vb2_buffer *vb,
 352                      struct fimc_frame *frame, struct fimc_addr *paddr)
 353{
 354        int ret = 0;
 355        u32 pix_size;
 356
 357        if (vb == NULL || frame == NULL)
 358                return -EINVAL;
 359
 360        pix_size = frame->width * frame->height;
 361
 362        dbg("memplanes= %d, colplanes= %d, pix_size= %d",
 363                frame->fmt->memplanes, frame->fmt->colplanes, pix_size);
 364
 365        paddr->y = vb2_dma_contig_plane_dma_addr(vb, 0);
 366
 367        if (frame->fmt->memplanes == 1) {
 368                switch (frame->fmt->colplanes) {
 369                case 1:
 370                        paddr->cb = 0;
 371                        paddr->cr = 0;
 372                        break;
 373                case 2:
 374                        /* decompose Y into Y/Cb */
 375                        paddr->cb = (u32)(paddr->y + pix_size);
 376                        paddr->cr = 0;
 377                        break;
 378                case 3:
 379                        paddr->cb = (u32)(paddr->y + pix_size);
 380                        /* decompose Y into Y/Cb/Cr */
 381                        if (FIMC_FMT_YCBCR420 == frame->fmt->color)
 382                                paddr->cr = (u32)(paddr->cb
 383                                                + (pix_size >> 2));
 384                        else /* 422 */
 385                                paddr->cr = (u32)(paddr->cb
 386                                                + (pix_size >> 1));
 387                        break;
 388                default:
 389                        return -EINVAL;
 390                }
 391        } else if (!frame->fmt->mdataplanes) {
 392                if (frame->fmt->memplanes >= 2)
 393                        paddr->cb = vb2_dma_contig_plane_dma_addr(vb, 1);
 394
 395                if (frame->fmt->memplanes == 3)
 396                        paddr->cr = vb2_dma_contig_plane_dma_addr(vb, 2);
 397        }
 398
 399        dbg("PHYS_ADDR: y= 0x%X  cb= 0x%X cr= 0x%X ret= %d",
 400            paddr->y, paddr->cb, paddr->cr, ret);
 401
 402        return ret;
 403}
 404
 405/* Set order for 1 and 2 plane YCBCR 4:2:2 formats. */
 406void fimc_set_yuv_order(struct fimc_ctx *ctx)
 407{
 408        /* The one only mode supported in SoC. */
 409        ctx->in_order_2p = FIMC_REG_CIOCTRL_ORDER422_2P_LSB_CRCB;
 410        ctx->out_order_2p = FIMC_REG_CIOCTRL_ORDER422_2P_LSB_CRCB;
 411
 412        /* Set order for 1 plane input formats. */
 413        switch (ctx->s_frame.fmt->color) {
 414        case FIMC_FMT_YCRYCB422:
 415                ctx->in_order_1p = FIMC_REG_MSCTRL_ORDER422_YCRYCB;
 416                break;
 417        case FIMC_FMT_CBYCRY422:
 418                ctx->in_order_1p = FIMC_REG_MSCTRL_ORDER422_CBYCRY;
 419                break;
 420        case FIMC_FMT_CRYCBY422:
 421                ctx->in_order_1p = FIMC_REG_MSCTRL_ORDER422_CRYCBY;
 422                break;
 423        case FIMC_FMT_YCBYCR422:
 424        default:
 425                ctx->in_order_1p = FIMC_REG_MSCTRL_ORDER422_YCBYCR;
 426                break;
 427        }
 428        dbg("ctx->in_order_1p= %d", ctx->in_order_1p);
 429
 430        switch (ctx->d_frame.fmt->color) {
 431        case FIMC_FMT_YCRYCB422:
 432                ctx->out_order_1p = FIMC_REG_CIOCTRL_ORDER422_YCRYCB;
 433                break;
 434        case FIMC_FMT_CBYCRY422:
 435                ctx->out_order_1p = FIMC_REG_CIOCTRL_ORDER422_CBYCRY;
 436                break;
 437        case FIMC_FMT_CRYCBY422:
 438                ctx->out_order_1p = FIMC_REG_CIOCTRL_ORDER422_CRYCBY;
 439                break;
 440        case FIMC_FMT_YCBYCR422:
 441        default:
 442                ctx->out_order_1p = FIMC_REG_CIOCTRL_ORDER422_YCBYCR;
 443                break;
 444        }
 445        dbg("ctx->out_order_1p= %d", ctx->out_order_1p);
 446}
 447
 448void fimc_prepare_dma_offset(struct fimc_ctx *ctx, struct fimc_frame *f)
 449{
 450        bool pix_hoff = ctx->fimc_dev->drv_data->dma_pix_hoff;
 451        u32 i, depth = 0;
 452
 453        for (i = 0; i < f->fmt->memplanes; i++)
 454                depth += f->fmt->depth[i];
 455
 456        f->dma_offset.y_h = f->offs_h;
 457        if (!pix_hoff)
 458                f->dma_offset.y_h *= (depth >> 3);
 459
 460        f->dma_offset.y_v = f->offs_v;
 461
 462        f->dma_offset.cb_h = f->offs_h;
 463        f->dma_offset.cb_v = f->offs_v;
 464
 465        f->dma_offset.cr_h = f->offs_h;
 466        f->dma_offset.cr_v = f->offs_v;
 467
 468        if (!pix_hoff) {
 469                if (f->fmt->colplanes == 3) {
 470                        f->dma_offset.cb_h >>= 1;
 471                        f->dma_offset.cr_h >>= 1;
 472                }
 473                if (f->fmt->color == FIMC_FMT_YCBCR420) {
 474                        f->dma_offset.cb_v >>= 1;
 475                        f->dma_offset.cr_v >>= 1;
 476                }
 477        }
 478
 479        dbg("in_offset: color= %d, y_h= %d, y_v= %d",
 480            f->fmt->color, f->dma_offset.y_h, f->dma_offset.y_v);
 481}
 482
 483static int fimc_set_color_effect(struct fimc_ctx *ctx, enum v4l2_colorfx colorfx)
 484{
 485        struct fimc_effect *effect = &ctx->effect;
 486
 487        switch (colorfx) {
 488        case V4L2_COLORFX_NONE:
 489                effect->type = FIMC_REG_CIIMGEFF_FIN_BYPASS;
 490                break;
 491        case V4L2_COLORFX_BW:
 492                effect->type = FIMC_REG_CIIMGEFF_FIN_ARBITRARY;
 493                effect->pat_cb = 128;
 494                effect->pat_cr = 128;
 495                break;
 496        case V4L2_COLORFX_SEPIA:
 497                effect->type = FIMC_REG_CIIMGEFF_FIN_ARBITRARY;
 498                effect->pat_cb = 115;
 499                effect->pat_cr = 145;
 500                break;
 501        case V4L2_COLORFX_NEGATIVE:
 502                effect->type = FIMC_REG_CIIMGEFF_FIN_NEGATIVE;
 503                break;
 504        case V4L2_COLORFX_EMBOSS:
 505                effect->type = FIMC_REG_CIIMGEFF_FIN_EMBOSSING;
 506                break;
 507        case V4L2_COLORFX_ART_FREEZE:
 508                effect->type = FIMC_REG_CIIMGEFF_FIN_ARTFREEZE;
 509                break;
 510        case V4L2_COLORFX_SILHOUETTE:
 511                effect->type = FIMC_REG_CIIMGEFF_FIN_SILHOUETTE;
 512                break;
 513        case V4L2_COLORFX_SET_CBCR:
 514                effect->type = FIMC_REG_CIIMGEFF_FIN_ARBITRARY;
 515                effect->pat_cb = ctx->ctrls.colorfx_cbcr->val >> 8;
 516                effect->pat_cr = ctx->ctrls.colorfx_cbcr->val & 0xff;
 517                break;
 518        default:
 519                return -EINVAL;
 520        }
 521
 522        return 0;
 523}
 524
 525/*
 526 * V4L2 controls handling
 527 */
 528#define ctrl_to_ctx(__ctrl) \
 529        container_of((__ctrl)->handler, struct fimc_ctx, ctrls.handler)
 530
 531static int __fimc_s_ctrl(struct fimc_ctx *ctx, struct v4l2_ctrl *ctrl)
 532{
 533        struct fimc_dev *fimc = ctx->fimc_dev;
 534        const struct fimc_variant *variant = fimc->variant;
 535        int ret = 0;
 536
 537        if (ctrl->flags & V4L2_CTRL_FLAG_INACTIVE)
 538                return 0;
 539
 540        switch (ctrl->id) {
 541        case V4L2_CID_HFLIP:
 542                ctx->hflip = ctrl->val;
 543                break;
 544
 545        case V4L2_CID_VFLIP:
 546                ctx->vflip = ctrl->val;
 547                break;
 548
 549        case V4L2_CID_ROTATE:
 550                if (fimc_capture_pending(fimc)) {
 551                        ret = fimc_check_scaler_ratio(ctx, ctx->s_frame.width,
 552                                        ctx->s_frame.height, ctx->d_frame.width,
 553                                        ctx->d_frame.height, ctrl->val);
 554                        if (ret)
 555                                return -EINVAL;
 556                }
 557                if ((ctrl->val == 90 || ctrl->val == 270) &&
 558                    !variant->has_out_rot)
 559                        return -EINVAL;
 560
 561                ctx->rotation = ctrl->val;
 562                break;
 563
 564        case V4L2_CID_ALPHA_COMPONENT:
 565                ctx->d_frame.alpha = ctrl->val;
 566                break;
 567
 568        case V4L2_CID_COLORFX:
 569                ret = fimc_set_color_effect(ctx, ctrl->val);
 570                if (ret)
 571                        return ret;
 572                break;
 573        }
 574
 575        ctx->state |= FIMC_PARAMS;
 576        set_bit(ST_CAPT_APPLY_CFG, &fimc->state);
 577        return 0;
 578}
 579
 580static int fimc_s_ctrl(struct v4l2_ctrl *ctrl)
 581{
 582        struct fimc_ctx *ctx = ctrl_to_ctx(ctrl);
 583        unsigned long flags;
 584        int ret;
 585
 586        spin_lock_irqsave(&ctx->fimc_dev->slock, flags);
 587        ret = __fimc_s_ctrl(ctx, ctrl);
 588        spin_unlock_irqrestore(&ctx->fimc_dev->slock, flags);
 589
 590        return ret;
 591}
 592
 593static const struct v4l2_ctrl_ops fimc_ctrl_ops = {
 594        .s_ctrl = fimc_s_ctrl,
 595};
 596
 597int fimc_ctrls_create(struct fimc_ctx *ctx)
 598{
 599        unsigned int max_alpha = fimc_get_alpha_mask(ctx->d_frame.fmt);
 600        struct fimc_ctrls *ctrls = &ctx->ctrls;
 601        struct v4l2_ctrl_handler *handler = &ctrls->handler;
 602
 603        if (ctx->ctrls.ready)
 604                return 0;
 605
 606        v4l2_ctrl_handler_init(handler, 6);
 607
 608        ctrls->rotate = v4l2_ctrl_new_std(handler, &fimc_ctrl_ops,
 609                                        V4L2_CID_ROTATE, 0, 270, 90, 0);
 610        ctrls->hflip = v4l2_ctrl_new_std(handler, &fimc_ctrl_ops,
 611                                        V4L2_CID_HFLIP, 0, 1, 1, 0);
 612        ctrls->vflip = v4l2_ctrl_new_std(handler, &fimc_ctrl_ops,
 613                                        V4L2_CID_VFLIP, 0, 1, 1, 0);
 614
 615        if (ctx->fimc_dev->drv_data->alpha_color)
 616                ctrls->alpha = v4l2_ctrl_new_std(handler, &fimc_ctrl_ops,
 617                                        V4L2_CID_ALPHA_COMPONENT,
 618                                        0, max_alpha, 1, 0);
 619        else
 620                ctrls->alpha = NULL;
 621
 622        ctrls->colorfx = v4l2_ctrl_new_std_menu(handler, &fimc_ctrl_ops,
 623                                V4L2_CID_COLORFX, V4L2_COLORFX_SET_CBCR,
 624                                ~0x983f, V4L2_COLORFX_NONE);
 625
 626        ctrls->colorfx_cbcr = v4l2_ctrl_new_std(handler, &fimc_ctrl_ops,
 627                                V4L2_CID_COLORFX_CBCR, 0, 0xffff, 1, 0);
 628
 629        ctx->effect.type = FIMC_REG_CIIMGEFF_FIN_BYPASS;
 630
 631        if (!handler->error) {
 632                v4l2_ctrl_cluster(2, &ctrls->colorfx);
 633                ctrls->ready = true;
 634        }
 635
 636        return handler->error;
 637}
 638
 639void fimc_ctrls_delete(struct fimc_ctx *ctx)
 640{
 641        struct fimc_ctrls *ctrls = &ctx->ctrls;
 642
 643        if (ctrls->ready) {
 644                v4l2_ctrl_handler_free(&ctrls->handler);
 645                ctrls->ready = false;
 646                ctrls->alpha = NULL;
 647        }
 648}
 649
 650void fimc_ctrls_activate(struct fimc_ctx *ctx, bool active)
 651{
 652        unsigned int has_alpha = ctx->d_frame.fmt->flags & FMT_HAS_ALPHA;
 653        struct fimc_ctrls *ctrls = &ctx->ctrls;
 654
 655        if (!ctrls->ready)
 656                return;
 657
 658        mutex_lock(ctrls->handler.lock);
 659        v4l2_ctrl_activate(ctrls->rotate, active);
 660        v4l2_ctrl_activate(ctrls->hflip, active);
 661        v4l2_ctrl_activate(ctrls->vflip, active);
 662        v4l2_ctrl_activate(ctrls->colorfx, active);
 663        if (ctrls->alpha)
 664                v4l2_ctrl_activate(ctrls->alpha, active && has_alpha);
 665
 666        if (active) {
 667                fimc_set_color_effect(ctx, ctrls->colorfx->cur.val);
 668                ctx->rotation = ctrls->rotate->val;
 669                ctx->hflip    = ctrls->hflip->val;
 670                ctx->vflip    = ctrls->vflip->val;
 671        } else {
 672                ctx->effect.type = FIMC_REG_CIIMGEFF_FIN_BYPASS;
 673                ctx->rotation = 0;
 674                ctx->hflip    = 0;
 675                ctx->vflip    = 0;
 676        }
 677        mutex_unlock(ctrls->handler.lock);
 678}
 679
 680/* Update maximum value of the alpha color control */
 681void fimc_alpha_ctrl_update(struct fimc_ctx *ctx)
 682{
 683        struct fimc_dev *fimc = ctx->fimc_dev;
 684        struct v4l2_ctrl *ctrl = ctx->ctrls.alpha;
 685
 686        if (ctrl == NULL || !fimc->drv_data->alpha_color)
 687                return;
 688
 689        v4l2_ctrl_lock(ctrl);
 690        ctrl->maximum = fimc_get_alpha_mask(ctx->d_frame.fmt);
 691
 692        if (ctrl->cur.val > ctrl->maximum)
 693                ctrl->cur.val = ctrl->maximum;
 694
 695        v4l2_ctrl_unlock(ctrl);
 696}
 697
 698void __fimc_get_format(struct fimc_frame *frame, struct v4l2_format *f)
 699{
 700        struct v4l2_pix_format_mplane *pixm = &f->fmt.pix_mp;
 701        int i;
 702
 703        pixm->width = frame->o_width;
 704        pixm->height = frame->o_height;
 705        pixm->field = V4L2_FIELD_NONE;
 706        pixm->pixelformat = frame->fmt->fourcc;
 707        pixm->colorspace = V4L2_COLORSPACE_JPEG;
 708        pixm->num_planes = frame->fmt->memplanes;
 709
 710        for (i = 0; i < pixm->num_planes; ++i) {
 711                pixm->plane_fmt[i].bytesperline = frame->bytesperline[i];
 712                pixm->plane_fmt[i].sizeimage = frame->payload[i];
 713        }
 714}
 715
 716/**
 717 * fimc_adjust_mplane_format - adjust bytesperline/sizeimage for each plane
 718 * @fmt: fimc pixel format description (input)
 719 * @width: requested pixel width
 720 * @height: requested pixel height
 721 * @pix: multi-plane format to adjust
 722 */
 723void fimc_adjust_mplane_format(struct fimc_fmt *fmt, u32 width, u32 height,
 724                               struct v4l2_pix_format_mplane *pix)
 725{
 726        u32 bytesperline = 0;
 727        int i;
 728
 729        pix->colorspace = V4L2_COLORSPACE_JPEG;
 730        pix->field = V4L2_FIELD_NONE;
 731        pix->num_planes = fmt->memplanes;
 732        pix->pixelformat = fmt->fourcc;
 733        pix->height = height;
 734        pix->width = width;
 735
 736        for (i = 0; i < pix->num_planes; ++i) {
 737                struct v4l2_plane_pix_format *plane_fmt = &pix->plane_fmt[i];
 738                u32 bpl = plane_fmt->bytesperline;
 739
 740                if (fmt->colplanes > 1 && (bpl == 0 || bpl < pix->width))
 741                        bpl = pix->width; /* Planar */
 742
 743                if (fmt->colplanes == 1 && /* Packed */
 744                    (bpl == 0 || ((bpl * 8) / fmt->depth[i]) < pix->width))
 745                        bpl = (pix->width * fmt->depth[0]) / 8;
 746                /*
 747                 * Currently bytesperline for each plane is same, except
 748                 * V4L2_PIX_FMT_YUV420M format. This calculation may need
 749                 * to be changed when other multi-planar formats are added
 750                 * to the fimc_formats[] array.
 751                 */
 752                if (i == 0)
 753                        bytesperline = bpl;
 754                else if (i == 1 && fmt->memplanes == 3)
 755                        bytesperline /= 2;
 756
 757                plane_fmt->bytesperline = bytesperline;
 758                plane_fmt->sizeimage = max((pix->width * pix->height *
 759                                   fmt->depth[i]) / 8, plane_fmt->sizeimage);
 760        }
 761}
 762
 763/**
 764 * fimc_find_format - lookup fimc color format by fourcc or media bus format
 765 * @pixelformat: fourcc to match, ignored if null
 766 * @mbus_code: media bus code to match, ignored if null
 767 * @mask: the color flags to match
 768 * @index: offset in the fimc_formats array, ignored if negative
 769 */
 770struct fimc_fmt *fimc_find_format(const u32 *pixelformat, const u32 *mbus_code,
 771                                  unsigned int mask, int index)
 772{
 773        struct fimc_fmt *fmt, *def_fmt = NULL;
 774        unsigned int i;
 775        int id = 0;
 776
 777        if (index >= (int)ARRAY_SIZE(fimc_formats))
 778                return NULL;
 779
 780        for (i = 0; i < ARRAY_SIZE(fimc_formats); ++i) {
 781                fmt = &fimc_formats[i];
 782                if (!(fmt->flags & mask))
 783                        continue;
 784                if (pixelformat && fmt->fourcc == *pixelformat)
 785                        return fmt;
 786                if (mbus_code && fmt->mbus_code == *mbus_code)
 787                        return fmt;
 788                if (index == id)
 789                        def_fmt = fmt;
 790                id++;
 791        }
 792        return def_fmt;
 793}
 794
 795static void fimc_clk_put(struct fimc_dev *fimc)
 796{
 797        int i;
 798        for (i = 0; i < MAX_FIMC_CLOCKS; i++) {
 799                if (IS_ERR(fimc->clock[i]))
 800                        continue;
 801                clk_unprepare(fimc->clock[i]);
 802                clk_put(fimc->clock[i]);
 803                fimc->clock[i] = ERR_PTR(-EINVAL);
 804        }
 805}
 806
 807static int fimc_clk_get(struct fimc_dev *fimc)
 808{
 809        int i, ret;
 810
 811        for (i = 0; i < MAX_FIMC_CLOCKS; i++)
 812                fimc->clock[i] = ERR_PTR(-EINVAL);
 813
 814        for (i = 0; i < MAX_FIMC_CLOCKS; i++) {
 815                fimc->clock[i] = clk_get(&fimc->pdev->dev, fimc_clocks[i]);
 816                if (IS_ERR(fimc->clock[i])) {
 817                        ret = PTR_ERR(fimc->clock[i]);
 818                        goto err;
 819                }
 820                ret = clk_prepare(fimc->clock[i]);
 821                if (ret < 0) {
 822                        clk_put(fimc->clock[i]);
 823                        fimc->clock[i] = ERR_PTR(-EINVAL);
 824                        goto err;
 825                }
 826        }
 827        return 0;
 828err:
 829        fimc_clk_put(fimc);
 830        dev_err(&fimc->pdev->dev, "failed to get clock: %s\n",
 831                fimc_clocks[i]);
 832        return -ENXIO;
 833}
 834
 835#if defined(CONFIG_PM_RUNTIME) || defined(CONFIG_PM_SLEEP)
 836static int fimc_m2m_suspend(struct fimc_dev *fimc)
 837{
 838        unsigned long flags;
 839        int timeout;
 840
 841        spin_lock_irqsave(&fimc->slock, flags);
 842        if (!fimc_m2m_pending(fimc)) {
 843                spin_unlock_irqrestore(&fimc->slock, flags);
 844                return 0;
 845        }
 846        clear_bit(ST_M2M_SUSPENDED, &fimc->state);
 847        set_bit(ST_M2M_SUSPENDING, &fimc->state);
 848        spin_unlock_irqrestore(&fimc->slock, flags);
 849
 850        timeout = wait_event_timeout(fimc->irq_queue,
 851                             test_bit(ST_M2M_SUSPENDED, &fimc->state),
 852                             FIMC_SHUTDOWN_TIMEOUT);
 853
 854        clear_bit(ST_M2M_SUSPENDING, &fimc->state);
 855        return timeout == 0 ? -EAGAIN : 0;
 856}
 857
 858static int fimc_m2m_resume(struct fimc_dev *fimc)
 859{
 860        struct fimc_ctx *ctx;
 861        unsigned long flags;
 862
 863        spin_lock_irqsave(&fimc->slock, flags);
 864        /* Clear for full H/W setup in first run after resume */
 865        ctx = fimc->m2m.ctx;
 866        fimc->m2m.ctx = NULL;
 867        spin_unlock_irqrestore(&fimc->slock, flags);
 868
 869        if (test_and_clear_bit(ST_M2M_SUSPENDED, &fimc->state))
 870                fimc_m2m_job_finish(ctx, VB2_BUF_STATE_ERROR);
 871
 872        return 0;
 873}
 874#endif /* CONFIG_PM_RUNTIME || CONFIG_PM_SLEEP */
 875
 876static const struct of_device_id fimc_of_match[];
 877
 878static int fimc_parse_dt(struct fimc_dev *fimc, u32 *clk_freq)
 879{
 880        struct device *dev = &fimc->pdev->dev;
 881        struct device_node *node = dev->of_node;
 882        const struct of_device_id *of_id;
 883        struct fimc_variant *v;
 884        struct fimc_pix_limit *lim;
 885        u32 args[FIMC_PIX_LIMITS_MAX];
 886        int ret;
 887
 888        if (of_property_read_bool(node, "samsung,lcd-wb"))
 889                return -ENODEV;
 890
 891        v = devm_kzalloc(dev, sizeof(*v) + sizeof(*lim), GFP_KERNEL);
 892        if (!v)
 893                return -ENOMEM;
 894
 895        of_id = of_match_node(fimc_of_match, node);
 896        if (!of_id)
 897                return -EINVAL;
 898        fimc->drv_data = of_id->data;
 899        ret = of_property_read_u32_array(node, "samsung,pix-limits",
 900                                         args, FIMC_PIX_LIMITS_MAX);
 901        if (ret < 0)
 902                return ret;
 903
 904        lim = (struct fimc_pix_limit *)&v[1];
 905
 906        lim->scaler_en_w = args[0];
 907        lim->scaler_dis_w = args[1];
 908        lim->out_rot_en_w = args[2];
 909        lim->out_rot_dis_w = args[3];
 910        v->pix_limit = lim;
 911
 912        ret = of_property_read_u32_array(node, "samsung,min-pix-sizes",
 913                                                                args, 2);
 914        v->min_inp_pixsize = ret ? FIMC_DEF_MIN_SIZE : args[0];
 915        v->min_out_pixsize = ret ? FIMC_DEF_MIN_SIZE : args[1];
 916        ret = of_property_read_u32_array(node, "samsung,min-pix-alignment",
 917                                                                args, 2);
 918        v->min_vsize_align = ret ? FIMC_DEF_HEIGHT_ALIGN : args[0];
 919        v->hor_offs_align = ret ? FIMC_DEF_HOR_OFFS_ALIGN : args[1];
 920
 921        ret = of_property_read_u32(node, "samsung,rotators", &args[1]);
 922        v->has_inp_rot = ret ? 1 : args[1] & 0x01;
 923        v->has_out_rot = ret ? 1 : args[1] & 0x10;
 924        v->has_mainscaler_ext = of_property_read_bool(node,
 925                                        "samsung,mainscaler-ext");
 926
 927        v->has_isp_wb = of_property_read_bool(node, "samsung,isp-wb");
 928        v->has_cam_if = of_property_read_bool(node, "samsung,cam-if");
 929        of_property_read_u32(node, "clock-frequency", clk_freq);
 930        fimc->id = of_alias_get_id(node, "fimc");
 931
 932        fimc->variant = v;
 933        return 0;
 934}
 935
 936static int fimc_probe(struct platform_device *pdev)
 937{
 938        struct device *dev = &pdev->dev;
 939        u32 lclk_freq = 0;
 940        struct fimc_dev *fimc;
 941        struct resource *res;
 942        int ret = 0;
 943
 944        fimc = devm_kzalloc(dev, sizeof(*fimc), GFP_KERNEL);
 945        if (!fimc)
 946                return -ENOMEM;
 947
 948        fimc->pdev = pdev;
 949
 950        if (dev->of_node) {
 951                ret = fimc_parse_dt(fimc, &lclk_freq);
 952                if (ret < 0)
 953                        return ret;
 954        } else {
 955                fimc->drv_data = fimc_get_drvdata(pdev);
 956                fimc->id = pdev->id;
 957        }
 958        if (!fimc->drv_data || fimc->id >= fimc->drv_data->num_entities ||
 959            fimc->id < 0) {
 960                dev_err(dev, "Invalid driver data or device id (%d)\n",
 961                        fimc->id);
 962                return -EINVAL;
 963        }
 964        if (!dev->of_node)
 965                fimc->variant = fimc->drv_data->variant[fimc->id];
 966
 967        init_waitqueue_head(&fimc->irq_queue);
 968        spin_lock_init(&fimc->slock);
 969        mutex_init(&fimc->lock);
 970
 971        fimc->sysreg = fimc_get_sysreg_regmap(dev->of_node);
 972        if (IS_ERR(fimc->sysreg))
 973                return PTR_ERR(fimc->sysreg);
 974
 975        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 976        fimc->regs = devm_ioremap_resource(dev, res);
 977        if (IS_ERR(fimc->regs))
 978                return PTR_ERR(fimc->regs);
 979
 980        res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 981        if (res == NULL) {
 982                dev_err(dev, "Failed to get IRQ resource\n");
 983                return -ENXIO;
 984        }
 985
 986        ret = fimc_clk_get(fimc);
 987        if (ret)
 988                return ret;
 989
 990        if (lclk_freq == 0)
 991                lclk_freq = fimc->drv_data->lclk_frequency;
 992
 993        ret = clk_set_rate(fimc->clock[CLK_BUS], lclk_freq);
 994        if (ret < 0)
 995                return ret;
 996
 997        ret = clk_enable(fimc->clock[CLK_BUS]);
 998        if (ret < 0)
 999                return ret;
1000
1001        ret = devm_request_irq(dev, res->start, fimc_irq_handler,
1002                               0, dev_name(dev), fimc);
1003        if (ret < 0) {
1004                dev_err(dev, "failed to install irq (%d)\n", ret);
1005                goto err_sclk;
1006        }
1007
1008        ret = fimc_initialize_capture_subdev(fimc);
1009        if (ret < 0)
1010                goto err_sclk;
1011
1012        platform_set_drvdata(pdev, fimc);
1013        pm_runtime_enable(dev);
1014
1015        if (!pm_runtime_enabled(dev)) {
1016                ret = clk_enable(fimc->clock[CLK_GATE]);
1017                if (ret < 0)
1018                        goto err_sd;
1019        }
1020
1021        /* Initialize contiguous memory allocator */
1022        fimc->alloc_ctx = vb2_dma_contig_init_ctx(dev);
1023        if (IS_ERR(fimc->alloc_ctx)) {
1024                ret = PTR_ERR(fimc->alloc_ctx);
1025                goto err_gclk;
1026        }
1027
1028        dev_dbg(dev, "FIMC.%d registered successfully\n", fimc->id);
1029        return 0;
1030
1031err_gclk:
1032        if (!pm_runtime_enabled(dev))
1033                clk_disable(fimc->clock[CLK_GATE]);
1034err_sd:
1035        fimc_unregister_capture_subdev(fimc);
1036err_sclk:
1037        clk_disable(fimc->clock[CLK_BUS]);
1038        fimc_clk_put(fimc);
1039        return ret;
1040}
1041
1042#ifdef CONFIG_PM_RUNTIME
1043static int fimc_runtime_resume(struct device *dev)
1044{
1045        struct fimc_dev *fimc = dev_get_drvdata(dev);
1046
1047        dbg("fimc%d: state: 0x%lx", fimc->id, fimc->state);
1048
1049        /* Enable clocks and perform basic initialization */
1050        clk_enable(fimc->clock[CLK_GATE]);
1051        fimc_hw_reset(fimc);
1052
1053        /* Resume the capture or mem-to-mem device */
1054        if (fimc_capture_busy(fimc))
1055                return fimc_capture_resume(fimc);
1056
1057        return fimc_m2m_resume(fimc);
1058}
1059
1060static int fimc_runtime_suspend(struct device *dev)
1061{
1062        struct fimc_dev *fimc = dev_get_drvdata(dev);
1063        int ret = 0;
1064
1065        if (fimc_capture_busy(fimc))
1066                ret = fimc_capture_suspend(fimc);
1067        else
1068                ret = fimc_m2m_suspend(fimc);
1069        if (!ret)
1070                clk_disable(fimc->clock[CLK_GATE]);
1071
1072        dbg("fimc%d: state: 0x%lx", fimc->id, fimc->state);
1073        return ret;
1074}
1075#endif
1076
1077#ifdef CONFIG_PM_SLEEP
1078static int fimc_resume(struct device *dev)
1079{
1080        struct fimc_dev *fimc = dev_get_drvdata(dev);
1081        unsigned long flags;
1082
1083        dbg("fimc%d: state: 0x%lx", fimc->id, fimc->state);
1084
1085        /* Do not resume if the device was idle before system suspend */
1086        spin_lock_irqsave(&fimc->slock, flags);
1087        if (!test_and_clear_bit(ST_LPM, &fimc->state) ||
1088            (!fimc_m2m_active(fimc) && !fimc_capture_busy(fimc))) {
1089                spin_unlock_irqrestore(&fimc->slock, flags);
1090                return 0;
1091        }
1092        fimc_hw_reset(fimc);
1093        spin_unlock_irqrestore(&fimc->slock, flags);
1094
1095        if (fimc_capture_busy(fimc))
1096                return fimc_capture_resume(fimc);
1097
1098        return fimc_m2m_resume(fimc);
1099}
1100
1101static int fimc_suspend(struct device *dev)
1102{
1103        struct fimc_dev *fimc = dev_get_drvdata(dev);
1104
1105        dbg("fimc%d: state: 0x%lx", fimc->id, fimc->state);
1106
1107        if (test_and_set_bit(ST_LPM, &fimc->state))
1108                return 0;
1109        if (fimc_capture_busy(fimc))
1110                return fimc_capture_suspend(fimc);
1111
1112        return fimc_m2m_suspend(fimc);
1113}
1114#endif /* CONFIG_PM_SLEEP */
1115
1116static int fimc_remove(struct platform_device *pdev)
1117{
1118        struct fimc_dev *fimc = platform_get_drvdata(pdev);
1119
1120        pm_runtime_disable(&pdev->dev);
1121        if (!pm_runtime_status_suspended(&pdev->dev))
1122                clk_disable(fimc->clock[CLK_GATE]);
1123        pm_runtime_set_suspended(&pdev->dev);
1124
1125        fimc_unregister_capture_subdev(fimc);
1126        vb2_dma_contig_cleanup_ctx(fimc->alloc_ctx);
1127
1128        clk_disable(fimc->clock[CLK_BUS]);
1129        fimc_clk_put(fimc);
1130
1131        dev_info(&pdev->dev, "driver unloaded\n");
1132        return 0;
1133}
1134
1135/* Image pixel limits, similar across several FIMC HW revisions. */
1136static const struct fimc_pix_limit s5p_pix_limit[4] = {
1137        [0] = {
1138                .scaler_en_w    = 3264,
1139                .scaler_dis_w   = 8192,
1140                .out_rot_en_w   = 1920,
1141                .out_rot_dis_w  = 4224,
1142        },
1143        [1] = {
1144                .scaler_en_w    = 4224,
1145                .scaler_dis_w   = 8192,
1146                .out_rot_en_w   = 1920,
1147                .out_rot_dis_w  = 4224,
1148        },
1149        [2] = {
1150                .scaler_en_w    = 1920,
1151                .scaler_dis_w   = 8192,
1152                .out_rot_en_w   = 1280,
1153                .out_rot_dis_w  = 1920,
1154        },
1155};
1156
1157static const struct fimc_variant fimc0_variant_s5p = {
1158        .has_inp_rot     = 1,
1159        .has_out_rot     = 1,
1160        .has_cam_if      = 1,
1161        .min_inp_pixsize = 16,
1162        .min_out_pixsize = 16,
1163        .hor_offs_align  = 8,
1164        .min_vsize_align = 16,
1165        .pix_limit       = &s5p_pix_limit[0],
1166};
1167
1168static const struct fimc_variant fimc2_variant_s5p = {
1169        .has_cam_if      = 1,
1170        .min_inp_pixsize = 16,
1171        .min_out_pixsize = 16,
1172        .hor_offs_align  = 8,
1173        .min_vsize_align = 16,
1174        .pix_limit       = &s5p_pix_limit[1],
1175};
1176
1177static const struct fimc_variant fimc0_variant_s5pv210 = {
1178        .has_inp_rot     = 1,
1179        .has_out_rot     = 1,
1180        .has_cam_if      = 1,
1181        .min_inp_pixsize = 16,
1182        .min_out_pixsize = 16,
1183        .hor_offs_align  = 8,
1184        .min_vsize_align = 16,
1185        .pix_limit       = &s5p_pix_limit[1],
1186};
1187
1188static const struct fimc_variant fimc1_variant_s5pv210 = {
1189        .has_inp_rot     = 1,
1190        .has_out_rot     = 1,
1191        .has_cam_if      = 1,
1192        .has_mainscaler_ext = 1,
1193        .min_inp_pixsize = 16,
1194        .min_out_pixsize = 16,
1195        .hor_offs_align  = 1,
1196        .min_vsize_align = 1,
1197        .pix_limit       = &s5p_pix_limit[2],
1198};
1199
1200static const struct fimc_variant fimc2_variant_s5pv210 = {
1201        .has_cam_if      = 1,
1202        .min_inp_pixsize = 16,
1203        .min_out_pixsize = 16,
1204        .hor_offs_align  = 8,
1205        .min_vsize_align = 16,
1206        .pix_limit       = &s5p_pix_limit[2],
1207};
1208
1209/* S5PC100 */
1210static const struct fimc_drvdata fimc_drvdata_s5p = {
1211        .variant = {
1212                [0] = &fimc0_variant_s5p,
1213                [1] = &fimc0_variant_s5p,
1214                [2] = &fimc2_variant_s5p,
1215        },
1216        .num_entities   = 3,
1217        .lclk_frequency = 133000000UL,
1218        .out_buf_count  = 4,
1219};
1220
1221/* S5PV210, S5PC110 */
1222static const struct fimc_drvdata fimc_drvdata_s5pv210 = {
1223        .variant = {
1224                [0] = &fimc0_variant_s5pv210,
1225                [1] = &fimc1_variant_s5pv210,
1226                [2] = &fimc2_variant_s5pv210,
1227        },
1228        .num_entities   = 3,
1229        .lclk_frequency = 166000000UL,
1230        .out_buf_count  = 4,
1231        .dma_pix_hoff   = 1,
1232};
1233
1234/* EXYNOS4210, S5PV310, S5PC210 */
1235static const struct fimc_drvdata fimc_drvdata_exynos4210 = {
1236        .num_entities   = 4,
1237        .lclk_frequency = 166000000UL,
1238        .dma_pix_hoff   = 1,
1239        .cistatus2      = 1,
1240        .alpha_color    = 1,
1241        .out_buf_count  = 32,
1242};
1243
1244/* EXYNOS4212, EXYNOS4412 */
1245static const struct fimc_drvdata fimc_drvdata_exynos4x12 = {
1246        .num_entities   = 4,
1247        .lclk_frequency = 166000000UL,
1248        .dma_pix_hoff   = 1,
1249        .cistatus2      = 1,
1250        .alpha_color    = 1,
1251        .out_buf_count  = 32,
1252};
1253
1254static const struct platform_device_id fimc_driver_ids[] = {
1255        {
1256                .name           = "s5p-fimc",
1257                .driver_data    = (unsigned long)&fimc_drvdata_s5p,
1258        }, {
1259                .name           = "s5pv210-fimc",
1260                .driver_data    = (unsigned long)&fimc_drvdata_s5pv210,
1261        }, {
1262                .name           = "exynos4-fimc",
1263                .driver_data    = (unsigned long)&fimc_drvdata_exynos4210,
1264        }, {
1265                .name           = "exynos4x12-fimc",
1266                .driver_data    = (unsigned long)&fimc_drvdata_exynos4x12,
1267        },
1268        { },
1269};
1270
1271static const struct of_device_id fimc_of_match[] = {
1272        {
1273                .compatible = "samsung,s5pv210-fimc",
1274                .data = &fimc_drvdata_s5pv210,
1275        }, {
1276                .compatible = "samsung,exynos4210-fimc",
1277                .data = &fimc_drvdata_exynos4210,
1278        }, {
1279                .compatible = "samsung,exynos4212-fimc",
1280                .data = &fimc_drvdata_exynos4x12,
1281        },
1282        { /* sentinel */ },
1283};
1284
1285static const struct dev_pm_ops fimc_pm_ops = {
1286        SET_SYSTEM_SLEEP_PM_OPS(fimc_suspend, fimc_resume)
1287        SET_RUNTIME_PM_OPS(fimc_runtime_suspend, fimc_runtime_resume, NULL)
1288};
1289
1290static struct platform_driver fimc_driver = {
1291        .probe          = fimc_probe,
1292        .remove         = fimc_remove,
1293        .id_table       = fimc_driver_ids,
1294        .driver = {
1295                .of_match_table = fimc_of_match,
1296                .name           = FIMC_DRIVER_NAME,
1297                .owner          = THIS_MODULE,
1298                .pm             = &fimc_pm_ops,
1299        }
1300};
1301
1302int __init fimc_register_driver(void)
1303{
1304        return platform_driver_register(&fimc_driver);
1305}
1306
1307void __exit fimc_unregister_driver(void)
1308{
1309        platform_driver_unregister(&fimc_driver);
1310}
1311