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15#include <linux/delay.h>
16#include <linux/dma-mapping.h>
17#include <linux/platform_device.h>
18#include <linux/platform_data/mmc-sdhci-s3c.h>
19#include <linux/slab.h>
20#include <linux/clk.h>
21#include <linux/io.h>
22#include <linux/gpio.h>
23#include <linux/module.h>
24#include <linux/of.h>
25#include <linux/of_gpio.h>
26#include <linux/pm.h>
27#include <linux/pm_runtime.h>
28
29#include <linux/mmc/host.h>
30
31#include "sdhci-s3c-regs.h"
32#include "sdhci.h"
33
34#define MAX_BUS_CLK (4)
35
36
37
38
39
40
41
42
43
44
45
46struct sdhci_s3c {
47 struct sdhci_host *host;
48 struct platform_device *pdev;
49 struct resource *ioarea;
50 struct s3c_sdhci_platdata *pdata;
51 int cur_clk;
52 int ext_cd_irq;
53 int ext_cd_gpio;
54
55 struct clk *clk_io;
56 struct clk *clk_bus[MAX_BUS_CLK];
57 unsigned long clk_rates[MAX_BUS_CLK];
58
59 bool no_divider;
60};
61
62
63
64
65
66
67
68
69
70struct sdhci_s3c_drv_data {
71 unsigned int sdhci_quirks;
72 bool no_divider;
73};
74
75static inline struct sdhci_s3c *to_s3c(struct sdhci_host *host)
76{
77 return sdhci_priv(host);
78}
79
80
81
82
83
84
85
86static unsigned int sdhci_s3c_get_max_clk(struct sdhci_host *host)
87{
88 struct sdhci_s3c *ourhost = to_s3c(host);
89 unsigned long rate, max = 0;
90 int src;
91
92 for (src = 0; src < MAX_BUS_CLK; src++) {
93 rate = ourhost->clk_rates[src];
94 if (rate > max)
95 max = rate;
96 }
97
98 return max;
99}
100
101
102
103
104
105
106
107static unsigned int sdhci_s3c_consider_clock(struct sdhci_s3c *ourhost,
108 unsigned int src,
109 unsigned int wanted)
110{
111 unsigned long rate;
112 struct clk *clksrc = ourhost->clk_bus[src];
113 int shift;
114
115 if (IS_ERR(clksrc))
116 return UINT_MAX;
117
118
119
120
121
122 if (ourhost->no_divider) {
123 rate = clk_round_rate(clksrc, wanted);
124 return wanted - rate;
125 }
126
127 rate = ourhost->clk_rates[src];
128
129 for (shift = 0; shift <= 8; ++shift) {
130 if ((rate >> shift) <= wanted)
131 break;
132 }
133
134 if (shift > 8) {
135 dev_dbg(&ourhost->pdev->dev,
136 "clk %d: rate %ld, min rate %lu > wanted %u\n",
137 src, rate, rate / 256, wanted);
138 return UINT_MAX;
139 }
140
141 dev_dbg(&ourhost->pdev->dev, "clk %d: rate %ld, want %d, got %ld\n",
142 src, rate, wanted, rate >> shift);
143
144 return wanted - (rate >> shift);
145}
146
147
148
149
150
151
152
153
154
155static void sdhci_s3c_set_clock(struct sdhci_host *host, unsigned int clock)
156{
157 struct sdhci_s3c *ourhost = to_s3c(host);
158 unsigned int best = UINT_MAX;
159 unsigned int delta;
160 int best_src = 0;
161 int src;
162 u32 ctrl;
163
164 host->mmc->actual_clock = 0;
165
166
167 if (clock == 0) {
168 sdhci_set_clock(host, clock);
169 return;
170 }
171
172 for (src = 0; src < MAX_BUS_CLK; src++) {
173 delta = sdhci_s3c_consider_clock(ourhost, src, clock);
174 if (delta < best) {
175 best = delta;
176 best_src = src;
177 }
178 }
179
180 dev_dbg(&ourhost->pdev->dev,
181 "selected source %d, clock %d, delta %d\n",
182 best_src, clock, best);
183
184
185 if (ourhost->cur_clk != best_src) {
186 struct clk *clk = ourhost->clk_bus[best_src];
187
188 clk_prepare_enable(clk);
189 if (ourhost->cur_clk >= 0)
190 clk_disable_unprepare(
191 ourhost->clk_bus[ourhost->cur_clk]);
192
193 ourhost->cur_clk = best_src;
194 host->max_clk = ourhost->clk_rates[best_src];
195 }
196
197
198 writew(0, host->ioaddr + SDHCI_CLOCK_CONTROL);
199
200 ctrl = readl(host->ioaddr + S3C_SDHCI_CONTROL2);
201 ctrl &= ~S3C_SDHCI_CTRL2_SELBASECLK_MASK;
202 ctrl |= best_src << S3C_SDHCI_CTRL2_SELBASECLK_SHIFT;
203 writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL2);
204
205
206 writel(S3C64XX_SDHCI_CONTROL4_DRIVE_9mA,
207 host->ioaddr + S3C64XX_SDHCI_CONTROL4);
208
209 ctrl = readl(host->ioaddr + S3C_SDHCI_CONTROL2);
210 ctrl |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR |
211 S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK |
212 S3C_SDHCI_CTRL2_ENFBCLKRX |
213 S3C_SDHCI_CTRL2_DFCNT_NONE |
214 S3C_SDHCI_CTRL2_ENCLKOUTHOLD);
215 writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL2);
216
217
218 ctrl = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0);
219 if (clock < 25 * 1000000)
220 ctrl |= (S3C_SDHCI_CTRL3_FCSEL3 | S3C_SDHCI_CTRL3_FCSEL2);
221 writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL3);
222
223 sdhci_set_clock(host, clock);
224}
225
226
227
228
229
230
231
232
233
234
235static unsigned int sdhci_s3c_get_min_clock(struct sdhci_host *host)
236{
237 struct sdhci_s3c *ourhost = to_s3c(host);
238 unsigned long rate, min = ULONG_MAX;
239 int src;
240
241 for (src = 0; src < MAX_BUS_CLK; src++) {
242 rate = ourhost->clk_rates[src] / 256;
243 if (!rate)
244 continue;
245 if (rate < min)
246 min = rate;
247 }
248
249 return min;
250}
251
252
253static unsigned int sdhci_cmu_get_max_clock(struct sdhci_host *host)
254{
255 struct sdhci_s3c *ourhost = to_s3c(host);
256 unsigned long rate, max = 0;
257 int src;
258
259 for (src = 0; src < MAX_BUS_CLK; src++) {
260 struct clk *clk;
261
262 clk = ourhost->clk_bus[src];
263 if (IS_ERR(clk))
264 continue;
265
266 rate = clk_round_rate(clk, ULONG_MAX);
267 if (rate > max)
268 max = rate;
269 }
270
271 return max;
272}
273
274
275static unsigned int sdhci_cmu_get_min_clock(struct sdhci_host *host)
276{
277 struct sdhci_s3c *ourhost = to_s3c(host);
278 unsigned long rate, min = ULONG_MAX;
279 int src;
280
281 for (src = 0; src < MAX_BUS_CLK; src++) {
282 struct clk *clk;
283
284 clk = ourhost->clk_bus[src];
285 if (IS_ERR(clk))
286 continue;
287
288 rate = clk_round_rate(clk, 0);
289 if (rate < min)
290 min = rate;
291 }
292
293 return min;
294}
295
296
297static void sdhci_cmu_set_clock(struct sdhci_host *host, unsigned int clock)
298{
299 struct sdhci_s3c *ourhost = to_s3c(host);
300 struct device *dev = &ourhost->pdev->dev;
301 unsigned long timeout;
302 u16 clk = 0;
303
304 host->mmc->actual_clock = 0;
305
306
307 if (clock == 0) {
308 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
309 return;
310 }
311
312 sdhci_s3c_set_clock(host, clock);
313
314 clk_set_rate(ourhost->clk_bus[ourhost->cur_clk], clock);
315
316 clk = SDHCI_CLOCK_INT_EN;
317 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
318
319
320 timeout = 20;
321 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
322 & SDHCI_CLOCK_INT_STABLE)) {
323 if (timeout == 0) {
324 dev_err(dev, "%s: Internal clock never stabilised.\n",
325 mmc_hostname(host->mmc));
326 return;
327 }
328 timeout--;
329 mdelay(1);
330 }
331
332 clk |= SDHCI_CLOCK_CARD_EN;
333 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
334}
335
336
337
338
339
340
341
342
343
344static void sdhci_s3c_set_bus_width(struct sdhci_host *host, int width)
345{
346 u8 ctrl;
347
348 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
349
350 switch (width) {
351 case MMC_BUS_WIDTH_8:
352 ctrl |= SDHCI_CTRL_8BITBUS;
353 ctrl &= ~SDHCI_CTRL_4BITBUS;
354 break;
355 case MMC_BUS_WIDTH_4:
356 ctrl |= SDHCI_CTRL_4BITBUS;
357 ctrl &= ~SDHCI_CTRL_8BITBUS;
358 break;
359 default:
360 ctrl &= ~SDHCI_CTRL_4BITBUS;
361 ctrl &= ~SDHCI_CTRL_8BITBUS;
362 break;
363 }
364
365 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
366}
367
368static struct sdhci_ops sdhci_s3c_ops = {
369 .get_max_clock = sdhci_s3c_get_max_clk,
370 .set_clock = sdhci_s3c_set_clock,
371 .get_min_clock = sdhci_s3c_get_min_clock,
372 .set_bus_width = sdhci_s3c_set_bus_width,
373 .reset = sdhci_reset,
374 .set_uhs_signaling = sdhci_set_uhs_signaling,
375};
376
377#ifdef CONFIG_OF
378static int sdhci_s3c_parse_dt(struct device *dev,
379 struct sdhci_host *host, struct s3c_sdhci_platdata *pdata)
380{
381 struct device_node *node = dev->of_node;
382 u32 max_width;
383
384
385 if (of_property_read_u32(node, "bus-width", &max_width))
386 max_width = 1;
387 pdata->max_width = max_width;
388
389
390 if (of_get_property(node, "broken-cd", NULL)) {
391 pdata->cd_type = S3C_SDHCI_CD_NONE;
392 return 0;
393 }
394
395 if (of_get_property(node, "non-removable", NULL)) {
396 pdata->cd_type = S3C_SDHCI_CD_PERMANENT;
397 return 0;
398 }
399
400 if (of_get_named_gpio(node, "cd-gpios", 0))
401 return 0;
402
403
404 pdata->cd_type = S3C_SDHCI_CD_INTERNAL;
405 return 0;
406}
407#else
408static int sdhci_s3c_parse_dt(struct device *dev,
409 struct sdhci_host *host, struct s3c_sdhci_platdata *pdata)
410{
411 return -EINVAL;
412}
413#endif
414
415static const struct of_device_id sdhci_s3c_dt_match[];
416
417static inline struct sdhci_s3c_drv_data *sdhci_s3c_get_driver_data(
418 struct platform_device *pdev)
419{
420#ifdef CONFIG_OF
421 if (pdev->dev.of_node) {
422 const struct of_device_id *match;
423 match = of_match_node(sdhci_s3c_dt_match, pdev->dev.of_node);
424 return (struct sdhci_s3c_drv_data *)match->data;
425 }
426#endif
427 return (struct sdhci_s3c_drv_data *)
428 platform_get_device_id(pdev)->driver_data;
429}
430
431static int sdhci_s3c_probe(struct platform_device *pdev)
432{
433 struct s3c_sdhci_platdata *pdata;
434 struct sdhci_s3c_drv_data *drv_data;
435 struct device *dev = &pdev->dev;
436 struct sdhci_host *host;
437 struct sdhci_s3c *sc;
438 struct resource *res;
439 int ret, irq, ptr, clks;
440
441 if (!pdev->dev.platform_data && !pdev->dev.of_node) {
442 dev_err(dev, "no device data specified\n");
443 return -ENOENT;
444 }
445
446 irq = platform_get_irq(pdev, 0);
447 if (irq < 0) {
448 dev_err(dev, "no irq specified\n");
449 return irq;
450 }
451
452 host = sdhci_alloc_host(dev, sizeof(struct sdhci_s3c));
453 if (IS_ERR(host)) {
454 dev_err(dev, "sdhci_alloc_host() failed\n");
455 return PTR_ERR(host);
456 }
457 sc = sdhci_priv(host);
458
459 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
460 if (!pdata) {
461 ret = -ENOMEM;
462 goto err_pdata_io_clk;
463 }
464
465 if (pdev->dev.of_node) {
466 ret = sdhci_s3c_parse_dt(&pdev->dev, host, pdata);
467 if (ret)
468 goto err_pdata_io_clk;
469 } else {
470 memcpy(pdata, pdev->dev.platform_data, sizeof(*pdata));
471 sc->ext_cd_gpio = -1;
472 }
473
474 drv_data = sdhci_s3c_get_driver_data(pdev);
475
476 sc->host = host;
477 sc->pdev = pdev;
478 sc->pdata = pdata;
479 sc->cur_clk = -1;
480
481 platform_set_drvdata(pdev, host);
482
483 sc->clk_io = devm_clk_get(dev, "hsmmc");
484 if (IS_ERR(sc->clk_io)) {
485 dev_err(dev, "failed to get io clock\n");
486 ret = PTR_ERR(sc->clk_io);
487 goto err_pdata_io_clk;
488 }
489
490
491 clk_prepare_enable(sc->clk_io);
492
493 for (clks = 0, ptr = 0; ptr < MAX_BUS_CLK; ptr++) {
494 char name[14];
495
496 snprintf(name, 14, "mmc_busclk.%d", ptr);
497 sc->clk_bus[ptr] = devm_clk_get(dev, name);
498 if (IS_ERR(sc->clk_bus[ptr]))
499 continue;
500
501 clks++;
502 sc->clk_rates[ptr] = clk_get_rate(sc->clk_bus[ptr]);
503
504 dev_info(dev, "clock source %d: %s (%ld Hz)\n",
505 ptr, name, sc->clk_rates[ptr]);
506 }
507
508 if (clks == 0) {
509 dev_err(dev, "failed to find any bus clocks\n");
510 ret = -ENOENT;
511 goto err_no_busclks;
512 }
513
514 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
515 host->ioaddr = devm_ioremap_resource(&pdev->dev, res);
516 if (IS_ERR(host->ioaddr)) {
517 ret = PTR_ERR(host->ioaddr);
518 goto err_req_regs;
519 }
520
521
522 if (pdata->cfg_gpio)
523 pdata->cfg_gpio(pdev, pdata->max_width);
524
525 host->hw_name = "samsung-hsmmc";
526 host->ops = &sdhci_s3c_ops;
527 host->quirks = 0;
528 host->quirks2 = 0;
529 host->irq = irq;
530
531
532 host->quirks |= SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC;
533 host->quirks |= SDHCI_QUIRK_NO_HISPD_BIT;
534 if (drv_data) {
535 host->quirks |= drv_data->sdhci_quirks;
536 sc->no_divider = drv_data->no_divider;
537 }
538
539#ifndef CONFIG_MMC_SDHCI_S3C_DMA
540
541
542
543 host->quirks |= SDHCI_QUIRK_BROKEN_DMA;
544
545#endif
546
547
548
549
550 host->quirks |= SDHCI_QUIRK_NO_BUSY_IRQ;
551
552
553 host->quirks |= SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12;
554
555
556 host->quirks |= SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC;
557
558 if (pdata->cd_type == S3C_SDHCI_CD_NONE ||
559 pdata->cd_type == S3C_SDHCI_CD_PERMANENT)
560 host->quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION;
561
562 if (pdata->cd_type == S3C_SDHCI_CD_PERMANENT)
563 host->mmc->caps = MMC_CAP_NONREMOVABLE;
564
565 switch (pdata->max_width) {
566 case 8:
567 host->mmc->caps |= MMC_CAP_8_BIT_DATA;
568 case 4:
569 host->mmc->caps |= MMC_CAP_4_BIT_DATA;
570 break;
571 }
572
573 if (pdata->pm_caps)
574 host->mmc->pm_caps |= pdata->pm_caps;
575
576 host->quirks |= (SDHCI_QUIRK_32BIT_DMA_ADDR |
577 SDHCI_QUIRK_32BIT_DMA_SIZE);
578
579
580 host->quirks |= SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK;
581
582
583
584
585
586 if (sc->no_divider) {
587 sdhci_s3c_ops.set_clock = sdhci_cmu_set_clock;
588 sdhci_s3c_ops.get_min_clock = sdhci_cmu_get_min_clock;
589 sdhci_s3c_ops.get_max_clock = sdhci_cmu_get_max_clock;
590 }
591
592
593 if (pdata->host_caps)
594 host->mmc->caps |= pdata->host_caps;
595
596 if (pdata->host_caps2)
597 host->mmc->caps2 |= pdata->host_caps2;
598
599 pm_runtime_enable(&pdev->dev);
600 pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
601 pm_runtime_use_autosuspend(&pdev->dev);
602 pm_suspend_ignore_children(&pdev->dev, 1);
603
604 mmc_of_parse(host->mmc);
605
606 ret = sdhci_add_host(host);
607 if (ret) {
608 dev_err(dev, "sdhci_add_host() failed\n");
609 goto err_req_regs;
610 }
611
612#ifdef CONFIG_PM_RUNTIME
613 if (pdata->cd_type != S3C_SDHCI_CD_INTERNAL)
614 clk_disable_unprepare(sc->clk_io);
615#endif
616 return 0;
617
618 err_req_regs:
619 pm_runtime_disable(&pdev->dev);
620
621 err_no_busclks:
622 clk_disable_unprepare(sc->clk_io);
623
624 err_pdata_io_clk:
625 sdhci_free_host(host);
626
627 return ret;
628}
629
630static int sdhci_s3c_remove(struct platform_device *pdev)
631{
632 struct sdhci_host *host = platform_get_drvdata(pdev);
633 struct sdhci_s3c *sc = sdhci_priv(host);
634
635 if (sc->ext_cd_irq)
636 free_irq(sc->ext_cd_irq, sc);
637
638#ifdef CONFIG_PM_RUNTIME
639 if (sc->pdata->cd_type != S3C_SDHCI_CD_INTERNAL)
640 clk_prepare_enable(sc->clk_io);
641#endif
642 sdhci_remove_host(host, 1);
643
644 pm_runtime_dont_use_autosuspend(&pdev->dev);
645 pm_runtime_disable(&pdev->dev);
646
647 clk_disable_unprepare(sc->clk_io);
648
649 sdhci_free_host(host);
650
651 return 0;
652}
653
654#ifdef CONFIG_PM_SLEEP
655static int sdhci_s3c_suspend(struct device *dev)
656{
657 struct sdhci_host *host = dev_get_drvdata(dev);
658
659 return sdhci_suspend_host(host);
660}
661
662static int sdhci_s3c_resume(struct device *dev)
663{
664 struct sdhci_host *host = dev_get_drvdata(dev);
665
666 return sdhci_resume_host(host);
667}
668#endif
669
670#ifdef CONFIG_PM_RUNTIME
671static int sdhci_s3c_runtime_suspend(struct device *dev)
672{
673 struct sdhci_host *host = dev_get_drvdata(dev);
674 struct sdhci_s3c *ourhost = to_s3c(host);
675 struct clk *busclk = ourhost->clk_io;
676 int ret;
677
678 ret = sdhci_runtime_suspend_host(host);
679
680 if (ourhost->cur_clk >= 0)
681 clk_disable_unprepare(ourhost->clk_bus[ourhost->cur_clk]);
682 clk_disable_unprepare(busclk);
683 return ret;
684}
685
686static int sdhci_s3c_runtime_resume(struct device *dev)
687{
688 struct sdhci_host *host = dev_get_drvdata(dev);
689 struct sdhci_s3c *ourhost = to_s3c(host);
690 struct clk *busclk = ourhost->clk_io;
691 int ret;
692
693 clk_prepare_enable(busclk);
694 if (ourhost->cur_clk >= 0)
695 clk_prepare_enable(ourhost->clk_bus[ourhost->cur_clk]);
696 ret = sdhci_runtime_resume_host(host);
697 return ret;
698}
699#endif
700
701#ifdef CONFIG_PM
702static const struct dev_pm_ops sdhci_s3c_pmops = {
703 SET_SYSTEM_SLEEP_PM_OPS(sdhci_s3c_suspend, sdhci_s3c_resume)
704 SET_RUNTIME_PM_OPS(sdhci_s3c_runtime_suspend, sdhci_s3c_runtime_resume,
705 NULL)
706};
707
708#define SDHCI_S3C_PMOPS (&sdhci_s3c_pmops)
709
710#else
711#define SDHCI_S3C_PMOPS NULL
712#endif
713
714#if defined(CONFIG_CPU_EXYNOS4210) || defined(CONFIG_SOC_EXYNOS4212)
715static struct sdhci_s3c_drv_data exynos4_sdhci_drv_data = {
716 .no_divider = true,
717};
718#define EXYNOS4_SDHCI_DRV_DATA ((kernel_ulong_t)&exynos4_sdhci_drv_data)
719#else
720#define EXYNOS4_SDHCI_DRV_DATA ((kernel_ulong_t)NULL)
721#endif
722
723static struct platform_device_id sdhci_s3c_driver_ids[] = {
724 {
725 .name = "s3c-sdhci",
726 .driver_data = (kernel_ulong_t)NULL,
727 }, {
728 .name = "exynos4-sdhci",
729 .driver_data = EXYNOS4_SDHCI_DRV_DATA,
730 },
731 { }
732};
733MODULE_DEVICE_TABLE(platform, sdhci_s3c_driver_ids);
734
735#ifdef CONFIG_OF
736static const struct of_device_id sdhci_s3c_dt_match[] = {
737 { .compatible = "samsung,s3c6410-sdhci", },
738 { .compatible = "samsung,exynos4210-sdhci",
739 .data = (void *)EXYNOS4_SDHCI_DRV_DATA },
740 {},
741};
742MODULE_DEVICE_TABLE(of, sdhci_s3c_dt_match);
743#endif
744
745static struct platform_driver sdhci_s3c_driver = {
746 .probe = sdhci_s3c_probe,
747 .remove = sdhci_s3c_remove,
748 .id_table = sdhci_s3c_driver_ids,
749 .driver = {
750 .name = "s3c-sdhci",
751 .of_match_table = of_match_ptr(sdhci_s3c_dt_match),
752 .pm = SDHCI_S3C_PMOPS,
753 },
754};
755
756module_platform_driver(sdhci_s3c_driver);
757
758MODULE_DESCRIPTION("Samsung SDHCI (HSMMC) glue");
759MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
760MODULE_LICENSE("GPL v2");
761MODULE_ALIAS("platform:s3c-sdhci");
762