1/* 2 * NAND Flash Controller Device Driver 3 * Copyright (c) 2009 - 2010, Intel Corporation and its suppliers. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms and conditions of the GNU General Public License, 7 * version 2, as published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program; if not, write to the Free Software Foundation, Inc., 16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 17 * 18 */ 19 20#ifndef __DENALI_H__ 21#define __DENALI_H__ 22 23#include <linux/mtd/nand.h> 24 25#define DEVICE_RESET 0x0 26#define DEVICE_RESET__BANK0 0x0001 27#define DEVICE_RESET__BANK1 0x0002 28#define DEVICE_RESET__BANK2 0x0004 29#define DEVICE_RESET__BANK3 0x0008 30 31#define TRANSFER_SPARE_REG 0x10 32#define TRANSFER_SPARE_REG__FLAG 0x0001 33 34#define LOAD_WAIT_CNT 0x20 35#define LOAD_WAIT_CNT__VALUE 0xffff 36 37#define PROGRAM_WAIT_CNT 0x30 38#define PROGRAM_WAIT_CNT__VALUE 0xffff 39 40#define ERASE_WAIT_CNT 0x40 41#define ERASE_WAIT_CNT__VALUE 0xffff 42 43#define INT_MON_CYCCNT 0x50 44#define INT_MON_CYCCNT__VALUE 0xffff 45 46#define RB_PIN_ENABLED 0x60 47#define RB_PIN_ENABLED__BANK0 0x0001 48#define RB_PIN_ENABLED__BANK1 0x0002 49#define RB_PIN_ENABLED__BANK2 0x0004 50#define RB_PIN_ENABLED__BANK3 0x0008 51 52#define MULTIPLANE_OPERATION 0x70 53#define MULTIPLANE_OPERATION__FLAG 0x0001 54 55#define MULTIPLANE_READ_ENABLE 0x80 56#define MULTIPLANE_READ_ENABLE__FLAG 0x0001 57 58#define COPYBACK_DISABLE 0x90 59#define COPYBACK_DISABLE__FLAG 0x0001 60 61#define CACHE_WRITE_ENABLE 0xa0 62#define CACHE_WRITE_ENABLE__FLAG 0x0001 63 64#define CACHE_READ_ENABLE 0xb0 65#define CACHE_READ_ENABLE__FLAG 0x0001 66 67#define PREFETCH_MODE 0xc0 68#define PREFETCH_MODE__PREFETCH_EN 0x0001 69#define PREFETCH_MODE__PREFETCH_BURST_LENGTH 0xfff0 70 71#define CHIP_ENABLE_DONT_CARE 0xd0 72#define CHIP_EN_DONT_CARE__FLAG 0x01 73 74#define ECC_ENABLE 0xe0 75#define ECC_ENABLE__FLAG 0x0001 76 77#define GLOBAL_INT_ENABLE 0xf0 78#define GLOBAL_INT_EN_FLAG 0x01 79 80#define WE_2_RE 0x100 81#define WE_2_RE__VALUE 0x003f 82 83#define ADDR_2_DATA 0x110 84#define ADDR_2_DATA__VALUE 0x003f 85 86#define RE_2_WE 0x120 87#define RE_2_WE__VALUE 0x003f 88 89#define ACC_CLKS 0x130 90#define ACC_CLKS__VALUE 0x000f 91 92#define NUMBER_OF_PLANES 0x140 93#define NUMBER_OF_PLANES__VALUE 0x0007 94 95#define PAGES_PER_BLOCK 0x150 96#define PAGES_PER_BLOCK__VALUE 0xffff 97 98#define DEVICE_WIDTH 0x160 99#define DEVICE_WIDTH__VALUE 0x0003 100 101#define DEVICE_MAIN_AREA_SIZE 0x170 102#define DEVICE_MAIN_AREA_SIZE__VALUE 0xffff 103 104#define DEVICE_SPARE_AREA_SIZE 0x180 105#define DEVICE_SPARE_AREA_SIZE__VALUE 0xffff 106 107#define TWO_ROW_ADDR_CYCLES 0x190 108#define TWO_ROW_ADDR_CYCLES__FLAG 0x0001 109 110#define MULTIPLANE_ADDR_RESTRICT 0x1a0 111#define MULTIPLANE_ADDR_RESTRICT__FLAG 0x0001 112 113#define ECC_CORRECTION 0x1b0 114#define ECC_CORRECTION__VALUE 0x001f 115 116#define READ_MODE 0x1c0 117#define READ_MODE__VALUE 0x000f 118 119#define WRITE_MODE 0x1d0 120#define WRITE_MODE__VALUE 0x000f 121 122#define COPYBACK_MODE 0x1e0 123#define COPYBACK_MODE__VALUE 0x000f 124 125#define RDWR_EN_LO_CNT 0x1f0 126#define RDWR_EN_LO_CNT__VALUE 0x001f 127 128#define RDWR_EN_HI_CNT 0x200 129#define RDWR_EN_HI_CNT__VALUE 0x001f 130 131#define MAX_RD_DELAY 0x210 132#define MAX_RD_DELAY__VALUE 0x000f 133 134#define CS_SETUP_CNT 0x220 135#define CS_SETUP_CNT__VALUE 0x001f 136 137#define SPARE_AREA_SKIP_BYTES 0x230 138#define SPARE_AREA_SKIP_BYTES__VALUE 0x003f 139 140#define SPARE_AREA_MARKER 0x240 141#define SPARE_AREA_MARKER__VALUE 0xffff 142 143#define DEVICES_CONNECTED 0x250 144#define DEVICES_CONNECTED__VALUE 0x0007 145 146#define DIE_MASK 0x260 147#define DIE_MASK__VALUE 0x00ff 148 149#define FIRST_BLOCK_OF_NEXT_PLANE 0x270 150#define FIRST_BLOCK_OF_NEXT_PLANE__VALUE 0xffff 151 152#define WRITE_PROTECT 0x280 153#define WRITE_PROTECT__FLAG 0x0001 154 155#define RE_2_RE 0x290 156#define RE_2_RE__VALUE 0x003f 157 158#define MANUFACTURER_ID 0x300 159#define MANUFACTURER_ID__VALUE 0x00ff 160 161#define DEVICE_ID 0x310 162#define DEVICE_ID__VALUE 0x00ff 163 164#define DEVICE_PARAM_0 0x320 165#define DEVICE_PARAM_0__VALUE 0x00ff 166 167#define DEVICE_PARAM_1 0x330 168#define DEVICE_PARAM_1__VALUE 0x00ff 169 170#define DEVICE_PARAM_2 0x340 171#define DEVICE_PARAM_2__VALUE 0x00ff 172 173#define LOGICAL_PAGE_DATA_SIZE 0x350 174#define LOGICAL_PAGE_DATA_SIZE__VALUE 0xffff 175 176#define LOGICAL_PAGE_SPARE_SIZE 0x360 177#define LOGICAL_PAGE_SPARE_SIZE__VALUE 0xffff 178 179#define REVISION 0x370 180#define REVISION__VALUE 0xffff 181 182#define ONFI_DEVICE_FEATURES 0x380 183#define ONFI_DEVICE_FEATURES__VALUE 0x003f 184 185#define ONFI_OPTIONAL_COMMANDS 0x390 186#define ONFI_OPTIONAL_COMMANDS__VALUE 0x003f 187 188#define ONFI_TIMING_MODE 0x3a0 189#define ONFI_TIMING_MODE__VALUE 0x003f 190 191#define ONFI_PGM_CACHE_TIMING_MODE 0x3b0 192#define ONFI_PGM_CACHE_TIMING_MODE__VALUE 0x003f 193 194#define ONFI_DEVICE_NO_OF_LUNS 0x3c0 195#define ONFI_DEVICE_NO_OF_LUNS__NO_OF_LUNS 0x00ff 196#define ONFI_DEVICE_NO_OF_LUNS__ONFI_DEVICE 0x0100 197 198#define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L 0x3d0 199#define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L__VALUE 0xffff 200 201#define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U 0x3e0 202#define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U__VALUE 0xffff 203 204#define FEATURES 0x3f0 205#define FEATURES__N_BANKS 0x0003 206#define FEATURES__ECC_MAX_ERR 0x003c 207#define FEATURES__DMA 0x0040 208#define FEATURES__CMD_DMA 0x0080 209#define FEATURES__PARTITION 0x0100 210#define FEATURES__XDMA_SIDEBAND 0x0200 211#define FEATURES__GPREG 0x0400 212#define FEATURES__INDEX_ADDR 0x0800 213 214#define TRANSFER_MODE 0x400 215#define TRANSFER_MODE__VALUE 0x0003 216 217#define INTR_STATUS(__bank) (0x410 + ((__bank) * 0x50)) 218#define INTR_EN(__bank) (0x420 + ((__bank) * 0x50)) 219 220#define INTR_STATUS__ECC_TRANSACTION_DONE 0x0001 221#define INTR_STATUS__ECC_ERR 0x0002 222#define INTR_STATUS__DMA_CMD_COMP 0x0004 223#define INTR_STATUS__TIME_OUT 0x0008 224#define INTR_STATUS__PROGRAM_FAIL 0x0010 225#define INTR_STATUS__ERASE_FAIL 0x0020 226#define INTR_STATUS__LOAD_COMP 0x0040 227#define INTR_STATUS__PROGRAM_COMP 0x0080 228#define INTR_STATUS__ERASE_COMP 0x0100 229#define INTR_STATUS__PIPE_CPYBCK_CMD_COMP 0x0200 230#define INTR_STATUS__LOCKED_BLK 0x0400 231#define INTR_STATUS__UNSUP_CMD 0x0800 232#define INTR_STATUS__INT_ACT 0x1000 233#define INTR_STATUS__RST_COMP 0x2000 234#define INTR_STATUS__PIPE_CMD_ERR 0x4000 235#define INTR_STATUS__PAGE_XFER_INC 0x8000 236 237#define INTR_EN__ECC_TRANSACTION_DONE 0x0001 238#define INTR_EN__ECC_ERR 0x0002 239#define INTR_EN__DMA_CMD_COMP 0x0004 240#define INTR_EN__TIME_OUT 0x0008 241#define INTR_EN__PROGRAM_FAIL 0x0010 242#define INTR_EN__ERASE_FAIL 0x0020 243#define INTR_EN__LOAD_COMP 0x0040 244#define INTR_EN__PROGRAM_COMP 0x0080 245#define INTR_EN__ERASE_COMP 0x0100 246#define INTR_EN__PIPE_CPYBCK_CMD_COMP 0x0200 247#define INTR_EN__LOCKED_BLK 0x0400 248#define INTR_EN__UNSUP_CMD 0x0800 249#define INTR_EN__INT_ACT 0x1000 250#define INTR_EN__RST_COMP 0x2000 251#define INTR_EN__PIPE_CMD_ERR 0x4000 252#define INTR_EN__PAGE_XFER_INC 0x8000 253 254#define PAGE_CNT(__bank) (0x430 + ((__bank) * 0x50)) 255#define ERR_PAGE_ADDR(__bank) (0x440 + ((__bank) * 0x50)) 256#define ERR_BLOCK_ADDR(__bank) (0x450 + ((__bank) * 0x50)) 257 258#define DATA_INTR 0x550 259#define DATA_INTR__WRITE_SPACE_AV 0x0001 260#define DATA_INTR__READ_DATA_AV 0x0002 261 262#define DATA_INTR_EN 0x560 263#define DATA_INTR_EN__WRITE_SPACE_AV 0x0001 264#define DATA_INTR_EN__READ_DATA_AV 0x0002 265 266#define GPREG_0 0x570 267#define GPREG_0__VALUE 0xffff 268 269#define GPREG_1 0x580 270#define GPREG_1__VALUE 0xffff 271 272#define GPREG_2 0x590 273#define GPREG_2__VALUE 0xffff 274 275#define GPREG_3 0x5a0 276#define GPREG_3__VALUE 0xffff 277 278#define ECC_THRESHOLD 0x600 279#define ECC_THRESHOLD__VALUE 0x03ff 280 281#define ECC_ERROR_BLOCK_ADDRESS 0x610 282#define ECC_ERROR_BLOCK_ADDRESS__VALUE 0xffff 283 284#define ECC_ERROR_PAGE_ADDRESS 0x620 285#define ECC_ERROR_PAGE_ADDRESS__VALUE 0x0fff 286#define ECC_ERROR_PAGE_ADDRESS__BANK 0xf000 287 288#define ECC_ERROR_ADDRESS 0x630 289#define ECC_ERROR_ADDRESS__OFFSET 0x0fff 290#define ECC_ERROR_ADDRESS__SECTOR_NR 0xf000 291 292#define ERR_CORRECTION_INFO 0x640 293#define ERR_CORRECTION_INFO__BYTEMASK 0x00ff 294#define ERR_CORRECTION_INFO__DEVICE_NR 0x0f00 295#define ERR_CORRECTION_INFO__ERROR_TYPE 0x4000 296#define ERR_CORRECTION_INFO__LAST_ERR_INFO 0x8000 297 298#define DMA_ENABLE 0x700 299#define DMA_ENABLE__FLAG 0x0001 300 301#define IGNORE_ECC_DONE 0x710 302#define IGNORE_ECC_DONE__FLAG 0x0001 303 304#define DMA_INTR 0x720 305#define DMA_INTR__TARGET_ERROR 0x0001 306#define DMA_INTR__DESC_COMP_CHANNEL0 0x0002 307#define DMA_INTR__DESC_COMP_CHANNEL1 0x0004 308#define DMA_INTR__DESC_COMP_CHANNEL2 0x0008 309#define DMA_INTR__DESC_COMP_CHANNEL3 0x0010 310#define DMA_INTR__MEMCOPY_DESC_COMP 0x0020 311 312#define DMA_INTR_EN 0x730 313#define DMA_INTR_EN__TARGET_ERROR 0x0001 314#define DMA_INTR_EN__DESC_COMP_CHANNEL0 0x0002 315#define DMA_INTR_EN__DESC_COMP_CHANNEL1 0x0004 316#define DMA_INTR_EN__DESC_COMP_CHANNEL2 0x0008 317#define DMA_INTR_EN__DESC_COMP_CHANNEL3 0x0010 318#define DMA_INTR_EN__MEMCOPY_DESC_COMP 0x0020 319 320#define TARGET_ERR_ADDR_LO 0x740 321#define TARGET_ERR_ADDR_LO__VALUE 0xffff 322 323#define TARGET_ERR_ADDR_HI 0x750 324#define TARGET_ERR_ADDR_HI__VALUE 0xffff 325 326#define CHNL_ACTIVE 0x760 327#define CHNL_ACTIVE__CHANNEL0 0x0001 328#define CHNL_ACTIVE__CHANNEL1 0x0002 329#define CHNL_ACTIVE__CHANNEL2 0x0004 330#define CHNL_ACTIVE__CHANNEL3 0x0008 331 332#define ACTIVE_SRC_ID 0x800 333#define ACTIVE_SRC_ID__VALUE 0x00ff 334 335#define PTN_INTR 0x810 336#define PTN_INTR__CONFIG_ERROR 0x0001 337#define PTN_INTR__ACCESS_ERROR_BANK0 0x0002 338#define PTN_INTR__ACCESS_ERROR_BANK1 0x0004 339#define PTN_INTR__ACCESS_ERROR_BANK2 0x0008 340#define PTN_INTR__ACCESS_ERROR_BANK3 0x0010 341#define PTN_INTR__REG_ACCESS_ERROR 0x0020 342 343#define PTN_INTR_EN 0x820 344#define PTN_INTR_EN__CONFIG_ERROR 0x0001 345#define PTN_INTR_EN__ACCESS_ERROR_BANK0 0x0002 346#define PTN_INTR_EN__ACCESS_ERROR_BANK1 0x0004 347#define PTN_INTR_EN__ACCESS_ERROR_BANK2 0x0008 348#define PTN_INTR_EN__ACCESS_ERROR_BANK3 0x0010 349#define PTN_INTR_EN__REG_ACCESS_ERROR 0x0020 350 351#define PERM_SRC_ID(__bank) (0x830 + ((__bank) * 0x40)) 352#define PERM_SRC_ID__SRCID 0x00ff 353#define PERM_SRC_ID__DIRECT_ACCESS_ACTIVE 0x0800 354#define PERM_SRC_ID__WRITE_ACTIVE 0x2000 355#define PERM_SRC_ID__READ_ACTIVE 0x4000 356#define PERM_SRC_ID__PARTITION_VALID 0x8000 357 358#define MIN_BLK_ADDR(__bank) (0x840 + ((__bank) * 0x40)) 359#define MIN_BLK_ADDR__VALUE 0xffff 360 361#define MAX_BLK_ADDR(__bank) (0x850 + ((__bank) * 0x40)) 362#define MAX_BLK_ADDR__VALUE 0xffff 363 364#define MIN_MAX_BANK(__bank) (0x860 + ((__bank) * 0x40)) 365#define MIN_MAX_BANK__MIN_VALUE 0x0003 366#define MIN_MAX_BANK__MAX_VALUE 0x000c 367 368 369/* ffsdefs.h */ 370#define CLEAR 0 /*use this to clear a field instead of "fail"*/ 371#define SET 1 /*use this to set a field instead of "pass"*/ 372#define FAIL 1 /*failed flag*/ 373#define PASS 0 /*success flag*/ 374#define ERR -1 /*error flag*/ 375 376/* lld.h */ 377#define GOOD_BLOCK 0 378#define DEFECTIVE_BLOCK 1 379#define READ_ERROR 2 380 381#define CLK_X 5 382#define CLK_MULTI 4 383 384/* spectraswconfig.h */ 385#define CMD_DMA 0 386 387#define SPECTRA_PARTITION_ID 0 388/**** Block Table and Reserved Block Parameters *****/ 389#define SPECTRA_START_BLOCK 3 390#define NUM_FREE_BLOCKS_GATE 30 391 392/* KBV - Updated to LNW scratch register address */ 393#define SCRATCH_REG_ADDR CONFIG_MTD_NAND_DENALI_SCRATCH_REG_ADDR 394#define SCRATCH_REG_SIZE 64 395 396#define GLOB_HWCTL_DEFAULT_BLKS 2048 397 398#define SUPPORT_15BITECC 1 399#define SUPPORT_8BITECC 1 400 401#define CUSTOM_CONF_PARAMS 0 402 403#define ONFI_BLOOM_TIME 1 404#define MODE5_WORKAROUND 0 405 406 407#define MODE_00 0x00000000 408#define MODE_01 0x04000000 409#define MODE_10 0x08000000 410#define MODE_11 0x0C000000 411 412 413#define DATA_TRANSFER_MODE 0 414#define PROTECTION_PER_BLOCK 1 415#define LOAD_WAIT_COUNT 2 416#define PROGRAM_WAIT_COUNT 3 417#define ERASE_WAIT_COUNT 4 418#define INT_MONITOR_CYCLE_COUNT 5 419#define READ_BUSY_PIN_ENABLED 6 420#define MULTIPLANE_OPERATION_SUPPORT 7 421#define PRE_FETCH_MODE 8 422#define CE_DONT_CARE_SUPPORT 9 423#define COPYBACK_SUPPORT 10 424#define CACHE_WRITE_SUPPORT 11 425#define CACHE_READ_SUPPORT 12 426#define NUM_PAGES_IN_BLOCK 13 427#define ECC_ENABLE_SELECT 14 428#define WRITE_ENABLE_2_READ_ENABLE 15 429#define ADDRESS_2_DATA 16 430#define READ_ENABLE_2_WRITE_ENABLE 17 431#define TWO_ROW_ADDRESS_CYCLES 18 432#define MULTIPLANE_ADDRESS_RESTRICT 19 433#define ACC_CLOCKS 20 434#define READ_WRITE_ENABLE_LOW_COUNT 21 435#define READ_WRITE_ENABLE_HIGH_COUNT 22 436 437#define ECC_SECTOR_SIZE 512 438 439struct nand_buf { 440 int head; 441 int tail; 442 uint8_t *buf; 443 dma_addr_t dma_buf; 444}; 445 446#define INTEL_CE4100 1 447#define INTEL_MRST 2 448#define DT 3 449 450struct denali_nand_info { 451 struct mtd_info mtd; 452 struct nand_chip nand; 453 int flash_bank; /* currently selected chip */ 454 int status; 455 int platform; 456 struct nand_buf buf; 457 struct device *dev; 458 int total_used_banks; 459 uint32_t block; /* stored for future use */ 460 uint16_t page; 461 void __iomem *flash_reg; /* Mapped io reg base address */ 462 void __iomem *flash_mem; /* Mapped io reg base address */ 463 464 /* elements used by ISR */ 465 struct completion complete; 466 spinlock_t irq_lock; 467 uint32_t irq_status; 468 int irq_debug_array[32]; 469 int idx; 470 int irq; 471 472 uint32_t devnum; /* represent how many nands connected */ 473 uint32_t fwblks; /* represent how many blocks FW used */ 474 uint32_t totalblks; 475 uint32_t blksperchip; 476 uint32_t bbtskipbytes; 477 uint32_t max_banks; 478}; 479 480extern int denali_init(struct denali_nand_info *denali); 481extern void denali_remove(struct denali_nand_info *denali); 482 483#endif /* __DENALI_H__ */ 484