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117#include <linux/phy.h>
118#include <linux/clk.h>
119#include <linux/bitrev.h>
120#include <linux/crc32.h>
121
122#include "xgbe.h"
123#include "xgbe-common.h"
124
125static unsigned int xgbe_usec_to_riwt(struct xgbe_prv_data *pdata,
126 unsigned int usec)
127{
128 unsigned long rate;
129 unsigned int ret;
130
131 DBGPR("-->xgbe_usec_to_riwt\n");
132
133 rate = clk_get_rate(pdata->sysclk);
134
135
136
137
138
139
140
141 ret = (usec * (rate / 1000000)) / 256;
142
143 DBGPR("<--xgbe_usec_to_riwt\n");
144
145 return ret;
146}
147
148static unsigned int xgbe_riwt_to_usec(struct xgbe_prv_data *pdata,
149 unsigned int riwt)
150{
151 unsigned long rate;
152 unsigned int ret;
153
154 DBGPR("-->xgbe_riwt_to_usec\n");
155
156 rate = clk_get_rate(pdata->sysclk);
157
158
159
160
161
162
163
164 ret = (riwt * 256) / (rate / 1000000);
165
166 DBGPR("<--xgbe_riwt_to_usec\n");
167
168 return ret;
169}
170
171static int xgbe_config_pblx8(struct xgbe_prv_data *pdata)
172{
173 struct xgbe_channel *channel;
174 unsigned int i;
175
176 channel = pdata->channel;
177 for (i = 0; i < pdata->channel_count; i++, channel++)
178 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_CR, PBLX8,
179 pdata->pblx8);
180
181 return 0;
182}
183
184static int xgbe_get_tx_pbl_val(struct xgbe_prv_data *pdata)
185{
186 return XGMAC_DMA_IOREAD_BITS(pdata->channel, DMA_CH_TCR, PBL);
187}
188
189static int xgbe_config_tx_pbl_val(struct xgbe_prv_data *pdata)
190{
191 struct xgbe_channel *channel;
192 unsigned int i;
193
194 channel = pdata->channel;
195 for (i = 0; i < pdata->channel_count; i++, channel++) {
196 if (!channel->tx_ring)
197 break;
198
199 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, PBL,
200 pdata->tx_pbl);
201 }
202
203 return 0;
204}
205
206static int xgbe_get_rx_pbl_val(struct xgbe_prv_data *pdata)
207{
208 return XGMAC_DMA_IOREAD_BITS(pdata->channel, DMA_CH_RCR, PBL);
209}
210
211static int xgbe_config_rx_pbl_val(struct xgbe_prv_data *pdata)
212{
213 struct xgbe_channel *channel;
214 unsigned int i;
215
216 channel = pdata->channel;
217 for (i = 0; i < pdata->channel_count; i++, channel++) {
218 if (!channel->rx_ring)
219 break;
220
221 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RCR, PBL,
222 pdata->rx_pbl);
223 }
224
225 return 0;
226}
227
228static int xgbe_config_osp_mode(struct xgbe_prv_data *pdata)
229{
230 struct xgbe_channel *channel;
231 unsigned int i;
232
233 channel = pdata->channel;
234 for (i = 0; i < pdata->channel_count; i++, channel++) {
235 if (!channel->tx_ring)
236 break;
237
238 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, OSP,
239 pdata->tx_osp_mode);
240 }
241
242 return 0;
243}
244
245static int xgbe_config_rsf_mode(struct xgbe_prv_data *pdata, unsigned int val)
246{
247 unsigned int i;
248
249 for (i = 0; i < pdata->rx_q_count; i++)
250 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RSF, val);
251
252 return 0;
253}
254
255static int xgbe_config_tsf_mode(struct xgbe_prv_data *pdata, unsigned int val)
256{
257 unsigned int i;
258
259 for (i = 0; i < pdata->tx_q_count; i++)
260 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TSF, val);
261
262 return 0;
263}
264
265static int xgbe_config_rx_threshold(struct xgbe_prv_data *pdata,
266 unsigned int val)
267{
268 unsigned int i;
269
270 for (i = 0; i < pdata->rx_q_count; i++)
271 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RTC, val);
272
273 return 0;
274}
275
276static int xgbe_config_tx_threshold(struct xgbe_prv_data *pdata,
277 unsigned int val)
278{
279 unsigned int i;
280
281 for (i = 0; i < pdata->tx_q_count; i++)
282 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TTC, val);
283
284 return 0;
285}
286
287static int xgbe_config_rx_coalesce(struct xgbe_prv_data *pdata)
288{
289 struct xgbe_channel *channel;
290 unsigned int i;
291
292 channel = pdata->channel;
293 for (i = 0; i < pdata->channel_count; i++, channel++) {
294 if (!channel->rx_ring)
295 break;
296
297 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RIWT, RWT,
298 pdata->rx_riwt);
299 }
300
301 return 0;
302}
303
304static int xgbe_config_tx_coalesce(struct xgbe_prv_data *pdata)
305{
306 return 0;
307}
308
309static void xgbe_config_rx_buffer_size(struct xgbe_prv_data *pdata)
310{
311 struct xgbe_channel *channel;
312 unsigned int i;
313
314 channel = pdata->channel;
315 for (i = 0; i < pdata->channel_count; i++, channel++) {
316 if (!channel->rx_ring)
317 break;
318
319 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RCR, RBSZ,
320 pdata->rx_buf_size);
321 }
322}
323
324static void xgbe_config_tso_mode(struct xgbe_prv_data *pdata)
325{
326 struct xgbe_channel *channel;
327 unsigned int i;
328
329 channel = pdata->channel;
330 for (i = 0; i < pdata->channel_count; i++, channel++) {
331 if (!channel->tx_ring)
332 break;
333
334 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, TSE, 1);
335 }
336}
337
338static int xgbe_disable_tx_flow_control(struct xgbe_prv_data *pdata)
339{
340 unsigned int max_q_count, q_count;
341 unsigned int reg, reg_val;
342 unsigned int i;
343
344
345 for (i = 0; i < pdata->rx_q_count; i++)
346 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, EHFC, 0);
347
348
349 max_q_count = XGMAC_MAX_FLOW_CONTROL_QUEUES;
350 q_count = min_t(unsigned int, pdata->tx_q_count, max_q_count);
351 reg = MAC_Q0TFCR;
352 for (i = 0; i < q_count; i++) {
353 reg_val = XGMAC_IOREAD(pdata, reg);
354 XGMAC_SET_BITS(reg_val, MAC_Q0TFCR, TFE, 0);
355 XGMAC_IOWRITE(pdata, reg, reg_val);
356
357 reg += MAC_QTFCR_INC;
358 }
359
360 return 0;
361}
362
363static int xgbe_enable_tx_flow_control(struct xgbe_prv_data *pdata)
364{
365 unsigned int max_q_count, q_count;
366 unsigned int reg, reg_val;
367 unsigned int i;
368
369
370 for (i = 0; i < pdata->rx_q_count; i++)
371 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, EHFC, 1);
372
373
374 max_q_count = XGMAC_MAX_FLOW_CONTROL_QUEUES;
375 q_count = min_t(unsigned int, pdata->tx_q_count, max_q_count);
376 reg = MAC_Q0TFCR;
377 for (i = 0; i < q_count; i++) {
378 reg_val = XGMAC_IOREAD(pdata, reg);
379
380
381 XGMAC_SET_BITS(reg_val, MAC_Q0TFCR, TFE, 1);
382
383 XGMAC_SET_BITS(reg_val, MAC_Q0TFCR, PT, 0xffff);
384
385 XGMAC_IOWRITE(pdata, reg, reg_val);
386
387 reg += MAC_QTFCR_INC;
388 }
389
390 return 0;
391}
392
393static int xgbe_disable_rx_flow_control(struct xgbe_prv_data *pdata)
394{
395 XGMAC_IOWRITE_BITS(pdata, MAC_RFCR, RFE, 0);
396
397 return 0;
398}
399
400static int xgbe_enable_rx_flow_control(struct xgbe_prv_data *pdata)
401{
402 XGMAC_IOWRITE_BITS(pdata, MAC_RFCR, RFE, 1);
403
404 return 0;
405}
406
407static int xgbe_config_tx_flow_control(struct xgbe_prv_data *pdata)
408{
409 struct ieee_pfc *pfc = pdata->pfc;
410
411 if (pdata->tx_pause || (pfc && pfc->pfc_en))
412 xgbe_enable_tx_flow_control(pdata);
413 else
414 xgbe_disable_tx_flow_control(pdata);
415
416 return 0;
417}
418
419static int xgbe_config_rx_flow_control(struct xgbe_prv_data *pdata)
420{
421 struct ieee_pfc *pfc = pdata->pfc;
422
423 if (pdata->rx_pause || (pfc && pfc->pfc_en))
424 xgbe_enable_rx_flow_control(pdata);
425 else
426 xgbe_disable_rx_flow_control(pdata);
427
428 return 0;
429}
430
431static void xgbe_config_flow_control(struct xgbe_prv_data *pdata)
432{
433 struct ieee_pfc *pfc = pdata->pfc;
434
435 xgbe_config_tx_flow_control(pdata);
436 xgbe_config_rx_flow_control(pdata);
437
438 XGMAC_IOWRITE_BITS(pdata, MAC_RFCR, PFCE,
439 (pfc && pfc->pfc_en) ? 1 : 0);
440}
441
442static void xgbe_enable_dma_interrupts(struct xgbe_prv_data *pdata)
443{
444 struct xgbe_channel *channel;
445 unsigned int dma_ch_isr, dma_ch_ier;
446 unsigned int i;
447
448 channel = pdata->channel;
449 for (i = 0; i < pdata->channel_count; i++, channel++) {
450
451 dma_ch_isr = XGMAC_DMA_IOREAD(channel, DMA_CH_SR);
452 XGMAC_DMA_IOWRITE(channel, DMA_CH_SR, dma_ch_isr);
453
454
455 dma_ch_ier = 0;
456
457
458
459
460
461
462 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, NIE, 1);
463 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, AIE, 1);
464 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, FBEE, 1);
465
466 if (channel->tx_ring) {
467
468
469
470 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TIE, 1);
471 }
472 if (channel->rx_ring) {
473
474
475
476
477 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RBUE, 1);
478 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RIE, 1);
479 }
480
481 XGMAC_DMA_IOWRITE(channel, DMA_CH_IER, dma_ch_ier);
482 }
483}
484
485static void xgbe_enable_mtl_interrupts(struct xgbe_prv_data *pdata)
486{
487 unsigned int mtl_q_isr;
488 unsigned int q_count, i;
489
490 q_count = max(pdata->hw_feat.tx_q_cnt, pdata->hw_feat.rx_q_cnt);
491 for (i = 0; i < q_count; i++) {
492
493 mtl_q_isr = XGMAC_MTL_IOREAD(pdata, i, MTL_Q_ISR);
494 XGMAC_MTL_IOWRITE(pdata, i, MTL_Q_ISR, mtl_q_isr);
495
496
497 XGMAC_MTL_IOWRITE(pdata, i, MTL_Q_IER, 0);
498 }
499}
500
501static void xgbe_enable_mac_interrupts(struct xgbe_prv_data *pdata)
502{
503 unsigned int mac_ier = 0;
504
505
506 XGMAC_SET_BITS(mac_ier, MAC_IER, TSIE, 1);
507
508 XGMAC_IOWRITE(pdata, MAC_IER, mac_ier);
509
510
511 XGMAC_IOWRITE_BITS(pdata, MMC_RIER, ALL_INTERRUPTS, 0xffffffff);
512 XGMAC_IOWRITE_BITS(pdata, MMC_TIER, ALL_INTERRUPTS, 0xffffffff);
513}
514
515static int xgbe_set_gmii_speed(struct xgbe_prv_data *pdata)
516{
517 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, SS, 0x3);
518
519 return 0;
520}
521
522static int xgbe_set_gmii_2500_speed(struct xgbe_prv_data *pdata)
523{
524 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, SS, 0x2);
525
526 return 0;
527}
528
529static int xgbe_set_xgmii_speed(struct xgbe_prv_data *pdata)
530{
531 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, SS, 0);
532
533 return 0;
534}
535
536static int xgbe_set_promiscuous_mode(struct xgbe_prv_data *pdata,
537 unsigned int enable)
538{
539 unsigned int val = enable ? 1 : 0;
540
541 if (XGMAC_IOREAD_BITS(pdata, MAC_PFR, PR) == val)
542 return 0;
543
544 DBGPR(" %s promiscuous mode\n", enable ? "entering" : "leaving");
545 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, PR, val);
546
547 return 0;
548}
549
550static int xgbe_set_all_multicast_mode(struct xgbe_prv_data *pdata,
551 unsigned int enable)
552{
553 unsigned int val = enable ? 1 : 0;
554
555 if (XGMAC_IOREAD_BITS(pdata, MAC_PFR, PM) == val)
556 return 0;
557
558 DBGPR(" %s allmulti mode\n", enable ? "entering" : "leaving");
559 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, PM, val);
560
561 return 0;
562}
563
564static void xgbe_set_mac_reg(struct xgbe_prv_data *pdata,
565 struct netdev_hw_addr *ha, unsigned int *mac_reg)
566{
567 unsigned int mac_addr_hi, mac_addr_lo;
568 u8 *mac_addr;
569
570 mac_addr_lo = 0;
571 mac_addr_hi = 0;
572
573 if (ha) {
574 mac_addr = (u8 *)&mac_addr_lo;
575 mac_addr[0] = ha->addr[0];
576 mac_addr[1] = ha->addr[1];
577 mac_addr[2] = ha->addr[2];
578 mac_addr[3] = ha->addr[3];
579 mac_addr = (u8 *)&mac_addr_hi;
580 mac_addr[0] = ha->addr[4];
581 mac_addr[1] = ha->addr[5];
582
583 DBGPR(" adding mac address %pM at 0x%04x\n", ha->addr,
584 *mac_reg);
585
586 XGMAC_SET_BITS(mac_addr_hi, MAC_MACA1HR, AE, 1);
587 }
588
589 XGMAC_IOWRITE(pdata, *mac_reg, mac_addr_hi);
590 *mac_reg += MAC_MACA_INC;
591 XGMAC_IOWRITE(pdata, *mac_reg, mac_addr_lo);
592 *mac_reg += MAC_MACA_INC;
593}
594
595static void xgbe_set_mac_addn_addrs(struct xgbe_prv_data *pdata)
596{
597 struct net_device *netdev = pdata->netdev;
598 struct netdev_hw_addr *ha;
599 unsigned int mac_reg;
600 unsigned int addn_macs;
601
602 mac_reg = MAC_MACA1HR;
603 addn_macs = pdata->hw_feat.addn_mac;
604
605 if (netdev_uc_count(netdev) > addn_macs) {
606 xgbe_set_promiscuous_mode(pdata, 1);
607 } else {
608 netdev_for_each_uc_addr(ha, netdev) {
609 xgbe_set_mac_reg(pdata, ha, &mac_reg);
610 addn_macs--;
611 }
612
613 if (netdev_mc_count(netdev) > addn_macs) {
614 xgbe_set_all_multicast_mode(pdata, 1);
615 } else {
616 netdev_for_each_mc_addr(ha, netdev) {
617 xgbe_set_mac_reg(pdata, ha, &mac_reg);
618 addn_macs--;
619 }
620 }
621 }
622
623
624 while (addn_macs--)
625 xgbe_set_mac_reg(pdata, NULL, &mac_reg);
626}
627
628static void xgbe_set_mac_hash_table(struct xgbe_prv_data *pdata)
629{
630 struct net_device *netdev = pdata->netdev;
631 struct netdev_hw_addr *ha;
632 unsigned int hash_reg;
633 unsigned int hash_table_shift, hash_table_count;
634 u32 hash_table[XGBE_MAC_HASH_TABLE_SIZE];
635 u32 crc;
636 unsigned int i;
637
638 hash_table_shift = 26 - (pdata->hw_feat.hash_table_size >> 7);
639 hash_table_count = pdata->hw_feat.hash_table_size / 32;
640 memset(hash_table, 0, sizeof(hash_table));
641
642
643 netdev_for_each_uc_addr(ha, netdev) {
644 crc = bitrev32(~crc32_le(~0, ha->addr, ETH_ALEN));
645 crc >>= hash_table_shift;
646 hash_table[crc >> 5] |= (1 << (crc & 0x1f));
647 }
648
649 netdev_for_each_mc_addr(ha, netdev) {
650 crc = bitrev32(~crc32_le(~0, ha->addr, ETH_ALEN));
651 crc >>= hash_table_shift;
652 hash_table[crc >> 5] |= (1 << (crc & 0x1f));
653 }
654
655
656 hash_reg = MAC_HTR0;
657 for (i = 0; i < hash_table_count; i++) {
658 XGMAC_IOWRITE(pdata, hash_reg, hash_table[i]);
659 hash_reg += MAC_HTR_INC;
660 }
661}
662
663static int xgbe_add_mac_addresses(struct xgbe_prv_data *pdata)
664{
665 if (pdata->hw_feat.hash_table_size)
666 xgbe_set_mac_hash_table(pdata);
667 else
668 xgbe_set_mac_addn_addrs(pdata);
669
670 return 0;
671}
672
673static int xgbe_set_mac_address(struct xgbe_prv_data *pdata, u8 *addr)
674{
675 unsigned int mac_addr_hi, mac_addr_lo;
676
677 mac_addr_hi = (addr[5] << 8) | (addr[4] << 0);
678 mac_addr_lo = (addr[3] << 24) | (addr[2] << 16) |
679 (addr[1] << 8) | (addr[0] << 0);
680
681 XGMAC_IOWRITE(pdata, MAC_MACA0HR, mac_addr_hi);
682 XGMAC_IOWRITE(pdata, MAC_MACA0LR, mac_addr_lo);
683
684 return 0;
685}
686
687static int xgbe_read_mmd_regs(struct xgbe_prv_data *pdata, int prtad,
688 int mmd_reg)
689{
690 unsigned int mmd_address;
691 int mmd_data;
692
693 if (mmd_reg & MII_ADDR_C45)
694 mmd_address = mmd_reg & ~MII_ADDR_C45;
695 else
696 mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff);
697
698
699
700
701
702
703
704
705
706
707 mutex_lock(&pdata->xpcs_mutex);
708 XPCS_IOWRITE(pdata, PCS_MMD_SELECT << 2, mmd_address >> 8);
709 mmd_data = XPCS_IOREAD(pdata, (mmd_address & 0xff) << 2);
710 mutex_unlock(&pdata->xpcs_mutex);
711
712 return mmd_data;
713}
714
715static void xgbe_write_mmd_regs(struct xgbe_prv_data *pdata, int prtad,
716 int mmd_reg, int mmd_data)
717{
718 unsigned int mmd_address;
719
720 if (mmd_reg & MII_ADDR_C45)
721 mmd_address = mmd_reg & ~MII_ADDR_C45;
722 else
723 mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff);
724
725
726
727
728
729
730
731
732
733
734 mutex_lock(&pdata->xpcs_mutex);
735 XPCS_IOWRITE(pdata, PCS_MMD_SELECT << 2, mmd_address >> 8);
736 XPCS_IOWRITE(pdata, (mmd_address & 0xff) << 2, mmd_data);
737 mutex_unlock(&pdata->xpcs_mutex);
738}
739
740static int xgbe_tx_complete(struct xgbe_ring_desc *rdesc)
741{
742 return !XGMAC_GET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, OWN);
743}
744
745static int xgbe_disable_rx_csum(struct xgbe_prv_data *pdata)
746{
747 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, IPC, 0);
748
749 return 0;
750}
751
752static int xgbe_enable_rx_csum(struct xgbe_prv_data *pdata)
753{
754 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, IPC, 1);
755
756 return 0;
757}
758
759static int xgbe_enable_rx_vlan_stripping(struct xgbe_prv_data *pdata)
760{
761
762 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, EVLRXS, 1);
763
764
765 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, DOVLTC, 1);
766
767
768 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, ERSVLM, 0);
769
770
771 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, ESVL, 0);
772
773
774 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, EVLS, 0x3);
775
776 return 0;
777}
778
779static int xgbe_disable_rx_vlan_stripping(struct xgbe_prv_data *pdata)
780{
781 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, EVLS, 0);
782
783 return 0;
784}
785
786static int xgbe_enable_rx_vlan_filtering(struct xgbe_prv_data *pdata)
787{
788
789 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, VTFE, 1);
790
791
792 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, VTHM, 1);
793
794
795 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, VTIM, 0);
796
797
798 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, ETV, 1);
799
800
801
802
803
804
805
806 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, VL, 1);
807
808 return 0;
809}
810
811static int xgbe_disable_rx_vlan_filtering(struct xgbe_prv_data *pdata)
812{
813
814 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, VTFE, 0);
815
816 return 0;
817}
818
819#ifndef CRCPOLY_LE
820#define CRCPOLY_LE 0xedb88320
821#endif
822static u32 xgbe_vid_crc32_le(__le16 vid_le)
823{
824 u32 poly = CRCPOLY_LE;
825 u32 crc = ~0;
826 u32 temp = 0;
827 unsigned char *data = (unsigned char *)&vid_le;
828 unsigned char data_byte = 0;
829 int i, bits;
830
831 bits = get_bitmask_order(VLAN_VID_MASK);
832 for (i = 0; i < bits; i++) {
833 if ((i % 8) == 0)
834 data_byte = data[i / 8];
835
836 temp = ((crc & 1) ^ data_byte) & 1;
837 crc >>= 1;
838 data_byte >>= 1;
839
840 if (temp)
841 crc ^= poly;
842 }
843
844 return crc;
845}
846
847static int xgbe_update_vlan_hash_table(struct xgbe_prv_data *pdata)
848{
849 u32 crc;
850 u16 vid;
851 __le16 vid_le;
852 u16 vlan_hash_table = 0;
853
854
855 for_each_set_bit(vid, pdata->active_vlans, VLAN_N_VID) {
856
857 vid_le = cpu_to_le16(vid);
858 crc = bitrev32(~xgbe_vid_crc32_le(vid_le)) >> 28;
859
860 vlan_hash_table |= (1 << crc);
861 }
862
863
864 XGMAC_IOWRITE_BITS(pdata, MAC_VLANHTR, VLHT, vlan_hash_table);
865
866 return 0;
867}
868
869static void xgbe_tx_desc_reset(struct xgbe_ring_data *rdata)
870{
871 struct xgbe_ring_desc *rdesc = rdata->rdesc;
872
873
874
875
876
877
878
879 rdesc->desc0 = 0;
880 rdesc->desc1 = 0;
881 rdesc->desc2 = 0;
882 rdesc->desc3 = 0;
883}
884
885static void xgbe_tx_desc_init(struct xgbe_channel *channel)
886{
887 struct xgbe_ring *ring = channel->tx_ring;
888 struct xgbe_ring_data *rdata;
889 struct xgbe_ring_desc *rdesc;
890 int i;
891 int start_index = ring->cur;
892
893 DBGPR("-->tx_desc_init\n");
894
895
896 for (i = 0; i < ring->rdesc_count; i++) {
897 rdata = XGBE_GET_DESC_DATA(ring, i);
898 rdesc = rdata->rdesc;
899
900
901
902
903
904
905
906
907 rdesc->desc0 = 0;
908 rdesc->desc1 = 0;
909 rdesc->desc2 = 0;
910 rdesc->desc3 = 0;
911 }
912
913
914
915
916 wmb();
917
918
919 XGMAC_DMA_IOWRITE(channel, DMA_CH_TDRLR, ring->rdesc_count - 1);
920
921
922 rdata = XGBE_GET_DESC_DATA(ring, start_index);
923 XGMAC_DMA_IOWRITE(channel, DMA_CH_TDLR_HI,
924 upper_32_bits(rdata->rdesc_dma));
925 XGMAC_DMA_IOWRITE(channel, DMA_CH_TDLR_LO,
926 lower_32_bits(rdata->rdesc_dma));
927
928 DBGPR("<--tx_desc_init\n");
929}
930
931static void xgbe_rx_desc_reset(struct xgbe_ring_data *rdata)
932{
933 struct xgbe_ring_desc *rdesc = rdata->rdesc;
934
935
936
937
938
939
940
941
942 rdesc->desc0 = cpu_to_le32(lower_32_bits(rdata->skb_dma));
943 rdesc->desc1 = cpu_to_le32(upper_32_bits(rdata->skb_dma));
944 rdesc->desc2 = 0;
945
946 rdesc->desc3 = 0;
947 if (rdata->interrupt)
948 XGMAC_SET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, INTE, 1);
949
950
951
952
953
954 wmb();
955
956 XGMAC_SET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, OWN, 1);
957
958
959 wmb();
960}
961
962static void xgbe_rx_desc_init(struct xgbe_channel *channel)
963{
964 struct xgbe_prv_data *pdata = channel->pdata;
965 struct xgbe_ring *ring = channel->rx_ring;
966 struct xgbe_ring_data *rdata;
967 struct xgbe_ring_desc *rdesc;
968 unsigned int start_index = ring->cur;
969 unsigned int rx_coalesce, rx_frames;
970 unsigned int i;
971
972 DBGPR("-->rx_desc_init\n");
973
974 rx_coalesce = (pdata->rx_riwt || pdata->rx_frames) ? 1 : 0;
975 rx_frames = pdata->rx_frames;
976
977
978 for (i = 0; i < ring->rdesc_count; i++) {
979 rdata = XGBE_GET_DESC_DATA(ring, i);
980 rdesc = rdata->rdesc;
981
982
983
984
985
986
987
988
989 rdesc->desc0 = cpu_to_le32(lower_32_bits(rdata->skb_dma));
990 rdesc->desc1 = cpu_to_le32(upper_32_bits(rdata->skb_dma));
991 rdesc->desc2 = 0;
992 rdesc->desc3 = 0;
993 XGMAC_SET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, OWN, 1);
994 XGMAC_SET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, INTE, 1);
995 rdata->interrupt = 1;
996 if (rx_coalesce && (!rx_frames || ((i + 1) % rx_frames))) {
997
998 XGMAC_SET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, INTE,
999 0);
1000 rdata->interrupt = 0;
1001 }
1002 }
1003
1004
1005
1006
1007 wmb();
1008
1009
1010 XGMAC_DMA_IOWRITE(channel, DMA_CH_RDRLR, ring->rdesc_count - 1);
1011
1012
1013 rdata = XGBE_GET_DESC_DATA(ring, start_index);
1014 XGMAC_DMA_IOWRITE(channel, DMA_CH_RDLR_HI,
1015 upper_32_bits(rdata->rdesc_dma));
1016 XGMAC_DMA_IOWRITE(channel, DMA_CH_RDLR_LO,
1017 lower_32_bits(rdata->rdesc_dma));
1018
1019
1020 rdata = XGBE_GET_DESC_DATA(ring, start_index + ring->rdesc_count - 1);
1021 XGMAC_DMA_IOWRITE(channel, DMA_CH_RDTR_LO,
1022 lower_32_bits(rdata->rdesc_dma));
1023
1024 DBGPR("<--rx_desc_init\n");
1025}
1026
1027static void xgbe_update_tstamp_addend(struct xgbe_prv_data *pdata,
1028 unsigned int addend)
1029{
1030
1031 XGMAC_IOWRITE(pdata, MAC_TSAR, addend);
1032 XGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSADDREG, 1);
1033
1034
1035 while (XGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSADDREG))
1036 udelay(5);
1037}
1038
1039static void xgbe_set_tstamp_time(struct xgbe_prv_data *pdata, unsigned int sec,
1040 unsigned int nsec)
1041{
1042
1043 XGMAC_IOWRITE(pdata, MAC_STSUR, sec);
1044 XGMAC_IOWRITE(pdata, MAC_STNUR, nsec);
1045 XGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSINIT, 1);
1046
1047
1048 while (XGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSINIT))
1049 udelay(5);
1050}
1051
1052static u64 xgbe_get_tstamp_time(struct xgbe_prv_data *pdata)
1053{
1054 u64 nsec;
1055
1056 nsec = XGMAC_IOREAD(pdata, MAC_STSR);
1057 nsec *= NSEC_PER_SEC;
1058 nsec += XGMAC_IOREAD(pdata, MAC_STNR);
1059
1060 return nsec;
1061}
1062
1063static u64 xgbe_get_tx_tstamp(struct xgbe_prv_data *pdata)
1064{
1065 unsigned int tx_snr;
1066 u64 nsec;
1067
1068 tx_snr = XGMAC_IOREAD(pdata, MAC_TXSNR);
1069 if (XGMAC_GET_BITS(tx_snr, MAC_TXSNR, TXTSSTSMIS))
1070 return 0;
1071
1072 nsec = XGMAC_IOREAD(pdata, MAC_TXSSR);
1073 nsec *= NSEC_PER_SEC;
1074 nsec += tx_snr;
1075
1076 return nsec;
1077}
1078
1079static void xgbe_get_rx_tstamp(struct xgbe_packet_data *packet,
1080 struct xgbe_ring_desc *rdesc)
1081{
1082 u64 nsec;
1083
1084 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_CONTEXT_DESC3, TSA) &&
1085 !XGMAC_GET_BITS_LE(rdesc->desc3, RX_CONTEXT_DESC3, TSD)) {
1086 nsec = le32_to_cpu(rdesc->desc1);
1087 nsec <<= 32;
1088 nsec |= le32_to_cpu(rdesc->desc0);
1089 if (nsec != 0xffffffffffffffffULL) {
1090 packet->rx_tstamp = nsec;
1091 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1092 RX_TSTAMP, 1);
1093 }
1094 }
1095}
1096
1097static int xgbe_config_tstamp(struct xgbe_prv_data *pdata,
1098 unsigned int mac_tscr)
1099{
1100
1101 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSCTRLSSR, 1);
1102
1103
1104 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSCFUPDT, 1);
1105
1106
1107 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TXTSSTSM, 1);
1108
1109 XGMAC_IOWRITE(pdata, MAC_TSCR, mac_tscr);
1110
1111
1112 if (!XGMAC_GET_BITS(mac_tscr, MAC_TSCR, TSENA))
1113 return 0;
1114
1115
1116 XGMAC_IOWRITE_BITS(pdata, MAC_SSIR, SSINC, XGBE_TSTAMP_SSINC);
1117 XGMAC_IOWRITE_BITS(pdata, MAC_SSIR, SNSINC, XGBE_TSTAMP_SNSINC);
1118 xgbe_update_tstamp_addend(pdata, pdata->tstamp_addend);
1119 xgbe_set_tstamp_time(pdata, 0, 0);
1120
1121
1122 timecounter_init(&pdata->tstamp_tc, &pdata->tstamp_cc,
1123 ktime_to_ns(ktime_get_real()));
1124
1125 return 0;
1126}
1127
1128static void xgbe_config_dcb_tc(struct xgbe_prv_data *pdata)
1129{
1130 struct ieee_ets *ets = pdata->ets;
1131 unsigned int total_weight, min_weight, weight;
1132 unsigned int i;
1133
1134 if (!ets)
1135 return;
1136
1137
1138
1139
1140 XGMAC_IOWRITE_BITS(pdata, MTL_OMR, ETSALG, MTL_ETSALG_DWRR);
1141
1142
1143 total_weight = pdata->netdev->mtu * pdata->hw_feat.tc_cnt;
1144 min_weight = total_weight / 100;
1145 if (!min_weight)
1146 min_weight = 1;
1147
1148 for (i = 0; i < pdata->hw_feat.tc_cnt; i++) {
1149 switch (ets->tc_tsa[i]) {
1150 case IEEE_8021QAZ_TSA_STRICT:
1151 DBGPR(" TC%u using SP\n", i);
1152 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_ETSCR, TSA,
1153 MTL_TSA_SP);
1154 break;
1155 case IEEE_8021QAZ_TSA_ETS:
1156 weight = total_weight * ets->tc_tx_bw[i] / 100;
1157 weight = clamp(weight, min_weight, total_weight);
1158
1159 DBGPR(" TC%u using DWRR (weight %u)\n", i, weight);
1160 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_ETSCR, TSA,
1161 MTL_TSA_ETS);
1162 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_QWR, QW,
1163 weight);
1164 break;
1165 }
1166 }
1167}
1168
1169static void xgbe_config_dcb_pfc(struct xgbe_prv_data *pdata)
1170{
1171 struct ieee_pfc *pfc = pdata->pfc;
1172 struct ieee_ets *ets = pdata->ets;
1173 unsigned int mask, reg, reg_val;
1174 unsigned int tc, prio;
1175
1176 if (!pfc || !ets)
1177 return;
1178
1179 for (tc = 0; tc < pdata->hw_feat.tc_cnt; tc++) {
1180 mask = 0;
1181 for (prio = 0; prio < IEEE_8021QAZ_MAX_TCS; prio++) {
1182 if ((pfc->pfc_en & (1 << prio)) &&
1183 (ets->prio_tc[prio] == tc))
1184 mask |= (1 << prio);
1185 }
1186 mask &= 0xff;
1187
1188 DBGPR(" TC%u PFC mask=%#x\n", tc, mask);
1189 reg = MTL_TCPM0R + (MTL_TCPM_INC * (tc / MTL_TCPM_TC_PER_REG));
1190 reg_val = XGMAC_IOREAD(pdata, reg);
1191
1192 reg_val &= ~(0xff << ((tc % MTL_TCPM_TC_PER_REG) << 3));
1193 reg_val |= (mask << ((tc % MTL_TCPM_TC_PER_REG) << 3));
1194
1195 XGMAC_IOWRITE(pdata, reg, reg_val);
1196 }
1197
1198 xgbe_config_flow_control(pdata);
1199}
1200
1201static void xgbe_pre_xmit(struct xgbe_channel *channel)
1202{
1203 struct xgbe_prv_data *pdata = channel->pdata;
1204 struct xgbe_ring *ring = channel->tx_ring;
1205 struct xgbe_ring_data *rdata;
1206 struct xgbe_ring_desc *rdesc;
1207 struct xgbe_packet_data *packet = &ring->packet_data;
1208 unsigned int csum, tso, vlan;
1209 unsigned int tso_context, vlan_context;
1210 unsigned int tx_coalesce, tx_frames;
1211 int start_index = ring->cur;
1212 int i;
1213
1214 DBGPR("-->xgbe_pre_xmit\n");
1215
1216 csum = XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1217 CSUM_ENABLE);
1218 tso = XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1219 TSO_ENABLE);
1220 vlan = XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1221 VLAN_CTAG);
1222
1223 if (tso && (packet->mss != ring->tx.cur_mss))
1224 tso_context = 1;
1225 else
1226 tso_context = 0;
1227
1228 if (vlan && (packet->vlan_ctag != ring->tx.cur_vlan_ctag))
1229 vlan_context = 1;
1230 else
1231 vlan_context = 0;
1232
1233 tx_coalesce = (pdata->tx_usecs || pdata->tx_frames) ? 1 : 0;
1234 tx_frames = pdata->tx_frames;
1235 if (tx_coalesce && !channel->tx_timer_active)
1236 ring->coalesce_count = 0;
1237
1238 rdata = XGBE_GET_DESC_DATA(ring, ring->cur);
1239 rdesc = rdata->rdesc;
1240
1241
1242 if (tso_context || vlan_context) {
1243 if (tso_context) {
1244 DBGPR(" TSO context descriptor, mss=%u\n",
1245 packet->mss);
1246
1247
1248 XGMAC_SET_BITS_LE(rdesc->desc2, TX_CONTEXT_DESC2,
1249 MSS, packet->mss);
1250
1251
1252 XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3,
1253 CTXT, 1);
1254
1255
1256 XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3,
1257 TCMSSV, 1);
1258
1259 ring->tx.cur_mss = packet->mss;
1260 }
1261
1262 if (vlan_context) {
1263 DBGPR(" VLAN context descriptor, ctag=%u\n",
1264 packet->vlan_ctag);
1265
1266
1267 XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3,
1268 CTXT, 1);
1269
1270
1271 XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3,
1272 VT, packet->vlan_ctag);
1273
1274
1275 XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3,
1276 VLTV, 1);
1277
1278 ring->tx.cur_vlan_ctag = packet->vlan_ctag;
1279 }
1280
1281 ring->cur++;
1282 rdata = XGBE_GET_DESC_DATA(ring, ring->cur);
1283 rdesc = rdata->rdesc;
1284 }
1285
1286
1287 rdesc->desc0 = cpu_to_le32(lower_32_bits(rdata->skb_dma));
1288 rdesc->desc1 = cpu_to_le32(upper_32_bits(rdata->skb_dma));
1289
1290
1291 XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, HL_B1L,
1292 rdata->skb_dma_len);
1293
1294
1295 if (vlan)
1296 XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, VTIR,
1297 TX_NORMAL_DESC2_VLAN_INSERT);
1298
1299
1300 if (XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, PTP))
1301 XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, TTSE, 1);
1302
1303
1304 XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, IC, 1);
1305 if (tx_coalesce && (!tx_frames ||
1306 (++ring->coalesce_count % tx_frames)))
1307
1308 XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, IC, 0);
1309
1310
1311 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, FD, 1);
1312
1313
1314 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, CTXT, 0);
1315
1316
1317 if (ring->cur != start_index)
1318 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, OWN, 1);
1319
1320 if (tso) {
1321
1322 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, TSE, 1);
1323 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, TCPPL,
1324 packet->tcp_payload_len);
1325 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, TCPHDRLEN,
1326 packet->tcp_header_len / 4);
1327 } else {
1328
1329 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, CPC, 0);
1330
1331
1332 if (csum)
1333 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3,
1334 CIC, 0x3);
1335
1336
1337 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, FL,
1338 packet->length);
1339 }
1340
1341 for (i = ring->cur - start_index + 1; i < packet->rdesc_count; i++) {
1342 ring->cur++;
1343 rdata = XGBE_GET_DESC_DATA(ring, ring->cur);
1344 rdesc = rdata->rdesc;
1345
1346
1347 rdesc->desc0 = cpu_to_le32(lower_32_bits(rdata->skb_dma));
1348 rdesc->desc1 = cpu_to_le32(upper_32_bits(rdata->skb_dma));
1349
1350
1351 XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, HL_B1L,
1352 rdata->skb_dma_len);
1353
1354
1355 XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, IC, 1);
1356 if (tx_coalesce && (!tx_frames ||
1357 (++ring->coalesce_count % tx_frames)))
1358
1359 XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, IC, 0);
1360
1361
1362 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, OWN, 1);
1363
1364
1365 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, CTXT, 0);
1366
1367
1368 if (csum)
1369 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3,
1370 CIC, 0x3);
1371 }
1372
1373
1374 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, LD, 1);
1375
1376
1377
1378
1379
1380 wmb();
1381
1382
1383 rdata = XGBE_GET_DESC_DATA(ring, start_index);
1384 rdesc = rdata->rdesc;
1385 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, OWN, 1);
1386
1387#ifdef XGMAC_ENABLE_TX_DESC_DUMP
1388 xgbe_dump_tx_desc(ring, start_index, packet->rdesc_count, 1);
1389#endif
1390
1391
1392 wmb();
1393
1394
1395
1396 ring->cur++;
1397 rdata = XGBE_GET_DESC_DATA(ring, ring->cur);
1398 XGMAC_DMA_IOWRITE(channel, DMA_CH_TDTR_LO,
1399 lower_32_bits(rdata->rdesc_dma));
1400
1401
1402 if (tx_coalesce && !channel->tx_timer_active) {
1403 channel->tx_timer_active = 1;
1404 hrtimer_start(&channel->tx_timer,
1405 ktime_set(0, pdata->tx_usecs * NSEC_PER_USEC),
1406 HRTIMER_MODE_REL);
1407 }
1408
1409 DBGPR(" %s: descriptors %u to %u written\n",
1410 channel->name, start_index & (ring->rdesc_count - 1),
1411 (ring->cur - 1) & (ring->rdesc_count - 1));
1412
1413 DBGPR("<--xgbe_pre_xmit\n");
1414}
1415
1416static int xgbe_dev_read(struct xgbe_channel *channel)
1417{
1418 struct xgbe_ring *ring = channel->rx_ring;
1419 struct xgbe_ring_data *rdata;
1420 struct xgbe_ring_desc *rdesc;
1421 struct xgbe_packet_data *packet = &ring->packet_data;
1422 struct net_device *netdev = channel->pdata->netdev;
1423 unsigned int err, etlt;
1424
1425 DBGPR("-->xgbe_dev_read: cur = %d\n", ring->cur);
1426
1427 rdata = XGBE_GET_DESC_DATA(ring, ring->cur);
1428 rdesc = rdata->rdesc;
1429
1430
1431 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, OWN))
1432 return 1;
1433
1434#ifdef XGMAC_ENABLE_RX_DESC_DUMP
1435 xgbe_dump_rx_desc(ring, rdesc, ring->cur);
1436#endif
1437
1438 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, CTXT)) {
1439
1440 xgbe_get_rx_tstamp(packet, rdesc);
1441
1442 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1443 CONTEXT, 1);
1444 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1445 CONTEXT_NEXT, 0);
1446 return 0;
1447 }
1448
1449
1450 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, CONTEXT, 0);
1451
1452
1453 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, CDA))
1454 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1455 CONTEXT_NEXT, 1);
1456
1457
1458 rdata->len = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, PL);
1459
1460 if (!XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, LD)) {
1461
1462 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1463 INCOMPLETE, 1);
1464 return 0;
1465 }
1466
1467
1468 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1469 INCOMPLETE, 0);
1470
1471
1472 if (channel->pdata->netdev->features & NETIF_F_RXCSUM)
1473 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1474 CSUM_DONE, 1);
1475
1476
1477 err = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, ES);
1478 etlt = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, ETLT);
1479 DBGPR(" err=%u, etlt=%#x\n", err, etlt);
1480
1481 if (!err || (err && !etlt)) {
1482 if ((etlt == 0x09) &&
1483 (netdev->features & NETIF_F_HW_VLAN_CTAG_RX)) {
1484 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1485 VLAN_CTAG, 1);
1486 packet->vlan_ctag = XGMAC_GET_BITS_LE(rdesc->desc0,
1487 RX_NORMAL_DESC0,
1488 OVT);
1489 DBGPR(" vlan-ctag=0x%04x\n", packet->vlan_ctag);
1490 }
1491 } else {
1492 if ((etlt == 0x05) || (etlt == 0x06))
1493 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1494 CSUM_DONE, 0);
1495 else
1496 XGMAC_SET_BITS(packet->errors, RX_PACKET_ERRORS,
1497 FRAME, 1);
1498 }
1499
1500 DBGPR("<--xgbe_dev_read: %s - descriptor=%u (cur=%d)\n", channel->name,
1501 ring->cur & (ring->rdesc_count - 1), ring->cur);
1502
1503 return 0;
1504}
1505
1506static int xgbe_is_context_desc(struct xgbe_ring_desc *rdesc)
1507{
1508
1509 return XGMAC_GET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, CTXT);
1510}
1511
1512static int xgbe_is_last_desc(struct xgbe_ring_desc *rdesc)
1513{
1514
1515 return XGMAC_GET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, LD);
1516}
1517
1518static int xgbe_enable_int(struct xgbe_channel *channel,
1519 enum xgbe_int int_id)
1520{
1521 unsigned int dma_ch_ier;
1522
1523 dma_ch_ier = XGMAC_DMA_IOREAD(channel, DMA_CH_IER);
1524
1525 switch (int_id) {
1526 case XGMAC_INT_DMA_CH_SR_TI:
1527 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TIE, 1);
1528 break;
1529 case XGMAC_INT_DMA_CH_SR_TPS:
1530 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TXSE, 1);
1531 break;
1532 case XGMAC_INT_DMA_CH_SR_TBU:
1533 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TBUE, 1);
1534 break;
1535 case XGMAC_INT_DMA_CH_SR_RI:
1536 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RIE, 1);
1537 break;
1538 case XGMAC_INT_DMA_CH_SR_RBU:
1539 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RBUE, 1);
1540 break;
1541 case XGMAC_INT_DMA_CH_SR_RPS:
1542 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RSE, 1);
1543 break;
1544 case XGMAC_INT_DMA_CH_SR_TI_RI:
1545 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TIE, 1);
1546 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RIE, 1);
1547 break;
1548 case XGMAC_INT_DMA_CH_SR_FBE:
1549 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, FBEE, 1);
1550 break;
1551 case XGMAC_INT_DMA_ALL:
1552 dma_ch_ier |= channel->saved_ier;
1553 break;
1554 default:
1555 return -1;
1556 }
1557
1558 XGMAC_DMA_IOWRITE(channel, DMA_CH_IER, dma_ch_ier);
1559
1560 return 0;
1561}
1562
1563static int xgbe_disable_int(struct xgbe_channel *channel,
1564 enum xgbe_int int_id)
1565{
1566 unsigned int dma_ch_ier;
1567
1568 dma_ch_ier = XGMAC_DMA_IOREAD(channel, DMA_CH_IER);
1569
1570 switch (int_id) {
1571 case XGMAC_INT_DMA_CH_SR_TI:
1572 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TIE, 0);
1573 break;
1574 case XGMAC_INT_DMA_CH_SR_TPS:
1575 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TXSE, 0);
1576 break;
1577 case XGMAC_INT_DMA_CH_SR_TBU:
1578 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TBUE, 0);
1579 break;
1580 case XGMAC_INT_DMA_CH_SR_RI:
1581 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RIE, 0);
1582 break;
1583 case XGMAC_INT_DMA_CH_SR_RBU:
1584 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RBUE, 0);
1585 break;
1586 case XGMAC_INT_DMA_CH_SR_RPS:
1587 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RSE, 0);
1588 break;
1589 case XGMAC_INT_DMA_CH_SR_TI_RI:
1590 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TIE, 0);
1591 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RIE, 0);
1592 break;
1593 case XGMAC_INT_DMA_CH_SR_FBE:
1594 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, FBEE, 0);
1595 break;
1596 case XGMAC_INT_DMA_ALL:
1597 channel->saved_ier = dma_ch_ier & XGBE_DMA_INTERRUPT_MASK;
1598 dma_ch_ier &= ~XGBE_DMA_INTERRUPT_MASK;
1599 break;
1600 default:
1601 return -1;
1602 }
1603
1604 XGMAC_DMA_IOWRITE(channel, DMA_CH_IER, dma_ch_ier);
1605
1606 return 0;
1607}
1608
1609static int xgbe_exit(struct xgbe_prv_data *pdata)
1610{
1611 unsigned int count = 2000;
1612
1613 DBGPR("-->xgbe_exit\n");
1614
1615
1616 XGMAC_IOWRITE_BITS(pdata, DMA_MR, SWR, 1);
1617 usleep_range(10, 15);
1618
1619
1620 while (count-- && XGMAC_IOREAD_BITS(pdata, DMA_MR, SWR))
1621 usleep_range(500, 600);
1622
1623 if (!count)
1624 return -EBUSY;
1625
1626 DBGPR("<--xgbe_exit\n");
1627
1628 return 0;
1629}
1630
1631static int xgbe_flush_tx_queues(struct xgbe_prv_data *pdata)
1632{
1633 unsigned int i, count;
1634
1635 if (XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER) < 0x21)
1636 return 0;
1637
1638 for (i = 0; i < pdata->tx_q_count; i++)
1639 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, FTQ, 1);
1640
1641
1642 for (i = 0; i < pdata->tx_q_count; i++) {
1643 count = 2000;
1644 while (count-- && XGMAC_MTL_IOREAD_BITS(pdata, i,
1645 MTL_Q_TQOMR, FTQ))
1646 usleep_range(500, 600);
1647
1648 if (!count)
1649 return -EBUSY;
1650 }
1651
1652 return 0;
1653}
1654
1655static void xgbe_config_dma_bus(struct xgbe_prv_data *pdata)
1656{
1657
1658 XGMAC_IOWRITE_BITS(pdata, DMA_SBMR, EAME, 1);
1659
1660
1661 XGMAC_IOWRITE_BITS(pdata, DMA_SBMR, UNDEF, 1);
1662 XGMAC_IOWRITE_BITS(pdata, DMA_SBMR, BLEN_256, 1);
1663}
1664
1665static void xgbe_config_dma_cache(struct xgbe_prv_data *pdata)
1666{
1667 unsigned int arcache, awcache;
1668
1669 arcache = 0;
1670 XGMAC_SET_BITS(arcache, DMA_AXIARCR, DRC, pdata->arcache);
1671 XGMAC_SET_BITS(arcache, DMA_AXIARCR, DRD, pdata->axdomain);
1672 XGMAC_SET_BITS(arcache, DMA_AXIARCR, TEC, pdata->arcache);
1673 XGMAC_SET_BITS(arcache, DMA_AXIARCR, TED, pdata->axdomain);
1674 XGMAC_SET_BITS(arcache, DMA_AXIARCR, THC, pdata->arcache);
1675 XGMAC_SET_BITS(arcache, DMA_AXIARCR, THD, pdata->axdomain);
1676 XGMAC_IOWRITE(pdata, DMA_AXIARCR, arcache);
1677
1678 awcache = 0;
1679 XGMAC_SET_BITS(awcache, DMA_AXIAWCR, DWC, pdata->awcache);
1680 XGMAC_SET_BITS(awcache, DMA_AXIAWCR, DWD, pdata->axdomain);
1681 XGMAC_SET_BITS(awcache, DMA_AXIAWCR, RPC, pdata->awcache);
1682 XGMAC_SET_BITS(awcache, DMA_AXIAWCR, RPD, pdata->axdomain);
1683 XGMAC_SET_BITS(awcache, DMA_AXIAWCR, RHC, pdata->awcache);
1684 XGMAC_SET_BITS(awcache, DMA_AXIAWCR, RHD, pdata->axdomain);
1685 XGMAC_SET_BITS(awcache, DMA_AXIAWCR, TDC, pdata->awcache);
1686 XGMAC_SET_BITS(awcache, DMA_AXIAWCR, TDD, pdata->axdomain);
1687 XGMAC_IOWRITE(pdata, DMA_AXIAWCR, awcache);
1688}
1689
1690static void xgbe_config_mtl_mode(struct xgbe_prv_data *pdata)
1691{
1692 unsigned int i;
1693
1694
1695 XGMAC_IOWRITE_BITS(pdata, MTL_OMR, ETSALG, MTL_ETSALG_WRR);
1696
1697
1698 for (i = 0; i < pdata->hw_feat.tc_cnt; i++) {
1699 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_ETSCR, TSA,
1700 MTL_TSA_ETS);
1701 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_QWR, QW, 1);
1702 }
1703
1704
1705 XGMAC_IOWRITE_BITS(pdata, MTL_OMR, RAA, MTL_RAA_SP);
1706}
1707
1708static unsigned int xgbe_calculate_per_queue_fifo(unsigned int fifo_size,
1709 unsigned int queue_count)
1710{
1711 unsigned int q_fifo_size = 0;
1712 enum xgbe_mtl_fifo_size p_fifo = XGMAC_MTL_FIFO_SIZE_256;
1713
1714
1715 switch (fifo_size) {
1716 case 0:
1717 q_fifo_size = XGBE_FIFO_SIZE_B(128);
1718 break;
1719 case 1:
1720 q_fifo_size = XGBE_FIFO_SIZE_B(256);
1721 break;
1722 case 2:
1723 q_fifo_size = XGBE_FIFO_SIZE_B(512);
1724 break;
1725 case 3:
1726 q_fifo_size = XGBE_FIFO_SIZE_KB(1);
1727 break;
1728 case 4:
1729 q_fifo_size = XGBE_FIFO_SIZE_KB(2);
1730 break;
1731 case 5:
1732 q_fifo_size = XGBE_FIFO_SIZE_KB(4);
1733 break;
1734 case 6:
1735 q_fifo_size = XGBE_FIFO_SIZE_KB(8);
1736 break;
1737 case 7:
1738 q_fifo_size = XGBE_FIFO_SIZE_KB(16);
1739 break;
1740 case 8:
1741 q_fifo_size = XGBE_FIFO_SIZE_KB(32);
1742 break;
1743 case 9:
1744 q_fifo_size = XGBE_FIFO_SIZE_KB(64);
1745 break;
1746 case 10:
1747 q_fifo_size = XGBE_FIFO_SIZE_KB(128);
1748 break;
1749 case 11:
1750 q_fifo_size = XGBE_FIFO_SIZE_KB(256);
1751 break;
1752 }
1753
1754
1755 q_fifo_size = min_t(unsigned int, XGBE_FIFO_MAX, q_fifo_size);
1756
1757 q_fifo_size = q_fifo_size / queue_count;
1758
1759
1760 if (q_fifo_size >= XGBE_FIFO_SIZE_KB(256))
1761 p_fifo = XGMAC_MTL_FIFO_SIZE_256K;
1762 else if (q_fifo_size >= XGBE_FIFO_SIZE_KB(128))
1763 p_fifo = XGMAC_MTL_FIFO_SIZE_128K;
1764 else if (q_fifo_size >= XGBE_FIFO_SIZE_KB(64))
1765 p_fifo = XGMAC_MTL_FIFO_SIZE_64K;
1766 else if (q_fifo_size >= XGBE_FIFO_SIZE_KB(32))
1767 p_fifo = XGMAC_MTL_FIFO_SIZE_32K;
1768 else if (q_fifo_size >= XGBE_FIFO_SIZE_KB(16))
1769 p_fifo = XGMAC_MTL_FIFO_SIZE_16K;
1770 else if (q_fifo_size >= XGBE_FIFO_SIZE_KB(8))
1771 p_fifo = XGMAC_MTL_FIFO_SIZE_8K;
1772 else if (q_fifo_size >= XGBE_FIFO_SIZE_KB(4))
1773 p_fifo = XGMAC_MTL_FIFO_SIZE_4K;
1774 else if (q_fifo_size >= XGBE_FIFO_SIZE_KB(2))
1775 p_fifo = XGMAC_MTL_FIFO_SIZE_2K;
1776 else if (q_fifo_size >= XGBE_FIFO_SIZE_KB(1))
1777 p_fifo = XGMAC_MTL_FIFO_SIZE_1K;
1778 else if (q_fifo_size >= XGBE_FIFO_SIZE_B(512))
1779 p_fifo = XGMAC_MTL_FIFO_SIZE_512;
1780 else if (q_fifo_size >= XGBE_FIFO_SIZE_B(256))
1781 p_fifo = XGMAC_MTL_FIFO_SIZE_256;
1782
1783 return p_fifo;
1784}
1785
1786static void xgbe_config_tx_fifo_size(struct xgbe_prv_data *pdata)
1787{
1788 enum xgbe_mtl_fifo_size fifo_size;
1789 unsigned int i;
1790
1791 fifo_size = xgbe_calculate_per_queue_fifo(pdata->hw_feat.tx_fifo_size,
1792 pdata->tx_q_count);
1793
1794 for (i = 0; i < pdata->tx_q_count; i++)
1795 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TQS, fifo_size);
1796
1797 netdev_notice(pdata->netdev, "%d Tx queues, %d byte fifo per queue\n",
1798 pdata->tx_q_count, ((fifo_size + 1) * 256));
1799}
1800
1801static void xgbe_config_rx_fifo_size(struct xgbe_prv_data *pdata)
1802{
1803 enum xgbe_mtl_fifo_size fifo_size;
1804 unsigned int i;
1805
1806 fifo_size = xgbe_calculate_per_queue_fifo(pdata->hw_feat.rx_fifo_size,
1807 pdata->rx_q_count);
1808
1809 for (i = 0; i < pdata->rx_q_count; i++)
1810 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RQS, fifo_size);
1811
1812 netdev_notice(pdata->netdev, "%d Rx queues, %d byte fifo per queue\n",
1813 pdata->rx_q_count, ((fifo_size + 1) * 256));
1814}
1815
1816static void xgbe_config_queue_mapping(struct xgbe_prv_data *pdata)
1817{
1818 unsigned int qptc, qptc_extra, queue;
1819 unsigned int prio_queues;
1820 unsigned int ppq, ppq_extra, prio;
1821 unsigned int mask;
1822 unsigned int i, j, reg, reg_val;
1823
1824
1825
1826
1827 qptc = pdata->tx_q_count / pdata->hw_feat.tc_cnt;
1828 qptc_extra = pdata->tx_q_count % pdata->hw_feat.tc_cnt;
1829
1830 for (i = 0, queue = 0; i < pdata->hw_feat.tc_cnt; i++) {
1831 for (j = 0; j < qptc; j++) {
1832 DBGPR(" TXq%u mapped to TC%u\n", queue, i);
1833 XGMAC_MTL_IOWRITE_BITS(pdata, queue, MTL_Q_TQOMR,
1834 Q2TCMAP, i);
1835 pdata->q2tc_map[queue++] = i;
1836 }
1837
1838 if (i < qptc_extra) {
1839 DBGPR(" TXq%u mapped to TC%u\n", queue, i);
1840 XGMAC_MTL_IOWRITE_BITS(pdata, queue, MTL_Q_TQOMR,
1841 Q2TCMAP, i);
1842 pdata->q2tc_map[queue++] = i;
1843 }
1844 }
1845
1846
1847 prio_queues = min_t(unsigned int, IEEE_8021QAZ_MAX_TCS,
1848 pdata->rx_q_count);
1849 ppq = IEEE_8021QAZ_MAX_TCS / prio_queues;
1850 ppq_extra = IEEE_8021QAZ_MAX_TCS % prio_queues;
1851
1852 reg = MAC_RQC2R;
1853 reg_val = 0;
1854 for (i = 0, prio = 0; i < prio_queues;) {
1855 mask = 0;
1856 for (j = 0; j < ppq; j++) {
1857 DBGPR(" PRIO%u mapped to RXq%u\n", prio, i);
1858 mask |= (1 << prio);
1859 pdata->prio2q_map[prio++] = i;
1860 }
1861
1862 if (i < ppq_extra) {
1863 DBGPR(" PRIO%u mapped to RXq%u\n", prio, i);
1864 mask |= (1 << prio);
1865 pdata->prio2q_map[prio++] = i;
1866 }
1867
1868 reg_val |= (mask << ((i++ % MAC_RQC2_Q_PER_REG) << 3));
1869
1870 if ((i % MAC_RQC2_Q_PER_REG) && (i != prio_queues))
1871 continue;
1872
1873 XGMAC_IOWRITE(pdata, reg, reg_val);
1874 reg += MAC_RQC2_INC;
1875 reg_val = 0;
1876 }
1877
1878
1879 reg = MTL_RQDCM0R;
1880 reg_val = 0;
1881 for (i = 0; i < pdata->rx_q_count;) {
1882 reg_val |= (0x80 << ((i++ % MTL_RQDCM_Q_PER_REG) << 3));
1883
1884 if ((i % MTL_RQDCM_Q_PER_REG) && (i != pdata->rx_q_count))
1885 continue;
1886
1887 XGMAC_IOWRITE(pdata, reg, reg_val);
1888
1889 reg += MTL_RQDCM_INC;
1890 reg_val = 0;
1891 }
1892}
1893
1894static void xgbe_config_flow_control_threshold(struct xgbe_prv_data *pdata)
1895{
1896 unsigned int i;
1897
1898 for (i = 0; i < pdata->rx_q_count; i++) {
1899
1900 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RFA, 2);
1901
1902
1903 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RFD, 4);
1904 }
1905}
1906
1907static void xgbe_config_mac_address(struct xgbe_prv_data *pdata)
1908{
1909 xgbe_set_mac_address(pdata, pdata->netdev->dev_addr);
1910
1911
1912 if (pdata->hw_feat.hash_table_size) {
1913 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, HPF, 1);
1914 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, HUC, 1);
1915 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, HMC, 1);
1916 }
1917}
1918
1919static void xgbe_config_jumbo_enable(struct xgbe_prv_data *pdata)
1920{
1921 unsigned int val;
1922
1923 val = (pdata->netdev->mtu > XGMAC_STD_PACKET_MTU) ? 1 : 0;
1924
1925 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, JE, val);
1926}
1927
1928static void xgbe_config_checksum_offload(struct xgbe_prv_data *pdata)
1929{
1930 if (pdata->netdev->features & NETIF_F_RXCSUM)
1931 xgbe_enable_rx_csum(pdata);
1932 else
1933 xgbe_disable_rx_csum(pdata);
1934}
1935
1936static void xgbe_config_vlan_support(struct xgbe_prv_data *pdata)
1937{
1938
1939 XGMAC_IOWRITE_BITS(pdata, MAC_VLANIR, CSVL, 0);
1940 XGMAC_IOWRITE_BITS(pdata, MAC_VLANIR, VLTI, 1);
1941
1942
1943 xgbe_update_vlan_hash_table(pdata);
1944
1945 if (pdata->netdev->features & NETIF_F_HW_VLAN_CTAG_FILTER)
1946 xgbe_enable_rx_vlan_filtering(pdata);
1947 else
1948 xgbe_disable_rx_vlan_filtering(pdata);
1949
1950 if (pdata->netdev->features & NETIF_F_HW_VLAN_CTAG_RX)
1951 xgbe_enable_rx_vlan_stripping(pdata);
1952 else
1953 xgbe_disable_rx_vlan_stripping(pdata);
1954}
1955
1956static u64 xgbe_mmc_read(struct xgbe_prv_data *pdata, unsigned int reg_lo)
1957{
1958 bool read_hi;
1959 u64 val;
1960
1961 switch (reg_lo) {
1962
1963 case MMC_TXOCTETCOUNT_GB_LO:
1964 case MMC_TXOCTETCOUNT_G_LO:
1965 case MMC_RXOCTETCOUNT_GB_LO:
1966 case MMC_RXOCTETCOUNT_G_LO:
1967 read_hi = true;
1968 break;
1969
1970 default:
1971 read_hi = false;
1972 };
1973
1974 val = XGMAC_IOREAD(pdata, reg_lo);
1975
1976 if (read_hi)
1977 val |= ((u64)XGMAC_IOREAD(pdata, reg_lo + 4) << 32);
1978
1979 return val;
1980}
1981
1982static void xgbe_tx_mmc_int(struct xgbe_prv_data *pdata)
1983{
1984 struct xgbe_mmc_stats *stats = &pdata->mmc_stats;
1985 unsigned int mmc_isr = XGMAC_IOREAD(pdata, MMC_TISR);
1986
1987 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXOCTETCOUNT_GB))
1988 stats->txoctetcount_gb +=
1989 xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_GB_LO);
1990
1991 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXFRAMECOUNT_GB))
1992 stats->txframecount_gb +=
1993 xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_GB_LO);
1994
1995 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXBROADCASTFRAMES_G))
1996 stats->txbroadcastframes_g +=
1997 xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_G_LO);
1998
1999 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXMULTICASTFRAMES_G))
2000 stats->txmulticastframes_g +=
2001 xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_G_LO);
2002
2003 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX64OCTETS_GB))
2004 stats->tx64octets_gb +=
2005 xgbe_mmc_read(pdata, MMC_TX64OCTETS_GB_LO);
2006
2007 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX65TO127OCTETS_GB))
2008 stats->tx65to127octets_gb +=
2009 xgbe_mmc_read(pdata, MMC_TX65TO127OCTETS_GB_LO);
2010
2011 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX128TO255OCTETS_GB))
2012 stats->tx128to255octets_gb +=
2013 xgbe_mmc_read(pdata, MMC_TX128TO255OCTETS_GB_LO);
2014
2015 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX256TO511OCTETS_GB))
2016 stats->tx256to511octets_gb +=
2017 xgbe_mmc_read(pdata, MMC_TX256TO511OCTETS_GB_LO);
2018
2019 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX512TO1023OCTETS_GB))
2020 stats->tx512to1023octets_gb +=
2021 xgbe_mmc_read(pdata, MMC_TX512TO1023OCTETS_GB_LO);
2022
2023 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX1024TOMAXOCTETS_GB))
2024 stats->tx1024tomaxoctets_gb +=
2025 xgbe_mmc_read(pdata, MMC_TX1024TOMAXOCTETS_GB_LO);
2026
2027 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXUNICASTFRAMES_GB))
2028 stats->txunicastframes_gb +=
2029 xgbe_mmc_read(pdata, MMC_TXUNICASTFRAMES_GB_LO);
2030
2031 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXMULTICASTFRAMES_GB))
2032 stats->txmulticastframes_gb +=
2033 xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_GB_LO);
2034
2035 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXBROADCASTFRAMES_GB))
2036 stats->txbroadcastframes_g +=
2037 xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_GB_LO);
2038
2039 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXUNDERFLOWERROR))
2040 stats->txunderflowerror +=
2041 xgbe_mmc_read(pdata, MMC_TXUNDERFLOWERROR_LO);
2042
2043 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXOCTETCOUNT_G))
2044 stats->txoctetcount_g +=
2045 xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_G_LO);
2046
2047 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXFRAMECOUNT_G))
2048 stats->txframecount_g +=
2049 xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_G_LO);
2050
2051 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXPAUSEFRAMES))
2052 stats->txpauseframes +=
2053 xgbe_mmc_read(pdata, MMC_TXPAUSEFRAMES_LO);
2054
2055 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXVLANFRAMES_G))
2056 stats->txvlanframes_g +=
2057 xgbe_mmc_read(pdata, MMC_TXVLANFRAMES_G_LO);
2058}
2059
2060static void xgbe_rx_mmc_int(struct xgbe_prv_data *pdata)
2061{
2062 struct xgbe_mmc_stats *stats = &pdata->mmc_stats;
2063 unsigned int mmc_isr = XGMAC_IOREAD(pdata, MMC_RISR);
2064
2065 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXFRAMECOUNT_GB))
2066 stats->rxframecount_gb +=
2067 xgbe_mmc_read(pdata, MMC_RXFRAMECOUNT_GB_LO);
2068
2069 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXOCTETCOUNT_GB))
2070 stats->rxoctetcount_gb +=
2071 xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_GB_LO);
2072
2073 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXOCTETCOUNT_G))
2074 stats->rxoctetcount_g +=
2075 xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_G_LO);
2076
2077 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXBROADCASTFRAMES_G))
2078 stats->rxbroadcastframes_g +=
2079 xgbe_mmc_read(pdata, MMC_RXBROADCASTFRAMES_G_LO);
2080
2081 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXMULTICASTFRAMES_G))
2082 stats->rxmulticastframes_g +=
2083 xgbe_mmc_read(pdata, MMC_RXMULTICASTFRAMES_G_LO);
2084
2085 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXCRCERROR))
2086 stats->rxcrcerror +=
2087 xgbe_mmc_read(pdata, MMC_RXCRCERROR_LO);
2088
2089 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXRUNTERROR))
2090 stats->rxrunterror +=
2091 xgbe_mmc_read(pdata, MMC_RXRUNTERROR);
2092
2093 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXJABBERERROR))
2094 stats->rxjabbererror +=
2095 xgbe_mmc_read(pdata, MMC_RXJABBERERROR);
2096
2097 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXUNDERSIZE_G))
2098 stats->rxundersize_g +=
2099 xgbe_mmc_read(pdata, MMC_RXUNDERSIZE_G);
2100
2101 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXOVERSIZE_G))
2102 stats->rxoversize_g +=
2103 xgbe_mmc_read(pdata, MMC_RXOVERSIZE_G);
2104
2105 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX64OCTETS_GB))
2106 stats->rx64octets_gb +=
2107 xgbe_mmc_read(pdata, MMC_RX64OCTETS_GB_LO);
2108
2109 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX65TO127OCTETS_GB))
2110 stats->rx65to127octets_gb +=
2111 xgbe_mmc_read(pdata, MMC_RX65TO127OCTETS_GB_LO);
2112
2113 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX128TO255OCTETS_GB))
2114 stats->rx128to255octets_gb +=
2115 xgbe_mmc_read(pdata, MMC_RX128TO255OCTETS_GB_LO);
2116
2117 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX256TO511OCTETS_GB))
2118 stats->rx256to511octets_gb +=
2119 xgbe_mmc_read(pdata, MMC_RX256TO511OCTETS_GB_LO);
2120
2121 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX512TO1023OCTETS_GB))
2122 stats->rx512to1023octets_gb +=
2123 xgbe_mmc_read(pdata, MMC_RX512TO1023OCTETS_GB_LO);
2124
2125 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX1024TOMAXOCTETS_GB))
2126 stats->rx1024tomaxoctets_gb +=
2127 xgbe_mmc_read(pdata, MMC_RX1024TOMAXOCTETS_GB_LO);
2128
2129 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXUNICASTFRAMES_G))
2130 stats->rxunicastframes_g +=
2131 xgbe_mmc_read(pdata, MMC_RXUNICASTFRAMES_G_LO);
2132
2133 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXLENGTHERROR))
2134 stats->rxlengtherror +=
2135 xgbe_mmc_read(pdata, MMC_RXLENGTHERROR_LO);
2136
2137 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXOUTOFRANGETYPE))
2138 stats->rxoutofrangetype +=
2139 xgbe_mmc_read(pdata, MMC_RXOUTOFRANGETYPE_LO);
2140
2141 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXPAUSEFRAMES))
2142 stats->rxpauseframes +=
2143 xgbe_mmc_read(pdata, MMC_RXPAUSEFRAMES_LO);
2144
2145 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXFIFOOVERFLOW))
2146 stats->rxfifooverflow +=
2147 xgbe_mmc_read(pdata, MMC_RXFIFOOVERFLOW_LO);
2148
2149 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXVLANFRAMES_GB))
2150 stats->rxvlanframes_gb +=
2151 xgbe_mmc_read(pdata, MMC_RXVLANFRAMES_GB_LO);
2152
2153 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXWATCHDOGERROR))
2154 stats->rxwatchdogerror +=
2155 xgbe_mmc_read(pdata, MMC_RXWATCHDOGERROR);
2156}
2157
2158static void xgbe_read_mmc_stats(struct xgbe_prv_data *pdata)
2159{
2160 struct xgbe_mmc_stats *stats = &pdata->mmc_stats;
2161
2162
2163 XGMAC_IOWRITE_BITS(pdata, MMC_CR, MCF, 1);
2164
2165 stats->txoctetcount_gb +=
2166 xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_GB_LO);
2167
2168 stats->txframecount_gb +=
2169 xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_GB_LO);
2170
2171 stats->txbroadcastframes_g +=
2172 xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_G_LO);
2173
2174 stats->txmulticastframes_g +=
2175 xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_G_LO);
2176
2177 stats->tx64octets_gb +=
2178 xgbe_mmc_read(pdata, MMC_TX64OCTETS_GB_LO);
2179
2180 stats->tx65to127octets_gb +=
2181 xgbe_mmc_read(pdata, MMC_TX65TO127OCTETS_GB_LO);
2182
2183 stats->tx128to255octets_gb +=
2184 xgbe_mmc_read(pdata, MMC_TX128TO255OCTETS_GB_LO);
2185
2186 stats->tx256to511octets_gb +=
2187 xgbe_mmc_read(pdata, MMC_TX256TO511OCTETS_GB_LO);
2188
2189 stats->tx512to1023octets_gb +=
2190 xgbe_mmc_read(pdata, MMC_TX512TO1023OCTETS_GB_LO);
2191
2192 stats->tx1024tomaxoctets_gb +=
2193 xgbe_mmc_read(pdata, MMC_TX1024TOMAXOCTETS_GB_LO);
2194
2195 stats->txunicastframes_gb +=
2196 xgbe_mmc_read(pdata, MMC_TXUNICASTFRAMES_GB_LO);
2197
2198 stats->txmulticastframes_gb +=
2199 xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_GB_LO);
2200
2201 stats->txbroadcastframes_g +=
2202 xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_GB_LO);
2203
2204 stats->txunderflowerror +=
2205 xgbe_mmc_read(pdata, MMC_TXUNDERFLOWERROR_LO);
2206
2207 stats->txoctetcount_g +=
2208 xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_G_LO);
2209
2210 stats->txframecount_g +=
2211 xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_G_LO);
2212
2213 stats->txpauseframes +=
2214 xgbe_mmc_read(pdata, MMC_TXPAUSEFRAMES_LO);
2215
2216 stats->txvlanframes_g +=
2217 xgbe_mmc_read(pdata, MMC_TXVLANFRAMES_G_LO);
2218
2219 stats->rxframecount_gb +=
2220 xgbe_mmc_read(pdata, MMC_RXFRAMECOUNT_GB_LO);
2221
2222 stats->rxoctetcount_gb +=
2223 xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_GB_LO);
2224
2225 stats->rxoctetcount_g +=
2226 xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_G_LO);
2227
2228 stats->rxbroadcastframes_g +=
2229 xgbe_mmc_read(pdata, MMC_RXBROADCASTFRAMES_G_LO);
2230
2231 stats->rxmulticastframes_g +=
2232 xgbe_mmc_read(pdata, MMC_RXMULTICASTFRAMES_G_LO);
2233
2234 stats->rxcrcerror +=
2235 xgbe_mmc_read(pdata, MMC_RXCRCERROR_LO);
2236
2237 stats->rxrunterror +=
2238 xgbe_mmc_read(pdata, MMC_RXRUNTERROR);
2239
2240 stats->rxjabbererror +=
2241 xgbe_mmc_read(pdata, MMC_RXJABBERERROR);
2242
2243 stats->rxundersize_g +=
2244 xgbe_mmc_read(pdata, MMC_RXUNDERSIZE_G);
2245
2246 stats->rxoversize_g +=
2247 xgbe_mmc_read(pdata, MMC_RXOVERSIZE_G);
2248
2249 stats->rx64octets_gb +=
2250 xgbe_mmc_read(pdata, MMC_RX64OCTETS_GB_LO);
2251
2252 stats->rx65to127octets_gb +=
2253 xgbe_mmc_read(pdata, MMC_RX65TO127OCTETS_GB_LO);
2254
2255 stats->rx128to255octets_gb +=
2256 xgbe_mmc_read(pdata, MMC_RX128TO255OCTETS_GB_LO);
2257
2258 stats->rx256to511octets_gb +=
2259 xgbe_mmc_read(pdata, MMC_RX256TO511OCTETS_GB_LO);
2260
2261 stats->rx512to1023octets_gb +=
2262 xgbe_mmc_read(pdata, MMC_RX512TO1023OCTETS_GB_LO);
2263
2264 stats->rx1024tomaxoctets_gb +=
2265 xgbe_mmc_read(pdata, MMC_RX1024TOMAXOCTETS_GB_LO);
2266
2267 stats->rxunicastframes_g +=
2268 xgbe_mmc_read(pdata, MMC_RXUNICASTFRAMES_G_LO);
2269
2270 stats->rxlengtherror +=
2271 xgbe_mmc_read(pdata, MMC_RXLENGTHERROR_LO);
2272
2273 stats->rxoutofrangetype +=
2274 xgbe_mmc_read(pdata, MMC_RXOUTOFRANGETYPE_LO);
2275
2276 stats->rxpauseframes +=
2277 xgbe_mmc_read(pdata, MMC_RXPAUSEFRAMES_LO);
2278
2279 stats->rxfifooverflow +=
2280 xgbe_mmc_read(pdata, MMC_RXFIFOOVERFLOW_LO);
2281
2282 stats->rxvlanframes_gb +=
2283 xgbe_mmc_read(pdata, MMC_RXVLANFRAMES_GB_LO);
2284
2285 stats->rxwatchdogerror +=
2286 xgbe_mmc_read(pdata, MMC_RXWATCHDOGERROR);
2287
2288
2289 XGMAC_IOWRITE_BITS(pdata, MMC_CR, MCF, 0);
2290}
2291
2292static void xgbe_config_mmc(struct xgbe_prv_data *pdata)
2293{
2294
2295 XGMAC_IOWRITE_BITS(pdata, MMC_CR, ROR, 1);
2296
2297
2298 XGMAC_IOWRITE_BITS(pdata, MMC_CR, CR, 1);
2299}
2300
2301static void xgbe_enable_tx(struct xgbe_prv_data *pdata)
2302{
2303 struct xgbe_channel *channel;
2304 unsigned int i;
2305
2306
2307 channel = pdata->channel;
2308 for (i = 0; i < pdata->channel_count; i++, channel++) {
2309 if (!channel->tx_ring)
2310 break;
2311
2312 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, ST, 1);
2313 }
2314
2315
2316 for (i = 0; i < pdata->tx_q_count; i++)
2317 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TXQEN,
2318 MTL_Q_ENABLED);
2319
2320
2321 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 1);
2322}
2323
2324static void xgbe_disable_tx(struct xgbe_prv_data *pdata)
2325{
2326 struct xgbe_channel *channel;
2327 unsigned int i;
2328
2329
2330 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 0);
2331
2332
2333 for (i = 0; i < pdata->tx_q_count; i++)
2334 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TXQEN, 0);
2335
2336
2337 channel = pdata->channel;
2338 for (i = 0; i < pdata->channel_count; i++, channel++) {
2339 if (!channel->tx_ring)
2340 break;
2341
2342 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, ST, 0);
2343 }
2344}
2345
2346static void xgbe_enable_rx(struct xgbe_prv_data *pdata)
2347{
2348 struct xgbe_channel *channel;
2349 unsigned int reg_val, i;
2350
2351
2352 channel = pdata->channel;
2353 for (i = 0; i < pdata->channel_count; i++, channel++) {
2354 if (!channel->rx_ring)
2355 break;
2356
2357 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RCR, SR, 1);
2358 }
2359
2360
2361 reg_val = 0;
2362 for (i = 0; i < pdata->rx_q_count; i++)
2363 reg_val |= (0x02 << (i << 1));
2364 XGMAC_IOWRITE(pdata, MAC_RQC0R, reg_val);
2365
2366
2367 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, DCRCC, 1);
2368 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, CST, 1);
2369 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, ACS, 1);
2370 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, RE, 1);
2371}
2372
2373static void xgbe_disable_rx(struct xgbe_prv_data *pdata)
2374{
2375 struct xgbe_channel *channel;
2376 unsigned int i;
2377
2378
2379 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, DCRCC, 0);
2380 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, CST, 0);
2381 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, ACS, 0);
2382 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, RE, 0);
2383
2384
2385 XGMAC_IOWRITE(pdata, MAC_RQC0R, 0);
2386
2387
2388 channel = pdata->channel;
2389 for (i = 0; i < pdata->channel_count; i++, channel++) {
2390 if (!channel->rx_ring)
2391 break;
2392
2393 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RCR, SR, 0);
2394 }
2395}
2396
2397static void xgbe_powerup_tx(struct xgbe_prv_data *pdata)
2398{
2399 struct xgbe_channel *channel;
2400 unsigned int i;
2401
2402
2403 channel = pdata->channel;
2404 for (i = 0; i < pdata->channel_count; i++, channel++) {
2405 if (!channel->tx_ring)
2406 break;
2407
2408 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, ST, 1);
2409 }
2410
2411
2412 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 1);
2413}
2414
2415static void xgbe_powerdown_tx(struct xgbe_prv_data *pdata)
2416{
2417 struct xgbe_channel *channel;
2418 unsigned int i;
2419
2420
2421 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 0);
2422
2423
2424 channel = pdata->channel;
2425 for (i = 0; i < pdata->channel_count; i++, channel++) {
2426 if (!channel->tx_ring)
2427 break;
2428
2429 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, ST, 0);
2430 }
2431}
2432
2433static void xgbe_powerup_rx(struct xgbe_prv_data *pdata)
2434{
2435 struct xgbe_channel *channel;
2436 unsigned int i;
2437
2438
2439 channel = pdata->channel;
2440 for (i = 0; i < pdata->channel_count; i++, channel++) {
2441 if (!channel->rx_ring)
2442 break;
2443
2444 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RCR, SR, 1);
2445 }
2446}
2447
2448static void xgbe_powerdown_rx(struct xgbe_prv_data *pdata)
2449{
2450 struct xgbe_channel *channel;
2451 unsigned int i;
2452
2453
2454 channel = pdata->channel;
2455 for (i = 0; i < pdata->channel_count; i++, channel++) {
2456 if (!channel->rx_ring)
2457 break;
2458
2459 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RCR, SR, 0);
2460 }
2461}
2462
2463static int xgbe_init(struct xgbe_prv_data *pdata)
2464{
2465 struct xgbe_desc_if *desc_if = &pdata->desc_if;
2466 int ret;
2467
2468 DBGPR("-->xgbe_init\n");
2469
2470
2471 ret = xgbe_flush_tx_queues(pdata);
2472 if (ret)
2473 return ret;
2474
2475
2476
2477
2478 xgbe_config_dma_bus(pdata);
2479 xgbe_config_dma_cache(pdata);
2480 xgbe_config_osp_mode(pdata);
2481 xgbe_config_pblx8(pdata);
2482 xgbe_config_tx_pbl_val(pdata);
2483 xgbe_config_rx_pbl_val(pdata);
2484 xgbe_config_rx_coalesce(pdata);
2485 xgbe_config_tx_coalesce(pdata);
2486 xgbe_config_rx_buffer_size(pdata);
2487 xgbe_config_tso_mode(pdata);
2488 desc_if->wrapper_tx_desc_init(pdata);
2489 desc_if->wrapper_rx_desc_init(pdata);
2490 xgbe_enable_dma_interrupts(pdata);
2491
2492
2493
2494
2495 xgbe_config_mtl_mode(pdata);
2496 xgbe_config_queue_mapping(pdata);
2497 xgbe_config_tsf_mode(pdata, pdata->tx_sf_mode);
2498 xgbe_config_rsf_mode(pdata, pdata->rx_sf_mode);
2499 xgbe_config_tx_threshold(pdata, pdata->tx_threshold);
2500 xgbe_config_rx_threshold(pdata, pdata->rx_threshold);
2501 xgbe_config_tx_fifo_size(pdata);
2502 xgbe_config_rx_fifo_size(pdata);
2503 xgbe_config_flow_control_threshold(pdata);
2504
2505
2506
2507 xgbe_config_dcb_tc(pdata);
2508 xgbe_config_dcb_pfc(pdata);
2509 xgbe_enable_mtl_interrupts(pdata);
2510
2511
2512
2513
2514 xgbe_config_mac_address(pdata);
2515 xgbe_config_jumbo_enable(pdata);
2516 xgbe_config_flow_control(pdata);
2517 xgbe_config_checksum_offload(pdata);
2518 xgbe_config_vlan_support(pdata);
2519 xgbe_config_mmc(pdata);
2520 xgbe_enable_mac_interrupts(pdata);
2521
2522 DBGPR("<--xgbe_init\n");
2523
2524 return 0;
2525}
2526
2527void xgbe_init_function_ptrs_dev(struct xgbe_hw_if *hw_if)
2528{
2529 DBGPR("-->xgbe_init_function_ptrs\n");
2530
2531 hw_if->tx_complete = xgbe_tx_complete;
2532
2533 hw_if->set_promiscuous_mode = xgbe_set_promiscuous_mode;
2534 hw_if->set_all_multicast_mode = xgbe_set_all_multicast_mode;
2535 hw_if->add_mac_addresses = xgbe_add_mac_addresses;
2536 hw_if->set_mac_address = xgbe_set_mac_address;
2537
2538 hw_if->enable_rx_csum = xgbe_enable_rx_csum;
2539 hw_if->disable_rx_csum = xgbe_disable_rx_csum;
2540
2541 hw_if->enable_rx_vlan_stripping = xgbe_enable_rx_vlan_stripping;
2542 hw_if->disable_rx_vlan_stripping = xgbe_disable_rx_vlan_stripping;
2543 hw_if->enable_rx_vlan_filtering = xgbe_enable_rx_vlan_filtering;
2544 hw_if->disable_rx_vlan_filtering = xgbe_disable_rx_vlan_filtering;
2545 hw_if->update_vlan_hash_table = xgbe_update_vlan_hash_table;
2546
2547 hw_if->read_mmd_regs = xgbe_read_mmd_regs;
2548 hw_if->write_mmd_regs = xgbe_write_mmd_regs;
2549
2550 hw_if->set_gmii_speed = xgbe_set_gmii_speed;
2551 hw_if->set_gmii_2500_speed = xgbe_set_gmii_2500_speed;
2552 hw_if->set_xgmii_speed = xgbe_set_xgmii_speed;
2553
2554 hw_if->enable_tx = xgbe_enable_tx;
2555 hw_if->disable_tx = xgbe_disable_tx;
2556 hw_if->enable_rx = xgbe_enable_rx;
2557 hw_if->disable_rx = xgbe_disable_rx;
2558
2559 hw_if->powerup_tx = xgbe_powerup_tx;
2560 hw_if->powerdown_tx = xgbe_powerdown_tx;
2561 hw_if->powerup_rx = xgbe_powerup_rx;
2562 hw_if->powerdown_rx = xgbe_powerdown_rx;
2563
2564 hw_if->pre_xmit = xgbe_pre_xmit;
2565 hw_if->dev_read = xgbe_dev_read;
2566 hw_if->enable_int = xgbe_enable_int;
2567 hw_if->disable_int = xgbe_disable_int;
2568 hw_if->init = xgbe_init;
2569 hw_if->exit = xgbe_exit;
2570
2571
2572 hw_if->tx_desc_init = xgbe_tx_desc_init;
2573 hw_if->rx_desc_init = xgbe_rx_desc_init;
2574 hw_if->tx_desc_reset = xgbe_tx_desc_reset;
2575 hw_if->rx_desc_reset = xgbe_rx_desc_reset;
2576 hw_if->is_last_desc = xgbe_is_last_desc;
2577 hw_if->is_context_desc = xgbe_is_context_desc;
2578
2579
2580 hw_if->config_tx_flow_control = xgbe_config_tx_flow_control;
2581 hw_if->config_rx_flow_control = xgbe_config_rx_flow_control;
2582
2583
2584 hw_if->config_rx_coalesce = xgbe_config_rx_coalesce;
2585 hw_if->config_tx_coalesce = xgbe_config_tx_coalesce;
2586 hw_if->usec_to_riwt = xgbe_usec_to_riwt;
2587 hw_if->riwt_to_usec = xgbe_riwt_to_usec;
2588
2589
2590 hw_if->config_rx_threshold = xgbe_config_rx_threshold;
2591 hw_if->config_tx_threshold = xgbe_config_tx_threshold;
2592
2593
2594 hw_if->config_rsf_mode = xgbe_config_rsf_mode;
2595 hw_if->config_tsf_mode = xgbe_config_tsf_mode;
2596
2597
2598 hw_if->config_osp_mode = xgbe_config_osp_mode;
2599
2600
2601 hw_if->config_rx_pbl_val = xgbe_config_rx_pbl_val;
2602 hw_if->get_rx_pbl_val = xgbe_get_rx_pbl_val;
2603 hw_if->config_tx_pbl_val = xgbe_config_tx_pbl_val;
2604 hw_if->get_tx_pbl_val = xgbe_get_tx_pbl_val;
2605 hw_if->config_pblx8 = xgbe_config_pblx8;
2606
2607
2608 hw_if->tx_mmc_int = xgbe_tx_mmc_int;
2609 hw_if->rx_mmc_int = xgbe_rx_mmc_int;
2610 hw_if->read_mmc_stats = xgbe_read_mmc_stats;
2611
2612
2613 hw_if->config_tstamp = xgbe_config_tstamp;
2614 hw_if->update_tstamp_addend = xgbe_update_tstamp_addend;
2615 hw_if->set_tstamp_time = xgbe_set_tstamp_time;
2616 hw_if->get_tstamp_time = xgbe_get_tstamp_time;
2617 hw_if->get_tx_tstamp = xgbe_get_tx_tstamp;
2618
2619
2620 hw_if->config_dcb_tc = xgbe_config_dcb_tc;
2621 hw_if->config_dcb_pfc = xgbe_config_dcb_pfc;
2622
2623 DBGPR("<--xgbe_init_function_ptrs\n");
2624}
2625
