linux/drivers/net/ethernet/mellanox/mlx4/en_tx.c
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   1/*
   2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
   3 *
   4 * This software is available to you under a choice of one of two
   5 * licenses.  You may choose to be licensed under the terms of the GNU
   6 * General Public License (GPL) Version 2, available from the file
   7 * COPYING in the main directory of this source tree, or the
   8 * OpenIB.org BSD license below:
   9 *
  10 *     Redistribution and use in source and binary forms, with or
  11 *     without modification, are permitted provided that the following
  12 *     conditions are met:
  13 *
  14 *      - Redistributions of source code must retain the above
  15 *        copyright notice, this list of conditions and the following
  16 *        disclaimer.
  17 *
  18 *      - Redistributions in binary form must reproduce the above
  19 *        copyright notice, this list of conditions and the following
  20 *        disclaimer in the documentation and/or other materials
  21 *        provided with the distribution.
  22 *
  23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30 * SOFTWARE.
  31 *
  32 */
  33
  34#include <asm/page.h>
  35#include <linux/mlx4/cq.h>
  36#include <linux/slab.h>
  37#include <linux/mlx4/qp.h>
  38#include <linux/skbuff.h>
  39#include <linux/if_vlan.h>
  40#include <linux/prefetch.h>
  41#include <linux/vmalloc.h>
  42#include <linux/tcp.h>
  43#include <linux/ip.h>
  44#include <linux/moduleparam.h>
  45
  46#include "mlx4_en.h"
  47
  48int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv,
  49                           struct mlx4_en_tx_ring **pring, int qpn, u32 size,
  50                           u16 stride, int node, int queue_index)
  51{
  52        struct mlx4_en_dev *mdev = priv->mdev;
  53        struct mlx4_en_tx_ring *ring;
  54        int tmp;
  55        int err;
  56
  57        ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, node);
  58        if (!ring) {
  59                ring = kzalloc(sizeof(*ring), GFP_KERNEL);
  60                if (!ring) {
  61                        en_err(priv, "Failed allocating TX ring\n");
  62                        return -ENOMEM;
  63                }
  64        }
  65
  66        ring->size = size;
  67        ring->size_mask = size - 1;
  68        ring->stride = stride;
  69
  70        tmp = size * sizeof(struct mlx4_en_tx_info);
  71        ring->tx_info = kmalloc_node(tmp, GFP_KERNEL | __GFP_NOWARN, node);
  72        if (!ring->tx_info) {
  73                ring->tx_info = vmalloc(tmp);
  74                if (!ring->tx_info) {
  75                        err = -ENOMEM;
  76                        goto err_ring;
  77                }
  78        }
  79
  80        en_dbg(DRV, priv, "Allocated tx_info ring at addr:%p size:%d\n",
  81                 ring->tx_info, tmp);
  82
  83        ring->bounce_buf = kmalloc_node(MAX_DESC_SIZE, GFP_KERNEL, node);
  84        if (!ring->bounce_buf) {
  85                ring->bounce_buf = kmalloc(MAX_DESC_SIZE, GFP_KERNEL);
  86                if (!ring->bounce_buf) {
  87                        err = -ENOMEM;
  88                        goto err_info;
  89                }
  90        }
  91        ring->buf_size = ALIGN(size * ring->stride, MLX4_EN_PAGE_SIZE);
  92
  93        /* Allocate HW buffers on provided NUMA node */
  94        set_dev_node(&mdev->dev->pdev->dev, node);
  95        err = mlx4_alloc_hwq_res(mdev->dev, &ring->wqres, ring->buf_size,
  96                                 2 * PAGE_SIZE);
  97        set_dev_node(&mdev->dev->pdev->dev, mdev->dev->numa_node);
  98        if (err) {
  99                en_err(priv, "Failed allocating hwq resources\n");
 100                goto err_bounce;
 101        }
 102
 103        err = mlx4_en_map_buffer(&ring->wqres.buf);
 104        if (err) {
 105                en_err(priv, "Failed to map TX buffer\n");
 106                goto err_hwq_res;
 107        }
 108
 109        ring->buf = ring->wqres.buf.direct.buf;
 110
 111        en_dbg(DRV, priv, "Allocated TX ring (addr:%p) - buf:%p size:%d buf_size:%d dma:%llx\n",
 112               ring, ring->buf, ring->size, ring->buf_size,
 113               (unsigned long long) ring->wqres.buf.direct.map);
 114
 115        ring->qpn = qpn;
 116        err = mlx4_qp_alloc(mdev->dev, ring->qpn, &ring->qp, GFP_KERNEL);
 117        if (err) {
 118                en_err(priv, "Failed allocating qp %d\n", ring->qpn);
 119                goto err_map;
 120        }
 121        ring->qp.event = mlx4_en_sqp_event;
 122
 123        err = mlx4_bf_alloc(mdev->dev, &ring->bf, node);
 124        if (err) {
 125                en_dbg(DRV, priv, "working without blueflame (%d)\n", err);
 126                ring->bf.uar = &mdev->priv_uar;
 127                ring->bf.uar->map = mdev->uar_map;
 128                ring->bf_enabled = false;
 129                ring->bf_alloced = false;
 130                priv->pflags &= ~MLX4_EN_PRIV_FLAGS_BLUEFLAME;
 131        } else {
 132                ring->bf_alloced = true;
 133                ring->bf_enabled = !!(priv->pflags &
 134                                      MLX4_EN_PRIV_FLAGS_BLUEFLAME);
 135        }
 136
 137        ring->hwtstamp_tx_type = priv->hwtstamp_config.tx_type;
 138        ring->queue_index = queue_index;
 139
 140        if (queue_index < priv->num_tx_rings_p_up && cpu_online(queue_index))
 141                cpumask_set_cpu(queue_index, &ring->affinity_mask);
 142
 143        *pring = ring;
 144        return 0;
 145
 146err_map:
 147        mlx4_en_unmap_buffer(&ring->wqres.buf);
 148err_hwq_res:
 149        mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size);
 150err_bounce:
 151        kfree(ring->bounce_buf);
 152        ring->bounce_buf = NULL;
 153err_info:
 154        kvfree(ring->tx_info);
 155        ring->tx_info = NULL;
 156err_ring:
 157        kfree(ring);
 158        *pring = NULL;
 159        return err;
 160}
 161
 162void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv,
 163                             struct mlx4_en_tx_ring **pring)
 164{
 165        struct mlx4_en_dev *mdev = priv->mdev;
 166        struct mlx4_en_tx_ring *ring = *pring;
 167        en_dbg(DRV, priv, "Destroying tx ring, qpn: %d\n", ring->qpn);
 168
 169        if (ring->bf_alloced)
 170                mlx4_bf_free(mdev->dev, &ring->bf);
 171        mlx4_qp_remove(mdev->dev, &ring->qp);
 172        mlx4_qp_free(mdev->dev, &ring->qp);
 173        mlx4_en_unmap_buffer(&ring->wqres.buf);
 174        mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size);
 175        kfree(ring->bounce_buf);
 176        ring->bounce_buf = NULL;
 177        kvfree(ring->tx_info);
 178        ring->tx_info = NULL;
 179        kfree(ring);
 180        *pring = NULL;
 181}
 182
 183int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv,
 184                             struct mlx4_en_tx_ring *ring,
 185                             int cq, int user_prio)
 186{
 187        struct mlx4_en_dev *mdev = priv->mdev;
 188        int err;
 189
 190        ring->cqn = cq;
 191        ring->prod = 0;
 192        ring->cons = 0xffffffff;
 193        ring->last_nr_txbb = 1;
 194        memset(ring->tx_info, 0, ring->size * sizeof(struct mlx4_en_tx_info));
 195        memset(ring->buf, 0, ring->buf_size);
 196
 197        ring->qp_state = MLX4_QP_STATE_RST;
 198        ring->doorbell_qpn = cpu_to_be32(ring->qp.qpn << 8);
 199        ring->mr_key = cpu_to_be32(mdev->mr.key);
 200
 201        mlx4_en_fill_qp_context(priv, ring->size, ring->stride, 1, 0, ring->qpn,
 202                                ring->cqn, user_prio, &ring->context);
 203        if (ring->bf_alloced)
 204                ring->context.usr_page = cpu_to_be32(ring->bf.uar->index);
 205
 206        err = mlx4_qp_to_ready(mdev->dev, &ring->wqres.mtt, &ring->context,
 207                               &ring->qp, &ring->qp_state);
 208        if (!user_prio && cpu_online(ring->queue_index))
 209                netif_set_xps_queue(priv->dev, &ring->affinity_mask,
 210                                    ring->queue_index);
 211
 212        return err;
 213}
 214
 215void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv,
 216                                struct mlx4_en_tx_ring *ring)
 217{
 218        struct mlx4_en_dev *mdev = priv->mdev;
 219
 220        mlx4_qp_modify(mdev->dev, NULL, ring->qp_state,
 221                       MLX4_QP_STATE_RST, NULL, 0, 0, &ring->qp);
 222}
 223
 224static void mlx4_en_stamp_wqe(struct mlx4_en_priv *priv,
 225                              struct mlx4_en_tx_ring *ring, int index,
 226                              u8 owner)
 227{
 228        __be32 stamp = cpu_to_be32(STAMP_VAL | (!!owner << STAMP_SHIFT));
 229        struct mlx4_en_tx_desc *tx_desc = ring->buf + index * TXBB_SIZE;
 230        struct mlx4_en_tx_info *tx_info = &ring->tx_info[index];
 231        void *end = ring->buf + ring->buf_size;
 232        __be32 *ptr = (__be32 *)tx_desc;
 233        int i;
 234
 235        /* Optimize the common case when there are no wraparounds */
 236        if (likely((void *)tx_desc + tx_info->nr_txbb * TXBB_SIZE <= end)) {
 237                /* Stamp the freed descriptor */
 238                for (i = 0; i < tx_info->nr_txbb * TXBB_SIZE;
 239                     i += STAMP_STRIDE) {
 240                        *ptr = stamp;
 241                        ptr += STAMP_DWORDS;
 242                }
 243        } else {
 244                /* Stamp the freed descriptor */
 245                for (i = 0; i < tx_info->nr_txbb * TXBB_SIZE;
 246                     i += STAMP_STRIDE) {
 247                        *ptr = stamp;
 248                        ptr += STAMP_DWORDS;
 249                        if ((void *)ptr >= end) {
 250                                ptr = ring->buf;
 251                                stamp ^= cpu_to_be32(0x80000000);
 252                        }
 253                }
 254        }
 255}
 256
 257
 258static u32 mlx4_en_free_tx_desc(struct mlx4_en_priv *priv,
 259                                struct mlx4_en_tx_ring *ring,
 260                                int index, u8 owner, u64 timestamp)
 261{
 262        struct mlx4_en_tx_info *tx_info = &ring->tx_info[index];
 263        struct mlx4_en_tx_desc *tx_desc = ring->buf + index * TXBB_SIZE;
 264        struct mlx4_wqe_data_seg *data = (void *) tx_desc + tx_info->data_offset;
 265        void *end = ring->buf + ring->buf_size;
 266        struct sk_buff *skb = tx_info->skb;
 267        int nr_maps = tx_info->nr_maps;
 268        int i;
 269
 270        /* We do not touch skb here, so prefetch skb->users location
 271         * to speedup consume_skb()
 272         */
 273        prefetchw(&skb->users);
 274
 275        if (unlikely(timestamp)) {
 276                struct skb_shared_hwtstamps hwts;
 277
 278                mlx4_en_fill_hwtstamps(priv->mdev, &hwts, timestamp);
 279                skb_tstamp_tx(skb, &hwts);
 280        }
 281
 282        /* Optimize the common case when there are no wraparounds */
 283        if (likely((void *) tx_desc + tx_info->nr_txbb * TXBB_SIZE <= end)) {
 284                if (!tx_info->inl) {
 285                        if (tx_info->linear)
 286                                dma_unmap_single(priv->ddev,
 287                                                tx_info->map0_dma,
 288                                                tx_info->map0_byte_count,
 289                                                PCI_DMA_TODEVICE);
 290                        else
 291                                dma_unmap_page(priv->ddev,
 292                                               tx_info->map0_dma,
 293                                               tx_info->map0_byte_count,
 294                                               PCI_DMA_TODEVICE);
 295                        for (i = 1; i < nr_maps; i++) {
 296                                data++;
 297                                dma_unmap_page(priv->ddev,
 298                                        (dma_addr_t)be64_to_cpu(data->addr),
 299                                        be32_to_cpu(data->byte_count),
 300                                        PCI_DMA_TODEVICE);
 301                        }
 302                }
 303        } else {
 304                if (!tx_info->inl) {
 305                        if ((void *) data >= end) {
 306                                data = ring->buf + ((void *)data - end);
 307                        }
 308
 309                        if (tx_info->linear)
 310                                dma_unmap_single(priv->ddev,
 311                                                tx_info->map0_dma,
 312                                                tx_info->map0_byte_count,
 313                                                PCI_DMA_TODEVICE);
 314                        else
 315                                dma_unmap_page(priv->ddev,
 316                                               tx_info->map0_dma,
 317                                               tx_info->map0_byte_count,
 318                                               PCI_DMA_TODEVICE);
 319                        for (i = 1; i < nr_maps; i++) {
 320                                data++;
 321                                /* Check for wraparound before unmapping */
 322                                if ((void *) data >= end)
 323                                        data = ring->buf;
 324                                dma_unmap_page(priv->ddev,
 325                                        (dma_addr_t)be64_to_cpu(data->addr),
 326                                        be32_to_cpu(data->byte_count),
 327                                        PCI_DMA_TODEVICE);
 328                        }
 329                }
 330        }
 331        dev_consume_skb_any(skb);
 332        return tx_info->nr_txbb;
 333}
 334
 335
 336int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring)
 337{
 338        struct mlx4_en_priv *priv = netdev_priv(dev);
 339        int cnt = 0;
 340
 341        /* Skip last polled descriptor */
 342        ring->cons += ring->last_nr_txbb;
 343        en_dbg(DRV, priv, "Freeing Tx buf - cons:0x%x prod:0x%x\n",
 344                 ring->cons, ring->prod);
 345
 346        if ((u32) (ring->prod - ring->cons) > ring->size) {
 347                if (netif_msg_tx_err(priv))
 348                        en_warn(priv, "Tx consumer passed producer!\n");
 349                return 0;
 350        }
 351
 352        while (ring->cons != ring->prod) {
 353                ring->last_nr_txbb = mlx4_en_free_tx_desc(priv, ring,
 354                                                ring->cons & ring->size_mask,
 355                                                !!(ring->cons & ring->size), 0);
 356                ring->cons += ring->last_nr_txbb;
 357                cnt++;
 358        }
 359
 360        netdev_tx_reset_queue(ring->tx_queue);
 361
 362        if (cnt)
 363                en_dbg(DRV, priv, "Freed %d uncompleted tx descriptors\n", cnt);
 364
 365        return cnt;
 366}
 367
 368static bool mlx4_en_process_tx_cq(struct net_device *dev,
 369                                 struct mlx4_en_cq *cq)
 370{
 371        struct mlx4_en_priv *priv = netdev_priv(dev);
 372        struct mlx4_cq *mcq = &cq->mcq;
 373        struct mlx4_en_tx_ring *ring = priv->tx_ring[cq->ring];
 374        struct mlx4_cqe *cqe;
 375        u16 index;
 376        u16 new_index, ring_index, stamp_index;
 377        u32 txbbs_skipped = 0;
 378        u32 txbbs_stamp = 0;
 379        u32 cons_index = mcq->cons_index;
 380        int size = cq->size;
 381        u32 size_mask = ring->size_mask;
 382        struct mlx4_cqe *buf = cq->buf;
 383        u32 packets = 0;
 384        u32 bytes = 0;
 385        int factor = priv->cqe_factor;
 386        u64 timestamp = 0;
 387        int done = 0;
 388        int budget = priv->tx_work_limit;
 389        u32 last_nr_txbb;
 390        u32 ring_cons;
 391
 392        if (!priv->port_up)
 393                return true;
 394
 395        netdev_txq_bql_complete_prefetchw(ring->tx_queue);
 396
 397        index = cons_index & size_mask;
 398        cqe = mlx4_en_get_cqe(buf, index, priv->cqe_size) + factor;
 399        last_nr_txbb = ACCESS_ONCE(ring->last_nr_txbb);
 400        ring_cons = ACCESS_ONCE(ring->cons);
 401        ring_index = ring_cons & size_mask;
 402        stamp_index = ring_index;
 403
 404        /* Process all completed CQEs */
 405        while (XNOR(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK,
 406                        cons_index & size) && (done < budget)) {
 407                /*
 408                 * make sure we read the CQE after we read the
 409                 * ownership bit
 410                 */
 411                rmb();
 412
 413                if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) ==
 414                             MLX4_CQE_OPCODE_ERROR)) {
 415                        struct mlx4_err_cqe *cqe_err = (struct mlx4_err_cqe *)cqe;
 416
 417                        en_err(priv, "CQE error - vendor syndrome: 0x%x syndrome: 0x%x\n",
 418                               cqe_err->vendor_err_syndrome,
 419                               cqe_err->syndrome);
 420                }
 421
 422                /* Skip over last polled CQE */
 423                new_index = be16_to_cpu(cqe->wqe_index) & size_mask;
 424
 425                do {
 426                        txbbs_skipped += last_nr_txbb;
 427                        ring_index = (ring_index + last_nr_txbb) & size_mask;
 428                        if (ring->tx_info[ring_index].ts_requested)
 429                                timestamp = mlx4_en_get_cqe_ts(cqe);
 430
 431                        /* free next descriptor */
 432                        last_nr_txbb = mlx4_en_free_tx_desc(
 433                                        priv, ring, ring_index,
 434                                        !!((ring_cons + txbbs_skipped) &
 435                                        ring->size), timestamp);
 436
 437                        mlx4_en_stamp_wqe(priv, ring, stamp_index,
 438                                          !!((ring_cons + txbbs_stamp) &
 439                                                ring->size));
 440                        stamp_index = ring_index;
 441                        txbbs_stamp = txbbs_skipped;
 442                        packets++;
 443                        bytes += ring->tx_info[ring_index].nr_bytes;
 444                } while ((++done < budget) && (ring_index != new_index));
 445
 446                ++cons_index;
 447                index = cons_index & size_mask;
 448                cqe = mlx4_en_get_cqe(buf, index, priv->cqe_size) + factor;
 449        }
 450
 451
 452        /*
 453         * To prevent CQ overflow we first update CQ consumer and only then
 454         * the ring consumer.
 455         */
 456        mcq->cons_index = cons_index;
 457        mlx4_cq_set_ci(mcq);
 458        wmb();
 459
 460        /* we want to dirty this cache line once */
 461        ACCESS_ONCE(ring->last_nr_txbb) = last_nr_txbb;
 462        ACCESS_ONCE(ring->cons) = ring_cons + txbbs_skipped;
 463
 464        netdev_tx_completed_queue(ring->tx_queue, packets, bytes);
 465
 466        /*
 467         * Wakeup Tx queue if this stopped, and at least 1 packet
 468         * was completed
 469         */
 470        if (netif_tx_queue_stopped(ring->tx_queue) && txbbs_skipped > 0) {
 471                netif_tx_wake_queue(ring->tx_queue);
 472                ring->wake_queue++;
 473        }
 474        return done < budget;
 475}
 476
 477void mlx4_en_tx_irq(struct mlx4_cq *mcq)
 478{
 479        struct mlx4_en_cq *cq = container_of(mcq, struct mlx4_en_cq, mcq);
 480        struct mlx4_en_priv *priv = netdev_priv(cq->dev);
 481
 482        if (priv->port_up)
 483                napi_schedule(&cq->napi);
 484        else
 485                mlx4_en_arm_cq(priv, cq);
 486}
 487
 488/* TX CQ polling - called by NAPI */
 489int mlx4_en_poll_tx_cq(struct napi_struct *napi, int budget)
 490{
 491        struct mlx4_en_cq *cq = container_of(napi, struct mlx4_en_cq, napi);
 492        struct net_device *dev = cq->dev;
 493        struct mlx4_en_priv *priv = netdev_priv(dev);
 494        int clean_complete;
 495
 496        clean_complete = mlx4_en_process_tx_cq(dev, cq);
 497        if (!clean_complete)
 498                return budget;
 499
 500        napi_complete(napi);
 501        mlx4_en_arm_cq(priv, cq);
 502
 503        return 0;
 504}
 505
 506static struct mlx4_en_tx_desc *mlx4_en_bounce_to_desc(struct mlx4_en_priv *priv,
 507                                                      struct mlx4_en_tx_ring *ring,
 508                                                      u32 index,
 509                                                      unsigned int desc_size)
 510{
 511        u32 copy = (ring->size - index) * TXBB_SIZE;
 512        int i;
 513
 514        for (i = desc_size - copy - 4; i >= 0; i -= 4) {
 515                if ((i & (TXBB_SIZE - 1)) == 0)
 516                        wmb();
 517
 518                *((u32 *) (ring->buf + i)) =
 519                        *((u32 *) (ring->bounce_buf + copy + i));
 520        }
 521
 522        for (i = copy - 4; i >= 4 ; i -= 4) {
 523                if ((i & (TXBB_SIZE - 1)) == 0)
 524                        wmb();
 525
 526                *((u32 *) (ring->buf + index * TXBB_SIZE + i)) =
 527                        *((u32 *) (ring->bounce_buf + i));
 528        }
 529
 530        /* Return real descriptor location */
 531        return ring->buf + index * TXBB_SIZE;
 532}
 533
 534/* Decide if skb can be inlined in tx descriptor to avoid dma mapping
 535 *
 536 * It seems strange we do not simply use skb_copy_bits().
 537 * This would allow to inline all skbs iff skb->len <= inline_thold
 538 *
 539 * Note that caller already checked skb was not a gso packet
 540 */
 541static bool is_inline(int inline_thold, const struct sk_buff *skb,
 542                      const struct skb_shared_info *shinfo,
 543                      void **pfrag)
 544{
 545        void *ptr;
 546
 547        if (skb->len > inline_thold || !inline_thold)
 548                return false;
 549
 550        if (shinfo->nr_frags == 1) {
 551                ptr = skb_frag_address_safe(&shinfo->frags[0]);
 552                if (unlikely(!ptr))
 553                        return false;
 554                *pfrag = ptr;
 555                return true;
 556        }
 557        if (shinfo->nr_frags)
 558                return false;
 559        return true;
 560}
 561
 562static int inline_size(const struct sk_buff *skb)
 563{
 564        if (skb->len + CTRL_SIZE + sizeof(struct mlx4_wqe_inline_seg)
 565            <= MLX4_INLINE_ALIGN)
 566                return ALIGN(skb->len + CTRL_SIZE +
 567                             sizeof(struct mlx4_wqe_inline_seg), 16);
 568        else
 569                return ALIGN(skb->len + CTRL_SIZE + 2 *
 570                             sizeof(struct mlx4_wqe_inline_seg), 16);
 571}
 572
 573static int get_real_size(const struct sk_buff *skb,
 574                         const struct skb_shared_info *shinfo,
 575                         struct net_device *dev,
 576                         int *lso_header_size,
 577                         bool *inline_ok,
 578                         void **pfrag)
 579{
 580        struct mlx4_en_priv *priv = netdev_priv(dev);
 581        int real_size;
 582
 583        if (shinfo->gso_size) {
 584                *inline_ok = false;
 585                if (skb->encapsulation)
 586                        *lso_header_size = (skb_inner_transport_header(skb) - skb->data) + inner_tcp_hdrlen(skb);
 587                else
 588                        *lso_header_size = skb_transport_offset(skb) + tcp_hdrlen(skb);
 589                real_size = CTRL_SIZE + shinfo->nr_frags * DS_SIZE +
 590                        ALIGN(*lso_header_size + 4, DS_SIZE);
 591                if (unlikely(*lso_header_size != skb_headlen(skb))) {
 592                        /* We add a segment for the skb linear buffer only if
 593                         * it contains data */
 594                        if (*lso_header_size < skb_headlen(skb))
 595                                real_size += DS_SIZE;
 596                        else {
 597                                if (netif_msg_tx_err(priv))
 598                                        en_warn(priv, "Non-linear headers\n");
 599                                return 0;
 600                        }
 601                }
 602        } else {
 603                *lso_header_size = 0;
 604                *inline_ok = is_inline(priv->prof->inline_thold, skb,
 605                                       shinfo, pfrag);
 606
 607                if (*inline_ok)
 608                        real_size = inline_size(skb);
 609                else
 610                        real_size = CTRL_SIZE +
 611                                    (shinfo->nr_frags + 1) * DS_SIZE;
 612        }
 613
 614        return real_size;
 615}
 616
 617static void build_inline_wqe(struct mlx4_en_tx_desc *tx_desc,
 618                             const struct sk_buff *skb,
 619                             const struct skb_shared_info *shinfo,
 620                             int real_size, u16 *vlan_tag,
 621                             int tx_ind, void *fragptr)
 622{
 623        struct mlx4_wqe_inline_seg *inl = &tx_desc->inl;
 624        int spc = MLX4_INLINE_ALIGN - CTRL_SIZE - sizeof *inl;
 625        unsigned int hlen = skb_headlen(skb);
 626
 627        if (skb->len <= spc) {
 628                if (likely(skb->len >= MIN_PKT_LEN)) {
 629                        inl->byte_count = cpu_to_be32(1 << 31 | skb->len);
 630                } else {
 631                        inl->byte_count = cpu_to_be32(1 << 31 | MIN_PKT_LEN);
 632                        memset(((void *)(inl + 1)) + skb->len, 0,
 633                               MIN_PKT_LEN - skb->len);
 634                }
 635                skb_copy_from_linear_data(skb, inl + 1, hlen);
 636                if (shinfo->nr_frags)
 637                        memcpy(((void *)(inl + 1)) + hlen, fragptr,
 638                               skb_frag_size(&shinfo->frags[0]));
 639
 640        } else {
 641                inl->byte_count = cpu_to_be32(1 << 31 | spc);
 642                if (hlen <= spc) {
 643                        skb_copy_from_linear_data(skb, inl + 1, hlen);
 644                        if (hlen < spc) {
 645                                memcpy(((void *)(inl + 1)) + hlen,
 646                                       fragptr, spc - hlen);
 647                                fragptr +=  spc - hlen;
 648                        }
 649                        inl = (void *) (inl + 1) + spc;
 650                        memcpy(((void *)(inl + 1)), fragptr, skb->len - spc);
 651                } else {
 652                        skb_copy_from_linear_data(skb, inl + 1, spc);
 653                        inl = (void *) (inl + 1) + spc;
 654                        skb_copy_from_linear_data_offset(skb, spc, inl + 1,
 655                                                         hlen - spc);
 656                        if (shinfo->nr_frags)
 657                                memcpy(((void *)(inl + 1)) + hlen - spc,
 658                                       fragptr,
 659                                       skb_frag_size(&shinfo->frags[0]));
 660                }
 661
 662                wmb();
 663                inl->byte_count = cpu_to_be32(1 << 31 | (skb->len - spc));
 664        }
 665}
 666
 667u16 mlx4_en_select_queue(struct net_device *dev, struct sk_buff *skb,
 668                         void *accel_priv, select_queue_fallback_t fallback)
 669{
 670        struct mlx4_en_priv *priv = netdev_priv(dev);
 671        u16 rings_p_up = priv->num_tx_rings_p_up;
 672        u8 up = 0;
 673
 674        if (dev->num_tc)
 675                return skb_tx_hash(dev, skb);
 676
 677        if (vlan_tx_tag_present(skb))
 678                up = vlan_tx_tag_get(skb) >> VLAN_PRIO_SHIFT;
 679
 680        return fallback(dev, skb) % rings_p_up + up * rings_p_up;
 681}
 682
 683static void mlx4_bf_copy(void __iomem *dst, const void *src,
 684                         unsigned int bytecnt)
 685{
 686        __iowrite64_copy(dst, src, bytecnt / 8);
 687}
 688
 689netdev_tx_t mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev)
 690{
 691        struct skb_shared_info *shinfo = skb_shinfo(skb);
 692        struct mlx4_en_priv *priv = netdev_priv(dev);
 693        struct device *ddev = priv->ddev;
 694        struct mlx4_en_tx_ring *ring;
 695        struct mlx4_en_tx_desc *tx_desc;
 696        struct mlx4_wqe_data_seg *data;
 697        struct mlx4_en_tx_info *tx_info;
 698        int tx_ind = 0;
 699        int nr_txbb;
 700        int desc_size;
 701        int real_size;
 702        u32 index, bf_index;
 703        __be32 op_own;
 704        u16 vlan_tag = 0;
 705        int i_frag;
 706        int lso_header_size;
 707        void *fragptr = NULL;
 708        bool bounce = false;
 709        bool send_doorbell;
 710        bool stop_queue;
 711        bool inline_ok;
 712        u32 ring_cons;
 713
 714        if (!priv->port_up)
 715                goto tx_drop;
 716
 717        tx_ind = skb_get_queue_mapping(skb);
 718        ring = priv->tx_ring[tx_ind];
 719
 720        /* fetch ring->cons far ahead before needing it to avoid stall */
 721        ring_cons = ACCESS_ONCE(ring->cons);
 722
 723        real_size = get_real_size(skb, shinfo, dev, &lso_header_size,
 724                                  &inline_ok, &fragptr);
 725        if (unlikely(!real_size))
 726                goto tx_drop;
 727
 728        /* Align descriptor to TXBB size */
 729        desc_size = ALIGN(real_size, TXBB_SIZE);
 730        nr_txbb = desc_size / TXBB_SIZE;
 731        if (unlikely(nr_txbb > MAX_DESC_TXBBS)) {
 732                if (netif_msg_tx_err(priv))
 733                        en_warn(priv, "Oversized header or SG list\n");
 734                goto tx_drop;
 735        }
 736
 737        if (vlan_tx_tag_present(skb))
 738                vlan_tag = vlan_tx_tag_get(skb);
 739
 740
 741        netdev_txq_bql_enqueue_prefetchw(ring->tx_queue);
 742
 743        /* Track current inflight packets for performance analysis */
 744        AVG_PERF_COUNTER(priv->pstats.inflight_avg,
 745                         (u32)(ring->prod - ring_cons - 1));
 746
 747        /* Packet is good - grab an index and transmit it */
 748        index = ring->prod & ring->size_mask;
 749        bf_index = ring->prod;
 750
 751        /* See if we have enough space for whole descriptor TXBB for setting
 752         * SW ownership on next descriptor; if not, use a bounce buffer. */
 753        if (likely(index + nr_txbb <= ring->size))
 754                tx_desc = ring->buf + index * TXBB_SIZE;
 755        else {
 756                tx_desc = (struct mlx4_en_tx_desc *) ring->bounce_buf;
 757                bounce = true;
 758        }
 759
 760        /* Save skb in tx_info ring */
 761        tx_info = &ring->tx_info[index];
 762        tx_info->skb = skb;
 763        tx_info->nr_txbb = nr_txbb;
 764
 765        data = &tx_desc->data;
 766        if (lso_header_size)
 767                data = ((void *)&tx_desc->lso + ALIGN(lso_header_size + 4,
 768                                                      DS_SIZE));
 769
 770        /* valid only for none inline segments */
 771        tx_info->data_offset = (void *)data - (void *)tx_desc;
 772
 773        tx_info->inl = inline_ok;
 774
 775        tx_info->linear = (lso_header_size < skb_headlen(skb) &&
 776                           !inline_ok) ? 1 : 0;
 777
 778        tx_info->nr_maps = shinfo->nr_frags + tx_info->linear;
 779        data += tx_info->nr_maps - 1;
 780
 781        if (!tx_info->inl) {
 782                dma_addr_t dma = 0;
 783                u32 byte_count = 0;
 784
 785                /* Map fragments if any */
 786                for (i_frag = shinfo->nr_frags - 1; i_frag >= 0; i_frag--) {
 787                        const struct skb_frag_struct *frag;
 788
 789                        frag = &shinfo->frags[i_frag];
 790                        byte_count = skb_frag_size(frag);
 791                        dma = skb_frag_dma_map(ddev, frag,
 792                                               0, byte_count,
 793                                               DMA_TO_DEVICE);
 794                        if (dma_mapping_error(ddev, dma))
 795                                goto tx_drop_unmap;
 796
 797                        data->addr = cpu_to_be64(dma);
 798                        data->lkey = ring->mr_key;
 799                        wmb();
 800                        data->byte_count = cpu_to_be32(byte_count);
 801                        --data;
 802                }
 803
 804                /* Map linear part if needed */
 805                if (tx_info->linear) {
 806                        byte_count = skb_headlen(skb) - lso_header_size;
 807
 808                        dma = dma_map_single(ddev, skb->data +
 809                                             lso_header_size, byte_count,
 810                                             PCI_DMA_TODEVICE);
 811                        if (dma_mapping_error(ddev, dma))
 812                                goto tx_drop_unmap;
 813
 814                        data->addr = cpu_to_be64(dma);
 815                        data->lkey = ring->mr_key;
 816                        wmb();
 817                        data->byte_count = cpu_to_be32(byte_count);
 818                }
 819                /* tx completion can avoid cache line miss for common cases */
 820                tx_info->map0_dma = dma;
 821                tx_info->map0_byte_count = byte_count;
 822        }
 823
 824        /*
 825         * For timestamping add flag to skb_shinfo and
 826         * set flag for further reference
 827         */
 828        tx_info->ts_requested = 0;
 829        if (unlikely(ring->hwtstamp_tx_type == HWTSTAMP_TX_ON &&
 830                     shinfo->tx_flags & SKBTX_HW_TSTAMP)) {
 831                shinfo->tx_flags |= SKBTX_IN_PROGRESS;
 832                tx_info->ts_requested = 1;
 833        }
 834
 835        /* Prepare ctrl segement apart opcode+ownership, which depends on
 836         * whether LSO is used */
 837        tx_desc->ctrl.srcrb_flags = priv->ctrl_flags;
 838        if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
 839                if (!skb->encapsulation)
 840                        tx_desc->ctrl.srcrb_flags |= cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM |
 841                                                                 MLX4_WQE_CTRL_TCP_UDP_CSUM);
 842                else
 843                        tx_desc->ctrl.srcrb_flags |= cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM);
 844                ring->tx_csum++;
 845        }
 846
 847        if (priv->flags & MLX4_EN_FLAG_ENABLE_HW_LOOPBACK) {
 848                struct ethhdr *ethh;
 849
 850                /* Copy dst mac address to wqe. This allows loopback in eSwitch,
 851                 * so that VFs and PF can communicate with each other
 852                 */
 853                ethh = (struct ethhdr *)skb->data;
 854                tx_desc->ctrl.srcrb_flags16[0] = get_unaligned((__be16 *)ethh->h_dest);
 855                tx_desc->ctrl.imm = get_unaligned((__be32 *)(ethh->h_dest + 2));
 856        }
 857
 858        /* Handle LSO (TSO) packets */
 859        if (lso_header_size) {
 860                int i;
 861
 862                /* Mark opcode as LSO */
 863                op_own = cpu_to_be32(MLX4_OPCODE_LSO | (1 << 6)) |
 864                        ((ring->prod & ring->size) ?
 865                                cpu_to_be32(MLX4_EN_BIT_DESC_OWN) : 0);
 866
 867                /* Fill in the LSO prefix */
 868                tx_desc->lso.mss_hdr_size = cpu_to_be32(
 869                        shinfo->gso_size << 16 | lso_header_size);
 870
 871                /* Copy headers;
 872                 * note that we already verified that it is linear */
 873                memcpy(tx_desc->lso.header, skb->data, lso_header_size);
 874
 875                ring->tso_packets++;
 876
 877                i = ((skb->len - lso_header_size) / shinfo->gso_size) +
 878                        !!((skb->len - lso_header_size) % shinfo->gso_size);
 879                tx_info->nr_bytes = skb->len + (i - 1) * lso_header_size;
 880                ring->packets += i;
 881        } else {
 882                /* Normal (Non LSO) packet */
 883                op_own = cpu_to_be32(MLX4_OPCODE_SEND) |
 884                        ((ring->prod & ring->size) ?
 885                         cpu_to_be32(MLX4_EN_BIT_DESC_OWN) : 0);
 886                tx_info->nr_bytes = max_t(unsigned int, skb->len, ETH_ZLEN);
 887                ring->packets++;
 888        }
 889        ring->bytes += tx_info->nr_bytes;
 890        netdev_tx_sent_queue(ring->tx_queue, tx_info->nr_bytes);
 891        AVG_PERF_COUNTER(priv->pstats.tx_pktsz_avg, skb->len);
 892
 893        if (tx_info->inl)
 894                build_inline_wqe(tx_desc, skb, shinfo, real_size, &vlan_tag,
 895                                 tx_ind, fragptr);
 896
 897        if (skb->encapsulation) {
 898                struct iphdr *ipv4 = (struct iphdr *)skb_inner_network_header(skb);
 899                if (ipv4->protocol == IPPROTO_TCP || ipv4->protocol == IPPROTO_UDP)
 900                        op_own |= cpu_to_be32(MLX4_WQE_CTRL_IIP | MLX4_WQE_CTRL_ILP);
 901                else
 902                        op_own |= cpu_to_be32(MLX4_WQE_CTRL_IIP);
 903        }
 904
 905        ring->prod += nr_txbb;
 906
 907        /* If we used a bounce buffer then copy descriptor back into place */
 908        if (unlikely(bounce))
 909                tx_desc = mlx4_en_bounce_to_desc(priv, ring, index, desc_size);
 910
 911        skb_tx_timestamp(skb);
 912
 913        /* Check available TXBBs And 2K spare for prefetch */
 914        stop_queue = (int)(ring->prod - ring_cons) >
 915                      ring->size - HEADROOM - MAX_DESC_TXBBS;
 916        if (unlikely(stop_queue)) {
 917                netif_tx_stop_queue(ring->tx_queue);
 918                ring->queue_stopped++;
 919        }
 920        send_doorbell = !skb->xmit_more || netif_xmit_stopped(ring->tx_queue);
 921
 922        real_size = (real_size / 16) & 0x3f;
 923
 924        if (ring->bf_enabled && desc_size <= MAX_BF && !bounce &&
 925            !vlan_tx_tag_present(skb) && send_doorbell) {
 926                tx_desc->ctrl.bf_qpn = ring->doorbell_qpn |
 927                                       cpu_to_be32(real_size);
 928
 929                op_own |= htonl((bf_index & 0xffff) << 8);
 930                /* Ensure new descriptor hits memory
 931                 * before setting ownership of this descriptor to HW
 932                 */
 933                wmb();
 934                tx_desc->ctrl.owner_opcode = op_own;
 935
 936                wmb();
 937
 938                mlx4_bf_copy(ring->bf.reg + ring->bf.offset, &tx_desc->ctrl,
 939                             desc_size);
 940
 941                wmb();
 942
 943                ring->bf.offset ^= ring->bf.buf_size;
 944        } else {
 945                tx_desc->ctrl.vlan_tag = cpu_to_be16(vlan_tag);
 946                tx_desc->ctrl.ins_vlan = MLX4_WQE_CTRL_INS_VLAN *
 947                        !!vlan_tx_tag_present(skb);
 948                tx_desc->ctrl.fence_size = real_size;
 949
 950                /* Ensure new descriptor hits memory
 951                 * before setting ownership of this descriptor to HW
 952                 */
 953                wmb();
 954                tx_desc->ctrl.owner_opcode = op_own;
 955                if (send_doorbell) {
 956                        wmb();
 957                        iowrite32(ring->doorbell_qpn,
 958                                  ring->bf.uar->map + MLX4_SEND_DOORBELL);
 959                } else {
 960                        ring->xmit_more++;
 961                }
 962        }
 963
 964        if (unlikely(stop_queue)) {
 965                /* If queue was emptied after the if (stop_queue) , and before
 966                 * the netif_tx_stop_queue() - need to wake the queue,
 967                 * or else it will remain stopped forever.
 968                 * Need a memory barrier to make sure ring->cons was not
 969                 * updated before queue was stopped.
 970                 */
 971                smp_rmb();
 972
 973                ring_cons = ACCESS_ONCE(ring->cons);
 974                if (unlikely(((int)(ring->prod - ring_cons)) <=
 975                             ring->size - HEADROOM - MAX_DESC_TXBBS)) {
 976                        netif_tx_wake_queue(ring->tx_queue);
 977                        ring->wake_queue++;
 978                }
 979        }
 980        return NETDEV_TX_OK;
 981
 982tx_drop_unmap:
 983        en_err(priv, "DMA mapping error\n");
 984
 985        while (++i_frag < shinfo->nr_frags) {
 986                ++data;
 987                dma_unmap_page(ddev, (dma_addr_t) be64_to_cpu(data->addr),
 988                               be32_to_cpu(data->byte_count),
 989                               PCI_DMA_TODEVICE);
 990        }
 991
 992tx_drop:
 993        dev_kfree_skb_any(skb);
 994        priv->stats.tx_dropped++;
 995        return NETDEV_TX_OK;
 996}
 997
 998