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30#include "wifi.h"
31#include "core.h"
32#include "pci.h"
33#include "base.h"
34#include "ps.h"
35#include "efuse.h"
36#include <linux/interrupt.h>
37#include <linux/export.h>
38#include <linux/kmemleak.h>
39#include <linux/module.h>
40
41MODULE_AUTHOR("lizhaoming <chaoming_li@realsil.com.cn>");
42MODULE_AUTHOR("Realtek WlanFAE <wlanfae@realtek.com>");
43MODULE_AUTHOR("Larry Finger <Larry.FInger@lwfinger.net>");
44MODULE_LICENSE("GPL");
45MODULE_DESCRIPTION("PCI basic driver for rtlwifi");
46
47static const u16 pcibridge_vendors[PCI_BRIDGE_VENDOR_MAX] = {
48 INTEL_VENDOR_ID,
49 ATI_VENDOR_ID,
50 AMD_VENDOR_ID,
51 SIS_VENDOR_ID
52};
53
54static const u8 ac_to_hwq[] = {
55 VO_QUEUE,
56 VI_QUEUE,
57 BE_QUEUE,
58 BK_QUEUE
59};
60
61static u8 _rtl_mac_to_hwqueue(struct ieee80211_hw *hw,
62 struct sk_buff *skb)
63{
64 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
65 __le16 fc = rtl_get_fc(skb);
66 u8 queue_index = skb_get_queue_mapping(skb);
67
68 if (unlikely(ieee80211_is_beacon(fc)))
69 return BEACON_QUEUE;
70 if (ieee80211_is_mgmt(fc) || ieee80211_is_ctl(fc))
71 return MGNT_QUEUE;
72 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE)
73 if (ieee80211_is_nullfunc(fc))
74 return HIGH_QUEUE;
75
76 return ac_to_hwq[queue_index];
77}
78
79
80static void _rtl_pci_update_default_setting(struct ieee80211_hw *hw)
81{
82 struct rtl_priv *rtlpriv = rtl_priv(hw);
83 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
84 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
85 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
86 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
87 u8 init_aspm;
88
89 ppsc->reg_rfps_level = 0;
90 ppsc->support_aspm = false;
91
92
93 ppsc->const_amdpci_aspm = rtlpci->const_amdpci_aspm;
94 switch (rtlpci->const_pci_aspm) {
95 case 0:
96
97 break;
98
99 case 1:
100
101 ppsc->reg_rfps_level |= RT_RF_LPS_LEVEL_ASPM;
102 break;
103
104 case 2:
105
106 ppsc->reg_rfps_level |= (RT_RF_LPS_LEVEL_ASPM |
107 RT_RF_OFF_LEVL_CLK_REQ);
108 break;
109
110 case 3:
111
112
113
114
115 ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM);
116 ppsc->reg_rfps_level |= (RT_RF_PS_LEVEL_ALWAYS_ASPM |
117 RT_RF_OFF_LEVL_CLK_REQ);
118 break;
119
120 case 4:
121
122
123
124
125 ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM |
126 RT_RF_OFF_LEVL_CLK_REQ);
127 ppsc->reg_rfps_level |= RT_RF_PS_LEVEL_ALWAYS_ASPM;
128 break;
129 }
130
131 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC;
132
133
134 switch (rtlpci->const_hwsw_rfoff_d3) {
135 case 1:
136 if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM)
137 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM;
138 break;
139
140 case 2:
141 if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM)
142 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM;
143 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC;
144 break;
145
146 case 3:
147 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_PCI_D3;
148 break;
149 }
150
151
152 switch (rtlpci->const_support_pciaspm) {
153 case 0:{
154
155 bool support_aspm = false;
156 ppsc->support_aspm = support_aspm;
157 break;
158 }
159 case 1:{
160
161 bool support_aspm = true;
162 bool support_backdoor = true;
163 ppsc->support_aspm = support_aspm;
164
165
166
167
168
169 ppsc->support_backdoor = support_backdoor;
170
171 break;
172 }
173 case 2:
174
175 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL) {
176 bool support_aspm = true;
177 ppsc->support_aspm = support_aspm;
178 }
179 break;
180 default:
181 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
182 "switch case not processed\n");
183 break;
184 }
185
186
187
188 pci_read_config_byte(rtlpci->pdev, 0x80, &init_aspm);
189 if (rtlpriv->rtlhal.hw_type == HARDWARE_TYPE_RTL8192SE &&
190 init_aspm == 0x43)
191 ppsc->support_aspm = false;
192}
193
194static bool _rtl_pci_platform_switch_device_pci_aspm(
195 struct ieee80211_hw *hw,
196 u8 value)
197{
198 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
199 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
200
201 if (rtlhal->hw_type != HARDWARE_TYPE_RTL8192SE)
202 value |= 0x40;
203
204 pci_write_config_byte(rtlpci->pdev, 0x80, value);
205
206 return false;
207}
208
209
210static void _rtl_pci_switch_clk_req(struct ieee80211_hw *hw, u8 value)
211{
212 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
213 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
214
215 pci_write_config_byte(rtlpci->pdev, 0x81, value);
216
217 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE)
218 udelay(100);
219}
220
221
222static void rtl_pci_disable_aspm(struct ieee80211_hw *hw)
223{
224 struct rtl_priv *rtlpriv = rtl_priv(hw);
225 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
226 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
227 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
228 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
229 u8 num4bytes = pcipriv->ndis_adapter.num4bytes;
230
231 u8 linkctrl_reg = pcipriv->ndis_adapter.linkctrl_reg;
232 u16 pcibridge_linkctrlreg = pcipriv->ndis_adapter.
233 pcibridge_linkctrlreg;
234 u16 aspmlevel = 0;
235 u8 tmp_u1b = 0;
236
237 if (!ppsc->support_aspm)
238 return;
239
240 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) {
241 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
242 "PCI(Bridge) UNKNOWN\n");
243
244 return;
245 }
246
247 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) {
248 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ);
249 _rtl_pci_switch_clk_req(hw, 0x0);
250 }
251
252
253 pci_read_config_byte(rtlpci->pdev, 0x80, &tmp_u1b);
254
255
256 aspmlevel |= BIT(0) | BIT(1);
257 linkctrl_reg &= ~aspmlevel;
258 pcibridge_linkctrlreg &= ~(BIT(0) | BIT(1));
259
260 _rtl_pci_platform_switch_device_pci_aspm(hw, linkctrl_reg);
261 udelay(50);
262
263
264 pci_write_config_byte(rtlpci->pdev, (num4bytes << 2),
265 pcibridge_linkctrlreg);
266
267 udelay(50);
268}
269
270
271
272
273
274
275
276static void rtl_pci_enable_aspm(struct ieee80211_hw *hw)
277{
278 struct rtl_priv *rtlpriv = rtl_priv(hw);
279 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
280 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
281 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
282 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
283 u8 num4bytes = pcipriv->ndis_adapter.num4bytes;
284 u16 aspmlevel;
285 u8 u_pcibridge_aspmsetting;
286 u8 u_device_aspmsetting;
287
288 if (!ppsc->support_aspm)
289 return;
290
291 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) {
292 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
293 "PCI(Bridge) UNKNOWN\n");
294 return;
295 }
296
297
298
299 u_pcibridge_aspmsetting =
300 pcipriv->ndis_adapter.pcibridge_linkctrlreg |
301 rtlpci->const_hostpci_aspm_setting;
302
303 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL)
304 u_pcibridge_aspmsetting &= ~BIT(0);
305
306 pci_write_config_byte(rtlpci->pdev, (num4bytes << 2),
307 u_pcibridge_aspmsetting);
308
309 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
310 "PlatformEnableASPM(): Write reg[%x] = %x\n",
311 (pcipriv->ndis_adapter.pcibridge_pciehdr_offset + 0x10),
312 u_pcibridge_aspmsetting);
313
314 udelay(50);
315
316
317 aspmlevel = rtlpci->const_devicepci_aspm_setting;
318 u_device_aspmsetting = pcipriv->ndis_adapter.linkctrl_reg;
319
320
321
322
323 u_device_aspmsetting |= aspmlevel;
324
325 _rtl_pci_platform_switch_device_pci_aspm(hw, u_device_aspmsetting);
326
327 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) {
328 _rtl_pci_switch_clk_req(hw, (ppsc->reg_rfps_level &
329 RT_RF_OFF_LEVL_CLK_REQ) ? 1 : 0);
330 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ);
331 }
332 udelay(100);
333}
334
335static bool rtl_pci_get_amd_l1_patch(struct ieee80211_hw *hw)
336{
337 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
338
339 bool status = false;
340 u8 offset_e0;
341 unsigned offset_e4;
342
343 pci_write_config_byte(rtlpci->pdev, 0xe0, 0xa0);
344
345 pci_read_config_byte(rtlpci->pdev, 0xe0, &offset_e0);
346
347 if (offset_e0 == 0xA0) {
348 pci_read_config_dword(rtlpci->pdev, 0xe4, &offset_e4);
349 if (offset_e4 & BIT(23))
350 status = true;
351 }
352
353 return status;
354}
355
356static bool rtl_pci_check_buddy_priv(struct ieee80211_hw *hw,
357 struct rtl_priv **buddy_priv)
358{
359 struct rtl_priv *rtlpriv = rtl_priv(hw);
360 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
361 bool find_buddy_priv = false;
362 struct rtl_priv *tpriv = NULL;
363 struct rtl_pci_priv *tpcipriv = NULL;
364
365 if (!list_empty(&rtlpriv->glb_var->glb_priv_list)) {
366 list_for_each_entry(tpriv, &rtlpriv->glb_var->glb_priv_list,
367 list) {
368 if (tpriv) {
369 tpcipriv = (struct rtl_pci_priv *)tpriv->priv;
370 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
371 "pcipriv->ndis_adapter.funcnumber %x\n",
372 pcipriv->ndis_adapter.funcnumber);
373 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
374 "tpcipriv->ndis_adapter.funcnumber %x\n",
375 tpcipriv->ndis_adapter.funcnumber);
376
377 if ((pcipriv->ndis_adapter.busnumber ==
378 tpcipriv->ndis_adapter.busnumber) &&
379 (pcipriv->ndis_adapter.devnumber ==
380 tpcipriv->ndis_adapter.devnumber) &&
381 (pcipriv->ndis_adapter.funcnumber !=
382 tpcipriv->ndis_adapter.funcnumber)) {
383 find_buddy_priv = true;
384 break;
385 }
386 }
387 }
388 }
389
390 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
391 "find_buddy_priv %d\n", find_buddy_priv);
392
393 if (find_buddy_priv)
394 *buddy_priv = tpriv;
395
396 return find_buddy_priv;
397}
398
399static void rtl_pci_get_linkcontrol_field(struct ieee80211_hw *hw)
400{
401 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
402 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
403 u8 capabilityoffset = pcipriv->ndis_adapter.pcibridge_pciehdr_offset;
404 u8 linkctrl_reg;
405 u8 num4bbytes;
406
407 num4bbytes = (capabilityoffset + 0x10) / 4;
408
409
410 pci_read_config_byte(rtlpci->pdev, (num4bbytes << 2), &linkctrl_reg);
411
412 pcipriv->ndis_adapter.pcibridge_linkctrlreg = linkctrl_reg;
413}
414
415static void rtl_pci_parse_configuration(struct pci_dev *pdev,
416 struct ieee80211_hw *hw)
417{
418 struct rtl_priv *rtlpriv = rtl_priv(hw);
419 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
420
421 u8 tmp;
422 u16 linkctrl_reg;
423
424
425 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &linkctrl_reg);
426 pcipriv->ndis_adapter.linkctrl_reg = (u8)linkctrl_reg;
427
428 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Link Control Register =%x\n",
429 pcipriv->ndis_adapter.linkctrl_reg);
430
431 pci_read_config_byte(pdev, 0x98, &tmp);
432 tmp |= BIT(4);
433 pci_write_config_byte(pdev, 0x98, tmp);
434
435 tmp = 0x17;
436 pci_write_config_byte(pdev, 0x70f, tmp);
437}
438
439static void rtl_pci_init_aspm(struct ieee80211_hw *hw)
440{
441 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
442
443 _rtl_pci_update_default_setting(hw);
444
445 if (ppsc->reg_rfps_level & RT_RF_PS_LEVEL_ALWAYS_ASPM) {
446
447 rtl_pci_enable_aspm(hw);
448 RT_SET_PS_LEVEL(ppsc, RT_RF_PS_LEVEL_ALWAYS_ASPM);
449 }
450
451}
452
453static void _rtl_pci_io_handler_init(struct device *dev,
454 struct ieee80211_hw *hw)
455{
456 struct rtl_priv *rtlpriv = rtl_priv(hw);
457
458 rtlpriv->io.dev = dev;
459
460 rtlpriv->io.write8_async = pci_write8_async;
461 rtlpriv->io.write16_async = pci_write16_async;
462 rtlpriv->io.write32_async = pci_write32_async;
463
464 rtlpriv->io.read8_sync = pci_read8_sync;
465 rtlpriv->io.read16_sync = pci_read16_sync;
466 rtlpriv->io.read32_sync = pci_read32_sync;
467
468}
469
470static bool _rtl_update_earlymode_info(struct ieee80211_hw *hw,
471 struct sk_buff *skb, struct rtl_tcb_desc *tcb_desc, u8 tid)
472{
473 struct rtl_priv *rtlpriv = rtl_priv(hw);
474 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
475 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
476 struct sk_buff *next_skb;
477 u8 additionlen = FCS_LEN;
478
479
480 if (info->control.hw_key)
481 additionlen += info->control.hw_key->icv_len;
482
483
484 tcb_desc->empkt_num = 0;
485 spin_lock_bh(&rtlpriv->locks.waitq_lock);
486 skb_queue_walk(&rtlpriv->mac80211.skb_waitq[tid], next_skb) {
487 struct ieee80211_tx_info *next_info;
488
489 next_info = IEEE80211_SKB_CB(next_skb);
490 if (next_info->flags & IEEE80211_TX_CTL_AMPDU) {
491 tcb_desc->empkt_len[tcb_desc->empkt_num] =
492 next_skb->len + additionlen;
493 tcb_desc->empkt_num++;
494 } else {
495 break;
496 }
497
498 if (skb_queue_is_last(&rtlpriv->mac80211.skb_waitq[tid],
499 next_skb))
500 break;
501
502 if (tcb_desc->empkt_num >= rtlhal->max_earlymode_num)
503 break;
504 }
505 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
506
507 return true;
508}
509
510
511static void _rtl_pci_tx_chk_waitq(struct ieee80211_hw *hw)
512{
513 struct rtl_priv *rtlpriv = rtl_priv(hw);
514 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
515 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
516 struct sk_buff *skb = NULL;
517 struct ieee80211_tx_info *info = NULL;
518 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
519 int tid;
520
521 if (!rtlpriv->rtlhal.earlymode_enable)
522 return;
523
524 if (rtlpriv->dm.supp_phymode_switch &&
525 (rtlpriv->easy_concurrent_ctl.switch_in_process ||
526 (rtlpriv->buddy_priv &&
527 rtlpriv->buddy_priv->easy_concurrent_ctl.switch_in_process)))
528 return;
529
530 for (tid = 7; tid >= 0; tid--) {
531 u8 hw_queue = ac_to_hwq[rtl_tid_to_ac(tid)];
532 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[hw_queue];
533 while (!mac->act_scanning &&
534 rtlpriv->psc.rfpwr_state == ERFON) {
535 struct rtl_tcb_desc tcb_desc;
536 memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc));
537
538 spin_lock_bh(&rtlpriv->locks.waitq_lock);
539 if (!skb_queue_empty(&mac->skb_waitq[tid]) &&
540 (ring->entries - skb_queue_len(&ring->queue) >
541 rtlhal->max_earlymode_num)) {
542 skb = skb_dequeue(&mac->skb_waitq[tid]);
543 } else {
544 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
545 break;
546 }
547 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
548
549
550
551 info = IEEE80211_SKB_CB(skb);
552 if (info->flags & IEEE80211_TX_CTL_AMPDU)
553 _rtl_update_earlymode_info(hw, skb,
554 &tcb_desc, tid);
555
556 rtlpriv->intf_ops->adapter_tx(hw, NULL, skb, &tcb_desc);
557 }
558 }
559}
560
561
562static void _rtl_pci_tx_isr(struct ieee80211_hw *hw, int prio)
563{
564 struct rtl_priv *rtlpriv = rtl_priv(hw);
565 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
566
567 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio];
568
569 while (skb_queue_len(&ring->queue)) {
570 struct sk_buff *skb;
571 struct ieee80211_tx_info *info;
572 __le16 fc;
573 u8 tid;
574 u8 *entry;
575
576 if (rtlpriv->use_new_trx_flow)
577 entry = (u8 *)(&ring->buffer_desc[ring->idx]);
578 else
579 entry = (u8 *)(&ring->desc[ring->idx]);
580
581 if (!rtlpriv->cfg->ops->is_tx_desc_closed(hw, prio, ring->idx))
582 return;
583 ring->idx = (ring->idx + 1) % ring->entries;
584
585 skb = __skb_dequeue(&ring->queue);
586 pci_unmap_single(rtlpci->pdev,
587 rtlpriv->cfg->ops->
588 get_desc((u8 *)entry, true,
589 HW_DESC_TXBUFF_ADDR),
590 skb->len, PCI_DMA_TODEVICE);
591
592
593 if (rtlpriv->rtlhal.earlymode_enable)
594 skb_pull(skb, EM_HDR_LEN);
595
596 RT_TRACE(rtlpriv, (COMP_INTR | COMP_SEND), DBG_TRACE,
597 "new ring->idx:%d, free: skb_queue_len:%d, free: seq:%x\n",
598 ring->idx,
599 skb_queue_len(&ring->queue),
600 *(u16 *)(skb->data + 22));
601
602 if (prio == TXCMD_QUEUE) {
603 dev_kfree_skb(skb);
604 goto tx_status_ok;
605
606 }
607
608
609
610
611
612 fc = rtl_get_fc(skb);
613 if (ieee80211_is_nullfunc(fc)) {
614 if (ieee80211_has_pm(fc)) {
615 rtlpriv->mac80211.offchan_delay = true;
616 rtlpriv->psc.state_inap = true;
617 } else {
618 rtlpriv->psc.state_inap = false;
619 }
620 }
621 if (ieee80211_is_action(fc)) {
622 struct ieee80211_mgmt *action_frame =
623 (struct ieee80211_mgmt *)skb->data;
624 if (action_frame->u.action.u.ht_smps.action ==
625 WLAN_HT_ACTION_SMPS) {
626 dev_kfree_skb(skb);
627 goto tx_status_ok;
628 }
629 }
630
631
632 tid = rtl_get_tid(skb);
633 if (tid <= 7)
634 rtlpriv->link_info.tidtx_inperiod[tid]++;
635
636 info = IEEE80211_SKB_CB(skb);
637 ieee80211_tx_info_clear_status(info);
638
639 info->flags |= IEEE80211_TX_STAT_ACK;
640
641
642 ieee80211_tx_status_irqsafe(hw, skb);
643
644 if ((ring->entries - skb_queue_len(&ring->queue))
645 == 2) {
646
647 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
648 "more desc left, wake skb_queue@%d, ring->idx = %d, skb_queue_len = 0x%x\n",
649 prio, ring->idx,
650 skb_queue_len(&ring->queue));
651
652 ieee80211_wake_queue(hw,
653 skb_get_queue_mapping
654 (skb));
655 }
656tx_status_ok:
657 skb = NULL;
658 }
659
660 if (((rtlpriv->link_info.num_rx_inperiod +
661 rtlpriv->link_info.num_tx_inperiod) > 8) ||
662 (rtlpriv->link_info.num_rx_inperiod > 2)) {
663 rtlpriv->enter_ps = false;
664 schedule_work(&rtlpriv->works.lps_change_work);
665 }
666}
667
668static int _rtl_pci_init_one_rxdesc(struct ieee80211_hw *hw,
669 u8 *entry, int rxring_idx, int desc_idx)
670{
671 struct rtl_priv *rtlpriv = rtl_priv(hw);
672 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
673 u32 bufferaddress;
674 u8 tmp_one = 1;
675 struct sk_buff *skb;
676
677 skb = dev_alloc_skb(rtlpci->rxbuffersize);
678 if (!skb)
679 return 0;
680 rtlpci->rx_ring[rxring_idx].rx_buf[desc_idx] = skb;
681
682
683 *((dma_addr_t *)skb->cb) =
684 pci_map_single(rtlpci->pdev, skb_tail_pointer(skb),
685 rtlpci->rxbuffersize, PCI_DMA_FROMDEVICE);
686 bufferaddress = *((dma_addr_t *)skb->cb);
687 if (pci_dma_mapping_error(rtlpci->pdev, bufferaddress))
688 return 0;
689 if (rtlpriv->use_new_trx_flow) {
690 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
691 HW_DESC_RX_PREPARE,
692 (u8 *)&bufferaddress);
693 } else {
694 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
695 HW_DESC_RXBUFF_ADDR,
696 (u8 *)&bufferaddress);
697 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
698 HW_DESC_RXPKT_LEN,
699 (u8 *)&rtlpci->rxbuffersize);
700 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
701 HW_DESC_RXOWN,
702 (u8 *)&tmp_one);
703 }
704 return 1;
705}
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720static void _rtl_pci_rx_to_mac80211(struct ieee80211_hw *hw,
721 struct sk_buff *skb,
722 struct ieee80211_rx_status rx_status)
723{
724 if (unlikely(!rtl_action_proc(hw, skb, false))) {
725 dev_kfree_skb_any(skb);
726 } else {
727 struct sk_buff *uskb = NULL;
728 u8 *pdata;
729
730 uskb = dev_alloc_skb(skb->len + 128);
731 if (likely(uskb)) {
732 memcpy(IEEE80211_SKB_RXCB(uskb), &rx_status,
733 sizeof(rx_status));
734 pdata = (u8 *)skb_put(uskb, skb->len);
735 memcpy(pdata, skb->data, skb->len);
736 dev_kfree_skb_any(skb);
737 ieee80211_rx_irqsafe(hw, uskb);
738 } else {
739 ieee80211_rx_irqsafe(hw, skb);
740 }
741 }
742}
743
744
745static void _rtl_pci_hs_interrupt(struct ieee80211_hw *hw)
746{
747 struct rtl_priv *rtlpriv = rtl_priv(hw);
748 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
749
750 rtl_write_byte(rtlpriv, rtlpriv->cfg->maps[MAC_HSISR],
751 rtl_read_byte(rtlpriv, rtlpriv->cfg->maps[MAC_HSISR]) |
752 rtlpci->sys_irq_mask);
753}
754
755static void _rtl_pci_rx_interrupt(struct ieee80211_hw *hw)
756{
757 struct rtl_priv *rtlpriv = rtl_priv(hw);
758 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
759 int rxring_idx = RTL_PCI_RX_MPDU_QUEUE;
760 struct ieee80211_rx_status rx_status = { 0 };
761 unsigned int count = rtlpci->rxringcount;
762 u8 own;
763 u8 tmp_one;
764 bool unicast = false;
765 u8 hw_queue = 0;
766 unsigned int rx_remained_cnt;
767 struct rtl_stats stats = {
768 .signal = 0,
769 .rate = 0,
770 };
771
772
773 while (count--) {
774 struct ieee80211_hdr *hdr;
775 __le16 fc;
776 u16 len;
777
778 struct rtl_rx_buffer_desc *buffer_desc = NULL;
779
780 struct rtl_rx_desc *pdesc = NULL;
781
782 struct sk_buff *skb = rtlpci->rx_ring[rxring_idx].rx_buf[
783 rtlpci->rx_ring[rxring_idx].idx];
784
785 if (rtlpriv->use_new_trx_flow) {
786 rx_remained_cnt =
787 rtlpriv->cfg->ops->rx_desc_buff_remained_cnt(hw,
788 hw_queue);
789 if (rx_remained_cnt < 1)
790 return;
791
792 } else {
793 pdesc = &rtlpci->rx_ring[rxring_idx].desc[
794 rtlpci->rx_ring[rxring_idx].idx];
795
796 own = (u8)rtlpriv->cfg->ops->get_desc((u8 *)pdesc,
797 false,
798 HW_DESC_OWN);
799 if (own)
800 return;
801 }
802
803
804
805
806
807 pci_unmap_single(rtlpci->pdev, *((dma_addr_t *)skb->cb),
808 rtlpci->rxbuffersize, PCI_DMA_FROMDEVICE);
809
810 if (rtlpriv->use_new_trx_flow) {
811 buffer_desc =
812 &rtlpci->rx_ring[rxring_idx].buffer_desc
813 [rtlpci->rx_ring[rxring_idx].idx];
814
815 pdesc = (struct rtl_rx_desc *)skb->data;
816 }
817 memset(&rx_status , 0 , sizeof(rx_status));
818 rtlpriv->cfg->ops->query_rx_desc(hw, &stats,
819 &rx_status, (u8 *)pdesc, skb);
820
821 if (rtlpriv->use_new_trx_flow)
822 rtlpriv->cfg->ops->rx_check_dma_ok(hw,
823 (u8 *)buffer_desc,
824 hw_queue);
825
826 len = rtlpriv->cfg->ops->get_desc((u8 *)pdesc, false,
827 HW_DESC_RXPKT_LEN);
828
829 if (skb->end - skb->tail > len) {
830 skb_put(skb, len);
831 if (rtlpriv->use_new_trx_flow)
832 skb_reserve(skb, stats.rx_drvinfo_size +
833 stats.rx_bufshift + 24);
834 else
835 skb_reserve(skb, stats.rx_drvinfo_size +
836 stats.rx_bufshift);
837
838 } else {
839 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
840 "skb->end - skb->tail = %d, len is %d\n",
841 skb->end - skb->tail, len);
842 break;
843 }
844
845 if (rtlpriv->cfg->ops->rx_command_packet &&
846 rtlpriv->cfg->ops->rx_command_packet(hw, stats, skb)) {
847 dev_kfree_skb_any(skb);
848 goto end;
849 }
850
851
852
853
854
855
856
857
858 hdr = rtl_get_hdr(skb);
859 fc = rtl_get_fc(skb);
860
861 if (!stats.crc && !stats.hwerror) {
862 memcpy(IEEE80211_SKB_RXCB(skb), &rx_status,
863 sizeof(rx_status));
864
865 if (is_broadcast_ether_addr(hdr->addr1)) {
866 ;
867 } else if (is_multicast_ether_addr(hdr->addr1)) {
868 ;
869 } else {
870 unicast = true;
871 rtlpriv->stats.rxbytesunicast += skb->len;
872 }
873 rtl_is_special_data(hw, skb, false);
874
875 if (ieee80211_is_data(fc)) {
876 rtlpriv->cfg->ops->led_control(hw, LED_CTL_RX);
877 if (unicast)
878 rtlpriv->link_info.num_rx_inperiod++;
879 }
880
881 rtl_beacon_statistic(hw, skb);
882 rtl_p2p_info(hw, (void *)skb->data, skb->len);
883
884 rtl_swlps_beacon(hw, (void *)skb->data, skb->len);
885 rtl_recognize_peer(hw, (void *)skb->data, skb->len);
886 if ((rtlpriv->mac80211.opmode == NL80211_IFTYPE_AP) &&
887 (rtlpriv->rtlhal.current_bandtype ==
888 BAND_ON_2_4G) &&
889 (ieee80211_is_beacon(fc) ||
890 ieee80211_is_probe_resp(fc))) {
891 dev_kfree_skb_any(skb);
892 } else {
893 _rtl_pci_rx_to_mac80211(hw, skb, rx_status);
894 }
895 } else {
896 dev_kfree_skb_any(skb);
897 }
898 if (rtlpriv->use_new_trx_flow) {
899 rtlpci->rx_ring[hw_queue].next_rx_rp += 1;
900 rtlpci->rx_ring[hw_queue].next_rx_rp %=
901 RTL_PCI_MAX_RX_COUNT;
902
903 rx_remained_cnt--;
904 rtl_write_word(rtlpriv, 0x3B4,
905 rtlpci->rx_ring[hw_queue].next_rx_rp);
906 }
907 if (((rtlpriv->link_info.num_rx_inperiod +
908 rtlpriv->link_info.num_tx_inperiod) > 8) ||
909 (rtlpriv->link_info.num_rx_inperiod > 2)) {
910 rtlpriv->enter_ps = false;
911 schedule_work(&rtlpriv->works.lps_change_work);
912 }
913end:
914 if (rtlpriv->use_new_trx_flow) {
915 _rtl_pci_init_one_rxdesc(hw, (u8 *)buffer_desc,
916 rxring_idx,
917 rtlpci->rx_ring[rxring_idx].idx);
918 } else {
919 _rtl_pci_init_one_rxdesc(hw, (u8 *)pdesc, rxring_idx,
920 rtlpci->rx_ring[rxring_idx].idx);
921
922 if (rtlpci->rx_ring[rxring_idx].idx ==
923 rtlpci->rxringcount - 1)
924 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc,
925 false,
926 HW_DESC_RXERO,
927 (u8 *)&tmp_one);
928 }
929 rtlpci->rx_ring[rxring_idx].idx =
930 (rtlpci->rx_ring[rxring_idx].idx + 1) %
931 rtlpci->rxringcount;
932 }
933}
934
935static irqreturn_t _rtl_pci_interrupt(int irq, void *dev_id)
936{
937 struct ieee80211_hw *hw = dev_id;
938 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
939 struct rtl_priv *rtlpriv = rtl_priv(hw);
940 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
941 unsigned long flags;
942 u32 inta = 0;
943 u32 intb = 0;
944 irqreturn_t ret = IRQ_HANDLED;
945
946 if (rtlpci->irq_enabled == 0)
947 return ret;
948
949 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock , flags);
950 rtlpriv->cfg->ops->disable_interrupt(hw);
951
952
953 rtlpriv->cfg->ops->interrupt_recognized(hw, &inta, &intb);
954
955
956 if (!inta || inta == 0xffff)
957 goto done;
958
959
960 if (inta & rtlpriv->cfg->maps[RTL_IMR_TBDOK]) {
961 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
962 "beacon ok interrupt!\n");
963 }
964
965 if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_TBDER])) {
966 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
967 "beacon err interrupt!\n");
968 }
969
970 if (inta & rtlpriv->cfg->maps[RTL_IMR_BDOK]) {
971 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, "beacon interrupt!\n");
972 }
973
974 if (inta & rtlpriv->cfg->maps[RTL_IMR_BCNINT]) {
975 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
976 "prepare beacon for interrupt!\n");
977 tasklet_schedule(&rtlpriv->works.irq_prepare_bcn_tasklet);
978 }
979
980
981 if (unlikely(intb & rtlpriv->cfg->maps[RTL_IMR_TXFOVW]))
982 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, "IMR_TXFOVW!\n");
983
984 if (inta & rtlpriv->cfg->maps[RTL_IMR_MGNTDOK]) {
985 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
986 "Manage ok interrupt!\n");
987 _rtl_pci_tx_isr(hw, MGNT_QUEUE);
988 }
989
990 if (inta & rtlpriv->cfg->maps[RTL_IMR_HIGHDOK]) {
991 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
992 "HIGH_QUEUE ok interrupt!\n");
993 _rtl_pci_tx_isr(hw, HIGH_QUEUE);
994 }
995
996 if (inta & rtlpriv->cfg->maps[RTL_IMR_BKDOK]) {
997 rtlpriv->link_info.num_tx_inperiod++;
998
999 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
1000 "BK Tx OK interrupt!\n");
1001 _rtl_pci_tx_isr(hw, BK_QUEUE);
1002 }
1003
1004 if (inta & rtlpriv->cfg->maps[RTL_IMR_BEDOK]) {
1005 rtlpriv->link_info.num_tx_inperiod++;
1006
1007 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
1008 "BE TX OK interrupt!\n");
1009 _rtl_pci_tx_isr(hw, BE_QUEUE);
1010 }
1011
1012 if (inta & rtlpriv->cfg->maps[RTL_IMR_VIDOK]) {
1013 rtlpriv->link_info.num_tx_inperiod++;
1014
1015 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
1016 "VI TX OK interrupt!\n");
1017 _rtl_pci_tx_isr(hw, VI_QUEUE);
1018 }
1019
1020 if (inta & rtlpriv->cfg->maps[RTL_IMR_VODOK]) {
1021 rtlpriv->link_info.num_tx_inperiod++;
1022
1023 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
1024 "Vo TX OK interrupt!\n");
1025 _rtl_pci_tx_isr(hw, VO_QUEUE);
1026 }
1027
1028 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE) {
1029 if (inta & rtlpriv->cfg->maps[RTL_IMR_COMDOK]) {
1030 rtlpriv->link_info.num_tx_inperiod++;
1031
1032 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
1033 "CMD TX OK interrupt!\n");
1034 _rtl_pci_tx_isr(hw, TXCMD_QUEUE);
1035 }
1036 }
1037
1038
1039 if (inta & rtlpriv->cfg->maps[RTL_IMR_ROK]) {
1040 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, "Rx ok interrupt!\n");
1041 _rtl_pci_rx_interrupt(hw);
1042 }
1043
1044 if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_RDU])) {
1045 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1046 "rx descriptor unavailable!\n");
1047 _rtl_pci_rx_interrupt(hw);
1048 }
1049
1050 if (unlikely(intb & rtlpriv->cfg->maps[RTL_IMR_RXFOVW])) {
1051 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, "rx overflow !\n");
1052 _rtl_pci_rx_interrupt(hw);
1053 }
1054
1055
1056 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8723AE) {
1057 if (inta & rtlpriv->cfg->maps[RTL_IMR_C2HCMD]) {
1058 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
1059 "firmware interrupt!\n");
1060 queue_delayed_work(rtlpriv->works.rtl_wq,
1061 &rtlpriv->works.fwevt_wq, 0);
1062 }
1063 }
1064
1065
1066
1067
1068
1069
1070
1071 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8188EE ||
1072 rtlhal->hw_type == HARDWARE_TYPE_RTL8723BE) {
1073 if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_HSISR_IND])) {
1074 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
1075 "hsisr interrupt!\n");
1076 _rtl_pci_hs_interrupt(hw);
1077 }
1078 }
1079
1080 if (rtlpriv->rtlhal.earlymode_enable)
1081 tasklet_schedule(&rtlpriv->works.irq_tasklet);
1082
1083done:
1084 rtlpriv->cfg->ops->enable_interrupt(hw);
1085 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1086 return ret;
1087}
1088
1089static void _rtl_pci_irq_tasklet(struct ieee80211_hw *hw)
1090{
1091 _rtl_pci_tx_chk_waitq(hw);
1092}
1093
1094static void _rtl_pci_prepare_bcn_tasklet(struct ieee80211_hw *hw)
1095{
1096 struct rtl_priv *rtlpriv = rtl_priv(hw);
1097 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1098 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1099 struct rtl8192_tx_ring *ring = NULL;
1100 struct ieee80211_hdr *hdr = NULL;
1101 struct ieee80211_tx_info *info = NULL;
1102 struct sk_buff *pskb = NULL;
1103 struct rtl_tx_desc *pdesc = NULL;
1104 struct rtl_tcb_desc tcb_desc;
1105
1106 struct rtl_tx_buffer_desc *pbuffer_desc = NULL;
1107 u8 temp_one = 1;
1108
1109 memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc));
1110 ring = &rtlpci->tx_ring[BEACON_QUEUE];
1111 pskb = __skb_dequeue(&ring->queue);
1112 if (pskb)
1113 kfree_skb(pskb);
1114
1115
1116 pskb = ieee80211_beacon_get(hw, mac->vif);
1117 if (pskb == NULL)
1118 return;
1119 hdr = rtl_get_hdr(pskb);
1120 info = IEEE80211_SKB_CB(pskb);
1121 pdesc = &ring->desc[0];
1122 if (rtlpriv->use_new_trx_flow)
1123 pbuffer_desc = &ring->buffer_desc[0];
1124
1125 rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *)pdesc,
1126 (u8 *)pbuffer_desc, info, NULL, pskb,
1127 BEACON_QUEUE, &tcb_desc);
1128
1129 __skb_queue_tail(&ring->queue, pskb);
1130
1131 if (rtlpriv->use_new_trx_flow) {
1132 temp_one = 4;
1133 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pbuffer_desc, true,
1134 HW_DESC_OWN, (u8 *)&temp_one);
1135 } else {
1136 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, true, HW_DESC_OWN,
1137 &temp_one);
1138 }
1139 return;
1140}
1141
1142static void _rtl_pci_init_trx_var(struct ieee80211_hw *hw)
1143{
1144 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1145 struct rtl_priv *rtlpriv = rtl_priv(hw);
1146 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1147 u8 i;
1148 u16 desc_num;
1149
1150 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192EE)
1151 desc_num = TX_DESC_NUM_92E;
1152 else
1153 desc_num = RT_TXDESC_NUM;
1154
1155 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
1156 rtlpci->txringcount[i] = desc_num;
1157
1158
1159
1160
1161
1162 rtlpci->txringcount[BEACON_QUEUE] = 2;
1163
1164
1165
1166
1167
1168 if (!rtl_priv(hw)->use_new_trx_flow)
1169 rtlpci->txringcount[BE_QUEUE] = RT_TXDESC_NUM_BE_QUEUE;
1170
1171 rtlpci->rxbuffersize = 9100;
1172 rtlpci->rxringcount = RTL_PCI_MAX_RX_COUNT;
1173}
1174
1175static void _rtl_pci_init_struct(struct ieee80211_hw *hw,
1176 struct pci_dev *pdev)
1177{
1178 struct rtl_priv *rtlpriv = rtl_priv(hw);
1179 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1180 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1181 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1182
1183 rtlpci->up_first_time = true;
1184 rtlpci->being_init_adapter = false;
1185
1186 rtlhal->hw = hw;
1187 rtlpci->pdev = pdev;
1188
1189
1190 _rtl_pci_init_trx_var(hw);
1191
1192 mac->beacon_interval = 100;
1193
1194
1195 mac->min_space_cfg = 0;
1196 mac->max_mss_density = 0;
1197
1198 mac->current_ampdu_density = 7;
1199 mac->current_ampdu_factor = 3;
1200
1201
1202 rtlpci->acm_method = EACMWAY2_SW;
1203
1204
1205 tasklet_init(&rtlpriv->works.irq_tasklet,
1206 (void (*)(unsigned long))_rtl_pci_irq_tasklet,
1207 (unsigned long)hw);
1208 tasklet_init(&rtlpriv->works.irq_prepare_bcn_tasklet,
1209 (void (*)(unsigned long))_rtl_pci_prepare_bcn_tasklet,
1210 (unsigned long)hw);
1211 INIT_WORK(&rtlpriv->works.lps_change_work,
1212 rtl_lps_change_work_callback);
1213}
1214
1215static int _rtl_pci_init_tx_ring(struct ieee80211_hw *hw,
1216 unsigned int prio, unsigned int entries)
1217{
1218 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1219 struct rtl_priv *rtlpriv = rtl_priv(hw);
1220 struct rtl_tx_buffer_desc *buffer_desc;
1221 struct rtl_tx_desc *desc;
1222 dma_addr_t buffer_desc_dma, desc_dma;
1223 u32 nextdescaddress;
1224 int i;
1225
1226
1227 if (rtlpriv->use_new_trx_flow) {
1228 buffer_desc =
1229 pci_zalloc_consistent(rtlpci->pdev,
1230 sizeof(*buffer_desc) * entries,
1231 &buffer_desc_dma);
1232
1233 if (!buffer_desc || (unsigned long)buffer_desc & 0xFF) {
1234 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1235 "Cannot allocate TX ring (prio = %d)\n",
1236 prio);
1237 return -ENOMEM;
1238 }
1239
1240 rtlpci->tx_ring[prio].buffer_desc = buffer_desc;
1241 rtlpci->tx_ring[prio].buffer_desc_dma = buffer_desc_dma;
1242
1243 rtlpci->tx_ring[prio].cur_tx_rp = 0;
1244 rtlpci->tx_ring[prio].cur_tx_wp = 0;
1245 rtlpci->tx_ring[prio].avl_desc = entries;
1246 }
1247
1248
1249 desc = pci_zalloc_consistent(rtlpci->pdev,
1250 sizeof(*desc) * entries, &desc_dma);
1251
1252 if (!desc || (unsigned long)desc & 0xFF) {
1253 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1254 "Cannot allocate TX ring (prio = %d)\n", prio);
1255 return -ENOMEM;
1256 }
1257
1258 rtlpci->tx_ring[prio].desc = desc;
1259 rtlpci->tx_ring[prio].dma = desc_dma;
1260
1261 rtlpci->tx_ring[prio].idx = 0;
1262 rtlpci->tx_ring[prio].entries = entries;
1263 skb_queue_head_init(&rtlpci->tx_ring[prio].queue);
1264
1265 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "queue:%d, ring_addr:%p\n",
1266 prio, desc);
1267
1268
1269 if (!rtlpriv->use_new_trx_flow) {
1270 for (i = 0; i < entries; i++) {
1271 nextdescaddress = (u32)desc_dma +
1272 ((i + 1) % entries) *
1273 sizeof(*desc);
1274
1275 rtlpriv->cfg->ops->set_desc(hw, (u8 *)&desc[i],
1276 true,
1277 HW_DESC_TX_NEXTDESC_ADDR,
1278 (u8 *)&nextdescaddress);
1279 }
1280 }
1281 return 0;
1282}
1283
1284static int _rtl_pci_init_rx_ring(struct ieee80211_hw *hw, int rxring_idx)
1285{
1286 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1287 struct rtl_priv *rtlpriv = rtl_priv(hw);
1288 int i;
1289
1290 if (rtlpriv->use_new_trx_flow) {
1291 struct rtl_rx_buffer_desc *entry = NULL;
1292
1293 rtlpci->rx_ring[rxring_idx].buffer_desc =
1294 pci_zalloc_consistent(rtlpci->pdev,
1295 sizeof(*rtlpci->rx_ring[rxring_idx].
1296 buffer_desc) *
1297 rtlpci->rxringcount,
1298 &rtlpci->rx_ring[rxring_idx].dma);
1299 if (!rtlpci->rx_ring[rxring_idx].buffer_desc ||
1300 (ulong)rtlpci->rx_ring[rxring_idx].buffer_desc & 0xFF) {
1301 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1302 "Cannot allocate RX ring\n");
1303 return -ENOMEM;
1304 }
1305
1306
1307 rtlpci->rx_ring[rxring_idx].idx = 0;
1308 for (i = 0; i < rtlpci->rxringcount; i++) {
1309 entry = &rtlpci->rx_ring[rxring_idx].buffer_desc[i];
1310 if (!_rtl_pci_init_one_rxdesc(hw, (u8 *)entry,
1311 rxring_idx, i))
1312 return -ENOMEM;
1313 }
1314 } else {
1315 struct rtl_rx_desc *entry = NULL;
1316 u8 tmp_one = 1;
1317
1318 rtlpci->rx_ring[rxring_idx].desc =
1319 pci_zalloc_consistent(rtlpci->pdev,
1320 sizeof(*rtlpci->rx_ring[rxring_idx].
1321 desc) * rtlpci->rxringcount,
1322 &rtlpci->rx_ring[rxring_idx].dma);
1323 if (!rtlpci->rx_ring[rxring_idx].desc ||
1324 (unsigned long)rtlpci->rx_ring[rxring_idx].desc & 0xFF) {
1325 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1326 "Cannot allocate RX ring\n");
1327 return -ENOMEM;
1328 }
1329
1330
1331 rtlpci->rx_ring[rxring_idx].idx = 0;
1332
1333 for (i = 0; i < rtlpci->rxringcount; i++) {
1334 entry = &rtlpci->rx_ring[rxring_idx].desc[i];
1335 if (!_rtl_pci_init_one_rxdesc(hw, (u8 *)entry,
1336 rxring_idx, i))
1337 return -ENOMEM;
1338 }
1339
1340 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
1341 HW_DESC_RXERO, &tmp_one);
1342 }
1343 return 0;
1344}
1345
1346static void _rtl_pci_free_tx_ring(struct ieee80211_hw *hw,
1347 unsigned int prio)
1348{
1349 struct rtl_priv *rtlpriv = rtl_priv(hw);
1350 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1351 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio];
1352
1353
1354 while (skb_queue_len(&ring->queue)) {
1355 u8 *entry;
1356 struct sk_buff *skb = __skb_dequeue(&ring->queue);
1357
1358 if (rtlpriv->use_new_trx_flow)
1359 entry = (u8 *)(&ring->buffer_desc[ring->idx]);
1360 else
1361 entry = (u8 *)(&ring->desc[ring->idx]);
1362
1363 pci_unmap_single(rtlpci->pdev,
1364 rtlpriv->cfg->
1365 ops->get_desc((u8 *)entry, true,
1366 HW_DESC_TXBUFF_ADDR),
1367 skb->len, PCI_DMA_TODEVICE);
1368 kfree_skb(skb);
1369 ring->idx = (ring->idx + 1) % ring->entries;
1370 }
1371
1372
1373 pci_free_consistent(rtlpci->pdev,
1374 sizeof(*ring->desc) * ring->entries,
1375 ring->desc, ring->dma);
1376 ring->desc = NULL;
1377 if (rtlpriv->use_new_trx_flow) {
1378 pci_free_consistent(rtlpci->pdev,
1379 sizeof(*ring->buffer_desc) * ring->entries,
1380 ring->buffer_desc, ring->buffer_desc_dma);
1381 ring->buffer_desc = NULL;
1382 }
1383}
1384
1385static void _rtl_pci_free_rx_ring(struct ieee80211_hw *hw, int rxring_idx)
1386{
1387 struct rtl_priv *rtlpriv = rtl_priv(hw);
1388 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1389 int i;
1390
1391
1392 for (i = 0; i < rtlpci->rxringcount; i++) {
1393 struct sk_buff *skb = rtlpci->rx_ring[rxring_idx].rx_buf[i];
1394
1395 if (!skb)
1396 continue;
1397 pci_unmap_single(rtlpci->pdev, *((dma_addr_t *)skb->cb),
1398 rtlpci->rxbuffersize, PCI_DMA_FROMDEVICE);
1399 kfree_skb(skb);
1400 }
1401
1402
1403 if (rtlpriv->use_new_trx_flow) {
1404 pci_free_consistent(rtlpci->pdev,
1405 sizeof(*rtlpci->rx_ring[rxring_idx].
1406 buffer_desc) * rtlpci->rxringcount,
1407 rtlpci->rx_ring[rxring_idx].buffer_desc,
1408 rtlpci->rx_ring[rxring_idx].dma);
1409 rtlpci->rx_ring[rxring_idx].buffer_desc = NULL;
1410 } else {
1411 pci_free_consistent(rtlpci->pdev,
1412 sizeof(*rtlpci->rx_ring[rxring_idx].desc) *
1413 rtlpci->rxringcount,
1414 rtlpci->rx_ring[rxring_idx].desc,
1415 rtlpci->rx_ring[rxring_idx].dma);
1416 rtlpci->rx_ring[rxring_idx].desc = NULL;
1417 }
1418}
1419
1420static int _rtl_pci_init_trx_ring(struct ieee80211_hw *hw)
1421{
1422 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1423 int ret;
1424 int i, rxring_idx;
1425
1426
1427
1428
1429 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++) {
1430 ret = _rtl_pci_init_rx_ring(hw, rxring_idx);
1431 if (ret)
1432 return ret;
1433 }
1434
1435 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) {
1436 ret = _rtl_pci_init_tx_ring(hw, i,
1437 rtlpci->txringcount[i]);
1438 if (ret)
1439 goto err_free_rings;
1440 }
1441
1442 return 0;
1443
1444err_free_rings:
1445 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++)
1446 _rtl_pci_free_rx_ring(hw, rxring_idx);
1447
1448 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
1449 if (rtlpci->tx_ring[i].desc ||
1450 rtlpci->tx_ring[i].buffer_desc)
1451 _rtl_pci_free_tx_ring(hw, i);
1452
1453 return 1;
1454}
1455
1456static int _rtl_pci_deinit_trx_ring(struct ieee80211_hw *hw)
1457{
1458 u32 i, rxring_idx;
1459
1460
1461 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++)
1462 _rtl_pci_free_rx_ring(hw, rxring_idx);
1463
1464
1465 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
1466 _rtl_pci_free_tx_ring(hw, i);
1467
1468 return 0;
1469}
1470
1471int rtl_pci_reset_trx_ring(struct ieee80211_hw *hw)
1472{
1473 struct rtl_priv *rtlpriv = rtl_priv(hw);
1474 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1475 int i, rxring_idx;
1476 unsigned long flags;
1477 u8 tmp_one = 1;
1478 u32 bufferaddress;
1479
1480
1481 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++) {
1482
1483
1484
1485
1486 if (!rtlpriv->use_new_trx_flow &&
1487 rtlpci->rx_ring[rxring_idx].desc) {
1488 struct rtl_rx_desc *entry = NULL;
1489
1490 rtlpci->rx_ring[rxring_idx].idx = 0;
1491 for (i = 0; i < rtlpci->rxringcount; i++) {
1492 entry = &rtlpci->rx_ring[rxring_idx].desc[i];
1493 bufferaddress =
1494 rtlpriv->cfg->ops->get_desc((u8 *)entry,
1495 false , HW_DESC_RXBUFF_ADDR);
1496 memset((u8 *)entry , 0 ,
1497 sizeof(*rtlpci->rx_ring
1498 [rxring_idx].desc));
1499 if (rtlpriv->use_new_trx_flow) {
1500 rtlpriv->cfg->ops->set_desc(hw,
1501 (u8 *)entry, false,
1502 HW_DESC_RX_PREPARE,
1503 (u8 *)&bufferaddress);
1504 } else {
1505 rtlpriv->cfg->ops->set_desc(hw,
1506 (u8 *)entry, false,
1507 HW_DESC_RXBUFF_ADDR,
1508 (u8 *)&bufferaddress);
1509 rtlpriv->cfg->ops->set_desc(hw,
1510 (u8 *)entry, false,
1511 HW_DESC_RXPKT_LEN,
1512 (u8 *)&rtlpci->rxbuffersize);
1513 rtlpriv->cfg->ops->set_desc(hw,
1514 (u8 *)entry, false,
1515 HW_DESC_RXOWN,
1516 (u8 *)&tmp_one);
1517 }
1518 }
1519 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
1520 HW_DESC_RXERO, (u8 *)&tmp_one);
1521 }
1522 rtlpci->rx_ring[rxring_idx].idx = 0;
1523 }
1524
1525
1526
1527
1528
1529 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
1530 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) {
1531 if (rtlpci->tx_ring[i].desc ||
1532 rtlpci->tx_ring[i].buffer_desc) {
1533 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[i];
1534
1535 while (skb_queue_len(&ring->queue)) {
1536 u8 *entry;
1537 struct sk_buff *skb =
1538 __skb_dequeue(&ring->queue);
1539 if (rtlpriv->use_new_trx_flow)
1540 entry = (u8 *)(&ring->buffer_desc
1541 [ring->idx]);
1542 else
1543 entry = (u8 *)(&ring->desc[ring->idx]);
1544
1545 pci_unmap_single(rtlpci->pdev,
1546 rtlpriv->cfg->ops->
1547 get_desc((u8 *)
1548 entry,
1549 true,
1550 HW_DESC_TXBUFF_ADDR),
1551 skb->len, PCI_DMA_TODEVICE);
1552 kfree_skb(skb);
1553 ring->idx = (ring->idx + 1) % ring->entries;
1554 }
1555 ring->idx = 0;
1556 }
1557 }
1558 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1559
1560 return 0;
1561}
1562
1563static bool rtl_pci_tx_chk_waitq_insert(struct ieee80211_hw *hw,
1564 struct ieee80211_sta *sta,
1565 struct sk_buff *skb)
1566{
1567 struct rtl_priv *rtlpriv = rtl_priv(hw);
1568 struct rtl_sta_info *sta_entry = NULL;
1569 u8 tid = rtl_get_tid(skb);
1570 __le16 fc = rtl_get_fc(skb);
1571
1572 if (!sta)
1573 return false;
1574 sta_entry = (struct rtl_sta_info *)sta->drv_priv;
1575
1576 if (!rtlpriv->rtlhal.earlymode_enable)
1577 return false;
1578 if (ieee80211_is_nullfunc(fc))
1579 return false;
1580 if (ieee80211_is_qos_nullfunc(fc))
1581 return false;
1582 if (ieee80211_is_pspoll(fc))
1583 return false;
1584 if (sta_entry->tids[tid].agg.agg_state != RTL_AGG_OPERATIONAL)
1585 return false;
1586 if (_rtl_mac_to_hwqueue(hw, skb) > VO_QUEUE)
1587 return false;
1588 if (tid > 7)
1589 return false;
1590
1591
1592 if (!rtlpriv->link_info.higher_busytxtraffic[tid])
1593 return false;
1594
1595 spin_lock_bh(&rtlpriv->locks.waitq_lock);
1596 skb_queue_tail(&rtlpriv->mac80211.skb_waitq[tid], skb);
1597 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
1598
1599 return true;
1600}
1601
1602static int rtl_pci_tx(struct ieee80211_hw *hw,
1603 struct ieee80211_sta *sta,
1604 struct sk_buff *skb,
1605 struct rtl_tcb_desc *ptcb_desc)
1606{
1607 struct rtl_priv *rtlpriv = rtl_priv(hw);
1608 struct rtl_sta_info *sta_entry = NULL;
1609 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1610 struct rtl8192_tx_ring *ring;
1611 struct rtl_tx_desc *pdesc;
1612 struct rtl_tx_buffer_desc *ptx_bd_desc = NULL;
1613 u16 idx;
1614 u8 hw_queue = _rtl_mac_to_hwqueue(hw, skb);
1615 unsigned long flags;
1616 struct ieee80211_hdr *hdr = rtl_get_hdr(skb);
1617 __le16 fc = rtl_get_fc(skb);
1618 u8 *pda_addr = hdr->addr1;
1619 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1620
1621 u8 tid = 0;
1622 u16 seq_number = 0;
1623 u8 own;
1624 u8 temp_one = 1;
1625
1626 if (ieee80211_is_mgmt(fc))
1627 rtl_tx_mgmt_proc(hw, skb);
1628
1629 if (rtlpriv->psc.sw_ps_enabled) {
1630 if (ieee80211_is_data(fc) && !ieee80211_is_nullfunc(fc) &&
1631 !ieee80211_has_pm(fc))
1632 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
1633 }
1634
1635 rtl_action_proc(hw, skb, true);
1636
1637 if (is_multicast_ether_addr(pda_addr))
1638 rtlpriv->stats.txbytesmulticast += skb->len;
1639 else if (is_broadcast_ether_addr(pda_addr))
1640 rtlpriv->stats.txbytesbroadcast += skb->len;
1641 else
1642 rtlpriv->stats.txbytesunicast += skb->len;
1643
1644 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
1645 ring = &rtlpci->tx_ring[hw_queue];
1646 if (hw_queue != BEACON_QUEUE) {
1647 if (rtlpriv->use_new_trx_flow)
1648 idx = ring->cur_tx_wp;
1649 else
1650 idx = (ring->idx + skb_queue_len(&ring->queue)) %
1651 ring->entries;
1652 } else {
1653 idx = 0;
1654 }
1655
1656 pdesc = &ring->desc[idx];
1657 if (rtlpriv->use_new_trx_flow) {
1658 ptx_bd_desc = &ring->buffer_desc[idx];
1659 } else {
1660 own = (u8) rtlpriv->cfg->ops->get_desc((u8 *)pdesc,
1661 true, HW_DESC_OWN);
1662
1663 if ((own == 1) && (hw_queue != BEACON_QUEUE)) {
1664 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1665 "No more TX desc@%d, ring->idx = %d, idx = %d, skb_queue_len = 0x%x\n",
1666 hw_queue, ring->idx, idx,
1667 skb_queue_len(&ring->queue));
1668
1669 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock,
1670 flags);
1671 return skb->len;
1672 }
1673 }
1674
1675 if (ieee80211_is_data_qos(fc)) {
1676 tid = rtl_get_tid(skb);
1677 if (sta) {
1678 sta_entry = (struct rtl_sta_info *)sta->drv_priv;
1679 seq_number = (le16_to_cpu(hdr->seq_ctrl) &
1680 IEEE80211_SCTL_SEQ) >> 4;
1681 seq_number += 1;
1682
1683 if (!ieee80211_has_morefrags(hdr->frame_control))
1684 sta_entry->tids[tid].seq_number = seq_number;
1685 }
1686 }
1687
1688 if (ieee80211_is_data(fc))
1689 rtlpriv->cfg->ops->led_control(hw, LED_CTL_TX);
1690
1691 rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *)pdesc,
1692 (u8 *)ptx_bd_desc, info, sta, skb, hw_queue, ptcb_desc);
1693
1694 __skb_queue_tail(&ring->queue, skb);
1695
1696 if (rtlpriv->use_new_trx_flow) {
1697 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, true,
1698 HW_DESC_OWN, &hw_queue);
1699 } else {
1700 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, true,
1701 HW_DESC_OWN, &temp_one);
1702 }
1703
1704 if ((ring->entries - skb_queue_len(&ring->queue)) < 2 &&
1705 hw_queue != BEACON_QUEUE) {
1706 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
1707 "less desc left, stop skb_queue@%d, ring->idx = %d, idx = %d, skb_queue_len = 0x%x\n",
1708 hw_queue, ring->idx, idx,
1709 skb_queue_len(&ring->queue));
1710
1711 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
1712 }
1713
1714 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1715
1716 rtlpriv->cfg->ops->tx_polling(hw, hw_queue);
1717
1718 return 0;
1719}
1720
1721static void rtl_pci_flush(struct ieee80211_hw *hw, u32 queues, bool drop)
1722{
1723 struct rtl_priv *rtlpriv = rtl_priv(hw);
1724 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1725 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1726 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1727 u16 i = 0;
1728 int queue_id;
1729 struct rtl8192_tx_ring *ring;
1730
1731 if (mac->skip_scan)
1732 return;
1733
1734 for (queue_id = RTL_PCI_MAX_TX_QUEUE_COUNT - 1; queue_id >= 0;) {
1735 u32 queue_len;
1736
1737 if (((queues >> queue_id) & 0x1) == 0) {
1738 queue_id--;
1739 continue;
1740 }
1741 ring = &pcipriv->dev.tx_ring[queue_id];
1742 queue_len = skb_queue_len(&ring->queue);
1743 if (queue_len == 0 || queue_id == BEACON_QUEUE ||
1744 queue_id == TXCMD_QUEUE) {
1745 queue_id--;
1746 continue;
1747 } else {
1748 msleep(20);
1749 i++;
1750 }
1751
1752
1753 if (rtlpriv->psc.rfpwr_state == ERFOFF ||
1754 is_hal_stop(rtlhal) || i >= 200)
1755 return;
1756 }
1757}
1758
1759static void rtl_pci_deinit(struct ieee80211_hw *hw)
1760{
1761 struct rtl_priv *rtlpriv = rtl_priv(hw);
1762 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1763
1764 _rtl_pci_deinit_trx_ring(hw);
1765
1766 synchronize_irq(rtlpci->pdev->irq);
1767 tasklet_kill(&rtlpriv->works.irq_tasklet);
1768 cancel_work_sync(&rtlpriv->works.lps_change_work);
1769
1770 flush_workqueue(rtlpriv->works.rtl_wq);
1771 destroy_workqueue(rtlpriv->works.rtl_wq);
1772
1773}
1774
1775static int rtl_pci_init(struct ieee80211_hw *hw, struct pci_dev *pdev)
1776{
1777 struct rtl_priv *rtlpriv = rtl_priv(hw);
1778 int err;
1779
1780 _rtl_pci_init_struct(hw, pdev);
1781
1782 err = _rtl_pci_init_trx_ring(hw);
1783 if (err) {
1784 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1785 "tx ring initialization failed\n");
1786 return err;
1787 }
1788
1789 return 0;
1790}
1791
1792static int rtl_pci_start(struct ieee80211_hw *hw)
1793{
1794 struct rtl_priv *rtlpriv = rtl_priv(hw);
1795 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1796 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1797 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1798
1799 int err;
1800
1801 rtl_pci_reset_trx_ring(hw);
1802
1803 rtlpci->driver_is_goingto_unload = false;
1804 if (rtlpriv->cfg->ops->get_btc_status &&
1805 rtlpriv->cfg->ops->get_btc_status()) {
1806 rtlpriv->btcoexist.btc_ops->btc_init_variables(rtlpriv);
1807 rtlpriv->btcoexist.btc_ops->btc_init_hal_vars(rtlpriv);
1808 }
1809 err = rtlpriv->cfg->ops->hw_init(hw);
1810 if (err) {
1811 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1812 "Failed to config hardware!\n");
1813 return err;
1814 }
1815
1816 rtlpriv->cfg->ops->enable_interrupt(hw);
1817 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "enable_interrupt OK\n");
1818
1819 rtl_init_rx_config(hw);
1820
1821
1822 set_hal_start(rtlhal);
1823
1824 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1825
1826 rtlpci->up_first_time = false;
1827
1828 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "rtl_pci_start OK\n");
1829 return 0;
1830}
1831
1832static void rtl_pci_stop(struct ieee80211_hw *hw)
1833{
1834 struct rtl_priv *rtlpriv = rtl_priv(hw);
1835 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1836 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1837 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1838 unsigned long flags;
1839 u8 RFInProgressTimeOut = 0;
1840
1841 if (rtlpriv->cfg->ops->get_btc_status())
1842 rtlpriv->btcoexist.btc_ops->btc_halt_notify();
1843
1844
1845
1846
1847
1848 set_hal_stop(rtlhal);
1849
1850 rtlpci->driver_is_goingto_unload = true;
1851 rtlpriv->cfg->ops->disable_interrupt(hw);
1852 cancel_work_sync(&rtlpriv->works.lps_change_work);
1853
1854 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1855 while (ppsc->rfchange_inprogress) {
1856 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1857 if (RFInProgressTimeOut > 100) {
1858 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1859 break;
1860 }
1861 mdelay(1);
1862 RFInProgressTimeOut++;
1863 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1864 }
1865 ppsc->rfchange_inprogress = true;
1866 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1867
1868 rtlpriv->cfg->ops->hw_disable(hw);
1869
1870 if (!rtlpriv->max_fw_size)
1871 return;
1872 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1873
1874 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1875 ppsc->rfchange_inprogress = false;
1876 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1877
1878 rtl_pci_enable_aspm(hw);
1879}
1880
1881static bool _rtl_pci_find_adapter(struct pci_dev *pdev,
1882 struct ieee80211_hw *hw)
1883{
1884 struct rtl_priv *rtlpriv = rtl_priv(hw);
1885 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1886 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1887 struct pci_dev *bridge_pdev = pdev->bus->self;
1888 u16 venderid;
1889 u16 deviceid;
1890 u8 revisionid;
1891 u16 irqline;
1892 u8 tmp;
1893
1894 pcipriv->ndis_adapter.pcibridge_vendor = PCI_BRIDGE_VENDOR_UNKNOWN;
1895 venderid = pdev->vendor;
1896 deviceid = pdev->device;
1897 pci_read_config_byte(pdev, 0x8, &revisionid);
1898 pci_read_config_word(pdev, 0x3C, &irqline);
1899
1900
1901
1902
1903
1904
1905
1906 if (deviceid == RTL_PCI_8192SE_DID &&
1907 revisionid == RTL_PCI_REVISION_ID_8192PCIE)
1908 return false;
1909
1910 if (deviceid == RTL_PCI_8192_DID ||
1911 deviceid == RTL_PCI_0044_DID ||
1912 deviceid == RTL_PCI_0047_DID ||
1913 deviceid == RTL_PCI_8192SE_DID ||
1914 deviceid == RTL_PCI_8174_DID ||
1915 deviceid == RTL_PCI_8173_DID ||
1916 deviceid == RTL_PCI_8172_DID ||
1917 deviceid == RTL_PCI_8171_DID) {
1918 switch (revisionid) {
1919 case RTL_PCI_REVISION_ID_8192PCIE:
1920 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1921 "8192 PCI-E is found - vid/did=%x/%x\n",
1922 venderid, deviceid);
1923 rtlhal->hw_type = HARDWARE_TYPE_RTL8192E;
1924 return false;
1925 case RTL_PCI_REVISION_ID_8192SE:
1926 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1927 "8192SE is found - vid/did=%x/%x\n",
1928 venderid, deviceid);
1929 rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE;
1930 break;
1931 default:
1932 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1933 "Err: Unknown device - vid/did=%x/%x\n",
1934 venderid, deviceid);
1935 rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE;
1936 break;
1937
1938 }
1939 } else if (deviceid == RTL_PCI_8723AE_DID) {
1940 rtlhal->hw_type = HARDWARE_TYPE_RTL8723AE;
1941 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1942 "8723AE PCI-E is found - "
1943 "vid/did=%x/%x\n", venderid, deviceid);
1944 } else if (deviceid == RTL_PCI_8192CET_DID ||
1945 deviceid == RTL_PCI_8192CE_DID ||
1946 deviceid == RTL_PCI_8191CE_DID ||
1947 deviceid == RTL_PCI_8188CE_DID) {
1948 rtlhal->hw_type = HARDWARE_TYPE_RTL8192CE;
1949 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1950 "8192C PCI-E is found - vid/did=%x/%x\n",
1951 venderid, deviceid);
1952 } else if (deviceid == RTL_PCI_8192DE_DID ||
1953 deviceid == RTL_PCI_8192DE_DID2) {
1954 rtlhal->hw_type = HARDWARE_TYPE_RTL8192DE;
1955 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1956 "8192D PCI-E is found - vid/did=%x/%x\n",
1957 venderid, deviceid);
1958 } else if (deviceid == RTL_PCI_8188EE_DID) {
1959 rtlhal->hw_type = HARDWARE_TYPE_RTL8188EE;
1960 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1961 "Find adapter, Hardware type is 8188EE\n");
1962 } else if (deviceid == RTL_PCI_8723BE_DID) {
1963 rtlhal->hw_type = HARDWARE_TYPE_RTL8723BE;
1964 RT_TRACE(rtlpriv, COMP_INIT , DBG_LOUD,
1965 "Find adapter, Hardware type is 8723BE\n");
1966 } else if (deviceid == RTL_PCI_8192EE_DID) {
1967 rtlhal->hw_type = HARDWARE_TYPE_RTL8192EE;
1968 RT_TRACE(rtlpriv, COMP_INIT , DBG_LOUD,
1969 "Find adapter, Hardware type is 8192EE\n");
1970 } else if (deviceid == RTL_PCI_8821AE_DID) {
1971 rtlhal->hw_type = HARDWARE_TYPE_RTL8821AE;
1972 RT_TRACE(rtlpriv, COMP_INIT , DBG_LOUD,
1973 "Find adapter, Hardware type is 8821AE\n");
1974 } else if (deviceid == RTL_PCI_8812AE_DID) {
1975 rtlhal->hw_type = HARDWARE_TYPE_RTL8812AE;
1976 RT_TRACE(rtlpriv, COMP_INIT , DBG_LOUD,
1977 "Find adapter, Hardware type is 8812AE\n");
1978 } else {
1979 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1980 "Err: Unknown device - vid/did=%x/%x\n",
1981 venderid, deviceid);
1982
1983 rtlhal->hw_type = RTL_DEFAULT_HARDWARE_TYPE;
1984 }
1985
1986 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DE) {
1987 if (revisionid == 0 || revisionid == 1) {
1988 if (revisionid == 0) {
1989 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1990 "Find 92DE MAC0\n");
1991 rtlhal->interfaceindex = 0;
1992 } else if (revisionid == 1) {
1993 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1994 "Find 92DE MAC1\n");
1995 rtlhal->interfaceindex = 1;
1996 }
1997 } else {
1998 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1999 "Unknown device - VendorID/DeviceID=%x/%x, Revision=%x\n",
2000 venderid, deviceid, revisionid);
2001 rtlhal->interfaceindex = 0;
2002 }
2003 }
2004
2005
2006 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192EE)
2007 rtlpriv->use_new_trx_flow = true;
2008 else
2009 rtlpriv->use_new_trx_flow = false;
2010
2011
2012 pcipriv->ndis_adapter.busnumber = pdev->bus->number;
2013 pcipriv->ndis_adapter.devnumber = PCI_SLOT(pdev->devfn);
2014 pcipriv->ndis_adapter.funcnumber = PCI_FUNC(pdev->devfn);
2015
2016
2017 pcipriv->ndis_adapter.pcibridge_vendor = PCI_BRIDGE_VENDOR_UNKNOWN;
2018
2019
2020
2021 if (bridge_pdev) {
2022
2023 pcipriv->ndis_adapter.pcibridge_vendorid = bridge_pdev->vendor;
2024 for (tmp = 0; tmp < PCI_BRIDGE_VENDOR_MAX; tmp++) {
2025 if (bridge_pdev->vendor == pcibridge_vendors[tmp]) {
2026 pcipriv->ndis_adapter.pcibridge_vendor = tmp;
2027 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
2028 "Pci Bridge Vendor is found index: %d\n",
2029 tmp);
2030 break;
2031 }
2032 }
2033 }
2034
2035 if (pcipriv->ndis_adapter.pcibridge_vendor !=
2036 PCI_BRIDGE_VENDOR_UNKNOWN) {
2037 pcipriv->ndis_adapter.pcibridge_busnum =
2038 bridge_pdev->bus->number;
2039 pcipriv->ndis_adapter.pcibridge_devnum =
2040 PCI_SLOT(bridge_pdev->devfn);
2041 pcipriv->ndis_adapter.pcibridge_funcnum =
2042 PCI_FUNC(bridge_pdev->devfn);
2043 pcipriv->ndis_adapter.pcibridge_pciehdr_offset =
2044 pci_pcie_cap(bridge_pdev);
2045 pcipriv->ndis_adapter.num4bytes =
2046 (pcipriv->ndis_adapter.pcibridge_pciehdr_offset + 0x10) / 4;
2047
2048 rtl_pci_get_linkcontrol_field(hw);
2049
2050 if (pcipriv->ndis_adapter.pcibridge_vendor ==
2051 PCI_BRIDGE_VENDOR_AMD) {
2052 pcipriv->ndis_adapter.amd_l1_patch =
2053 rtl_pci_get_amd_l1_patch(hw);
2054 }
2055 }
2056
2057 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
2058 "pcidev busnumber:devnumber:funcnumber:vendor:link_ctl %d:%d:%d:%x:%x\n",
2059 pcipriv->ndis_adapter.busnumber,
2060 pcipriv->ndis_adapter.devnumber,
2061 pcipriv->ndis_adapter.funcnumber,
2062 pdev->vendor, pcipriv->ndis_adapter.linkctrl_reg);
2063
2064 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
2065 "pci_bridge busnumber:devnumber:funcnumber:vendor:pcie_cap:link_ctl_reg:amd %d:%d:%d:%x:%x:%x:%x\n",
2066 pcipriv->ndis_adapter.pcibridge_busnum,
2067 pcipriv->ndis_adapter.pcibridge_devnum,
2068 pcipriv->ndis_adapter.pcibridge_funcnum,
2069 pcibridge_vendors[pcipriv->ndis_adapter.pcibridge_vendor],
2070 pcipriv->ndis_adapter.pcibridge_pciehdr_offset,
2071 pcipriv->ndis_adapter.pcibridge_linkctrlreg,
2072 pcipriv->ndis_adapter.amd_l1_patch);
2073
2074 rtl_pci_parse_configuration(pdev, hw);
2075 list_add_tail(&rtlpriv->list, &rtlpriv->glb_var->glb_priv_list);
2076
2077 return true;
2078}
2079
2080static int rtl_pci_intr_mode_msi(struct ieee80211_hw *hw)
2081{
2082 struct rtl_priv *rtlpriv = rtl_priv(hw);
2083 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2084 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
2085 int ret;
2086
2087 ret = pci_enable_msi(rtlpci->pdev);
2088 if (ret < 0)
2089 return ret;
2090
2091 ret = request_irq(rtlpci->pdev->irq, &_rtl_pci_interrupt,
2092 IRQF_SHARED, KBUILD_MODNAME, hw);
2093 if (ret < 0) {
2094 pci_disable_msi(rtlpci->pdev);
2095 return ret;
2096 }
2097
2098 rtlpci->using_msi = true;
2099
2100 RT_TRACE(rtlpriv, COMP_INIT|COMP_INTR, DBG_DMESG,
2101 "MSI Interrupt Mode!\n");
2102 return 0;
2103}
2104
2105static int rtl_pci_intr_mode_legacy(struct ieee80211_hw *hw)
2106{
2107 struct rtl_priv *rtlpriv = rtl_priv(hw);
2108 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2109 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
2110 int ret;
2111
2112 ret = request_irq(rtlpci->pdev->irq, &_rtl_pci_interrupt,
2113 IRQF_SHARED, KBUILD_MODNAME, hw);
2114 if (ret < 0)
2115 return ret;
2116
2117 rtlpci->using_msi = false;
2118 RT_TRACE(rtlpriv, COMP_INIT|COMP_INTR, DBG_DMESG,
2119 "Pin-based Interrupt Mode!\n");
2120 return 0;
2121}
2122
2123static int rtl_pci_intr_mode_decide(struct ieee80211_hw *hw)
2124{
2125 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2126 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
2127 int ret;
2128
2129 if (rtlpci->msi_support) {
2130 ret = rtl_pci_intr_mode_msi(hw);
2131 if (ret < 0)
2132 ret = rtl_pci_intr_mode_legacy(hw);
2133 } else {
2134 ret = rtl_pci_intr_mode_legacy(hw);
2135 }
2136 return ret;
2137}
2138
2139int rtl_pci_probe(struct pci_dev *pdev,
2140 const struct pci_device_id *id)
2141{
2142 struct ieee80211_hw *hw = NULL;
2143
2144 struct rtl_priv *rtlpriv = NULL;
2145 struct rtl_pci_priv *pcipriv = NULL;
2146 struct rtl_pci *rtlpci;
2147 unsigned long pmem_start, pmem_len, pmem_flags;
2148 int err;
2149
2150 err = pci_enable_device(pdev);
2151 if (err) {
2152 RT_ASSERT(false, "%s : Cannot enable new PCI device\n",
2153 pci_name(pdev));
2154 return err;
2155 }
2156
2157 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
2158 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) {
2159 RT_ASSERT(false,
2160 "Unable to obtain 32bit DMA for consistent allocations\n");
2161 err = -ENOMEM;
2162 goto fail1;
2163 }
2164 }
2165
2166 pci_set_master(pdev);
2167
2168 hw = ieee80211_alloc_hw(sizeof(struct rtl_pci_priv) +
2169 sizeof(struct rtl_priv), &rtl_ops);
2170 if (!hw) {
2171 RT_ASSERT(false,
2172 "%s : ieee80211 alloc failed\n", pci_name(pdev));
2173 err = -ENOMEM;
2174 goto fail1;
2175 }
2176
2177 SET_IEEE80211_DEV(hw, &pdev->dev);
2178 pci_set_drvdata(pdev, hw);
2179
2180 rtlpriv = hw->priv;
2181 rtlpriv->hw = hw;
2182 pcipriv = (void *)rtlpriv->priv;
2183 pcipriv->dev.pdev = pdev;
2184 init_completion(&rtlpriv->firmware_loading_complete);
2185
2186 rtlpriv->proximity.proxim_on = false;
2187
2188 pcipriv = (void *)rtlpriv->priv;
2189 pcipriv->dev.pdev = pdev;
2190
2191
2192 rtlpriv->rtlhal.interface = INTF_PCI;
2193 rtlpriv->cfg = (struct rtl_hal_cfg *)(id->driver_data);
2194 rtlpriv->intf_ops = &rtl_pci_ops;
2195 rtlpriv->glb_var = &rtl_global_var;
2196
2197
2198
2199
2200
2201
2202
2203
2204
2205 rtl_dbgp_flag_init(hw);
2206
2207
2208 err = pci_request_regions(pdev, KBUILD_MODNAME);
2209 if (err) {
2210 RT_ASSERT(false, "Can't obtain PCI resources\n");
2211 goto fail1;
2212 }
2213
2214 pmem_start = pci_resource_start(pdev, rtlpriv->cfg->bar_id);
2215 pmem_len = pci_resource_len(pdev, rtlpriv->cfg->bar_id);
2216 pmem_flags = pci_resource_flags(pdev, rtlpriv->cfg->bar_id);
2217
2218
2219 rtlpriv->io.pci_mem_start =
2220 (unsigned long)pci_iomap(pdev,
2221 rtlpriv->cfg->bar_id, pmem_len);
2222 if (rtlpriv->io.pci_mem_start == 0) {
2223 RT_ASSERT(false, "Can't map PCI mem\n");
2224 err = -ENOMEM;
2225 goto fail2;
2226 }
2227
2228 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
2229 "mem mapped space: start: 0x%08lx len:%08lx flags:%08lx, after map:0x%08lx\n",
2230 pmem_start, pmem_len, pmem_flags,
2231 rtlpriv->io.pci_mem_start);
2232
2233
2234 pci_write_config_byte(pdev, 0x81, 0);
2235
2236 pci_write_config_byte(pdev, 0x44, 0);
2237 pci_write_config_byte(pdev, 0x04, 0x06);
2238 pci_write_config_byte(pdev, 0x04, 0x07);
2239
2240
2241 if (!_rtl_pci_find_adapter(pdev, hw)) {
2242 err = -ENODEV;
2243 goto fail3;
2244 }
2245
2246
2247 _rtl_pci_io_handler_init(&pdev->dev, hw);
2248
2249
2250 rtlpriv->cfg->ops->read_eeprom_info(hw);
2251
2252 if (rtlpriv->cfg->ops->init_sw_vars(hw)) {
2253 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Can't init_sw_vars\n");
2254 err = -ENODEV;
2255 goto fail3;
2256 }
2257 rtlpriv->cfg->ops->init_sw_leds(hw);
2258
2259
2260 rtl_pci_init_aspm(hw);
2261
2262
2263 err = rtl_init_core(hw);
2264 if (err) {
2265 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
2266 "Can't allocate sw for mac80211\n");
2267 goto fail3;
2268 }
2269
2270
2271 err = rtl_pci_init(hw, pdev);
2272 if (err) {
2273 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Failed to init PCI\n");
2274 goto fail3;
2275 }
2276
2277 err = ieee80211_register_hw(hw);
2278 if (err) {
2279 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
2280 "Can't register mac80211 hw.\n");
2281 err = -ENODEV;
2282 goto fail3;
2283 }
2284 rtlpriv->mac80211.mac80211_registered = 1;
2285
2286 err = sysfs_create_group(&pdev->dev.kobj, &rtl_attribute_group);
2287 if (err) {
2288 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
2289 "failed to create sysfs device attributes\n");
2290 goto fail3;
2291 }
2292
2293
2294 rtl_init_rfkill(hw);
2295
2296 rtlpci = rtl_pcidev(pcipriv);
2297 err = rtl_pci_intr_mode_decide(hw);
2298 if (err) {
2299 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
2300 "%s: failed to register IRQ handler\n",
2301 wiphy_name(hw->wiphy));
2302 goto fail3;
2303 }
2304 rtlpci->irq_alloc = 1;
2305
2306 set_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status);
2307 return 0;
2308
2309fail3:
2310 pci_set_drvdata(pdev, NULL);
2311 rtl_deinit_core(hw);
2312
2313 if (rtlpriv->io.pci_mem_start != 0)
2314 pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start);
2315
2316fail2:
2317 pci_release_regions(pdev);
2318 complete(&rtlpriv->firmware_loading_complete);
2319
2320fail1:
2321 if (hw)
2322 ieee80211_free_hw(hw);
2323 pci_disable_device(pdev);
2324
2325 return err;
2326
2327}
2328EXPORT_SYMBOL(rtl_pci_probe);
2329
2330void rtl_pci_disconnect(struct pci_dev *pdev)
2331{
2332 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2333 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2334 struct rtl_priv *rtlpriv = rtl_priv(hw);
2335 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
2336 struct rtl_mac *rtlmac = rtl_mac(rtlpriv);
2337
2338
2339 wait_for_completion(&rtlpriv->firmware_loading_complete);
2340 clear_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status);
2341
2342 sysfs_remove_group(&pdev->dev.kobj, &rtl_attribute_group);
2343
2344
2345 if (rtlmac->mac80211_registered == 1) {
2346 ieee80211_unregister_hw(hw);
2347 rtlmac->mac80211_registered = 0;
2348 } else {
2349 rtl_deinit_deferred_work(hw);
2350 rtlpriv->intf_ops->adapter_stop(hw);
2351 }
2352 rtlpriv->cfg->ops->disable_interrupt(hw);
2353
2354
2355 rtl_deinit_rfkill(hw);
2356
2357 rtl_pci_deinit(hw);
2358 rtl_deinit_core(hw);
2359 rtlpriv->cfg->ops->deinit_sw_vars(hw);
2360
2361 if (rtlpci->irq_alloc) {
2362 synchronize_irq(rtlpci->pdev->irq);
2363 free_irq(rtlpci->pdev->irq, hw);
2364 rtlpci->irq_alloc = 0;
2365 }
2366
2367 if (rtlpci->using_msi)
2368 pci_disable_msi(rtlpci->pdev);
2369
2370 list_del(&rtlpriv->list);
2371 if (rtlpriv->io.pci_mem_start != 0) {
2372 pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start);
2373 pci_release_regions(pdev);
2374 }
2375
2376 pci_disable_device(pdev);
2377
2378 rtl_pci_disable_aspm(hw);
2379
2380 pci_set_drvdata(pdev, NULL);
2381
2382 ieee80211_free_hw(hw);
2383}
2384EXPORT_SYMBOL(rtl_pci_disconnect);
2385
2386#ifdef CONFIG_PM_SLEEP
2387
2388
2389
2390
2391
2392
2393
2394
2395
2396
2397
2398
2399
2400
2401
2402int rtl_pci_suspend(struct device *dev)
2403{
2404 struct pci_dev *pdev = to_pci_dev(dev);
2405 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2406 struct rtl_priv *rtlpriv = rtl_priv(hw);
2407
2408 rtlpriv->cfg->ops->hw_suspend(hw);
2409 rtl_deinit_rfkill(hw);
2410
2411 return 0;
2412}
2413EXPORT_SYMBOL(rtl_pci_suspend);
2414
2415int rtl_pci_resume(struct device *dev)
2416{
2417 struct pci_dev *pdev = to_pci_dev(dev);
2418 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2419 struct rtl_priv *rtlpriv = rtl_priv(hw);
2420
2421 rtlpriv->cfg->ops->hw_resume(hw);
2422 rtl_init_rfkill(hw);
2423 return 0;
2424}
2425EXPORT_SYMBOL(rtl_pci_resume);
2426#endif
2427
2428struct rtl_intf_ops rtl_pci_ops = {
2429 .read_efuse_byte = read_efuse_byte,
2430 .adapter_start = rtl_pci_start,
2431 .adapter_stop = rtl_pci_stop,
2432 .check_buddy_priv = rtl_pci_check_buddy_priv,
2433 .adapter_tx = rtl_pci_tx,
2434 .flush = rtl_pci_flush,
2435 .reset_trx_ring = rtl_pci_reset_trx_ring,
2436 .waitq_insert = rtl_pci_tx_chk_waitq_insert,
2437
2438 .disable_aspm = rtl_pci_disable_aspm,
2439 .enable_aspm = rtl_pci_enable_aspm,
2440};
2441
