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22#include <linux/slab.h>
23
24#include "reg.h"
25#include "boot.h"
26#include "io.h"
27#include "spi.h"
28#include "event.h"
29#include "acx.h"
30
31void wl1251_boot_target_enable_interrupts(struct wl1251 *wl)
32{
33 wl1251_reg_write32(wl, ACX_REG_INTERRUPT_MASK, ~(wl->intr_mask));
34 wl1251_reg_write32(wl, HI_CFG, HI_CFG_DEF_VAL);
35}
36
37int wl1251_boot_soft_reset(struct wl1251 *wl)
38{
39 unsigned long timeout;
40 u32 boot_data;
41
42
43 wl1251_reg_write32(wl, ACX_REG_SLV_SOFT_RESET, ACX_SLV_SOFT_RESET_BIT);
44
45
46 timeout = jiffies + usecs_to_jiffies(SOFT_RESET_MAX_TIME);
47 while (1) {
48 boot_data = wl1251_reg_read32(wl, ACX_REG_SLV_SOFT_RESET);
49 wl1251_debug(DEBUG_BOOT, "soft reset bootdata 0x%x", boot_data);
50 if ((boot_data & ACX_SLV_SOFT_RESET_BIT) == 0)
51 break;
52
53 if (time_after(jiffies, timeout)) {
54
55
56 wl1251_error("soft reset timeout");
57 return -1;
58 }
59
60 udelay(SOFT_RESET_STALL_TIME);
61 }
62
63
64 wl1251_reg_write32(wl, ENABLE, 0x0);
65
66
67 wl1251_reg_write32(wl, SPARE_A2, 0xffff);
68
69 return 0;
70}
71
72int wl1251_boot_init_seq(struct wl1251 *wl)
73{
74 u32 scr_pad6, init_data, tmp, elp_cmd, ref_freq;
75
76
77
78
79
80
81
82
83
84 static const u32 LUT[REF_FREQ_NUM][LUT_PARAM_NUM] = {
85
86 { 83, 87381, 0xB, 5, 0xF00, 3},
87 { 61, 141154, 0xB, 5, 0x1450, 2},
88 { 41, 174763, 0xC, 6, 0x2D00, 1},
89 { 40, 0, 0xC, 6, 0x2EE0, 1},
90 { 47, 162280, 0xC, 6, 0x2760, 1}
91 };
92
93
94 scr_pad6 = wl1251_reg_read32(wl, SCR_PAD6);
95 wl1251_debug(DEBUG_BOOT, "scr_pad6 0x%x", scr_pad6);
96
97
98 elp_cmd = wl1251_reg_read32(wl, ELP_CMD);
99 wl1251_debug(DEBUG_BOOT, "elp_cmd 0x%x", elp_cmd);
100
101
102 ref_freq = scr_pad6 & 0x000000FF;
103 wl1251_debug(DEBUG_BOOT, "ref_freq 0x%x", ref_freq);
104
105 wl1251_reg_write32(wl, PLL_CAL_TIME, 0x9);
106
107
108
109
110 wl1251_reg_write32(wl, CLK_BUF_TIME, 0x6);
111
112
113
114
115
116
117 tmp = ((scr_pad6 & 0x0000FF00) << 4) | 0x00004000;
118 wl1251_reg_write32(wl, ELP_CFG_MODE, tmp);
119
120
121 elp_cmd |= 0x00000040;
122 wl1251_reg_write32(wl, ELP_CMD, elp_cmd);
123
124
125
126 wl1251_reg_write32(wl, CFG_PLL_SYNC_CNT, 0x20);
127
128
129 init_data = wl1251_reg_read32(wl, CLK_REQ_TIME);
130
131
132
133
134
135 if (init_data > 0x21)
136 tmp = init_data - 0x21;
137 else
138 tmp = 0;
139 wl1251_reg_write32(wl, CLK_REQ_TIME, tmp);
140
141
142 wl1251_reg_write32(wl, 0x003058cc, 0x4B5);
143
144
145 wl1251_reg_write32(wl, 0x003058d4, 0x50);
146
147
148 wl1251_reg_write32(wl, 0x00305948, 0x11c001);
149
150
151
152
153
154 wl1251_reg_write32(wl, 0x003058f4, 0x1e);
155
156
157 tmp = LUT[ref_freq][LUT_PARAM_INTEGER_DIVIDER] | 0x00017000;
158 wl1251_reg_write32(wl, 0x00305840, tmp);
159
160
161
162
163 tmp = LUT[ref_freq][LUT_PARAM_FRACTIONAL_DIVIDER];
164 wl1251_reg_write32(wl, 0x00305844, tmp);
165
166
167 wl1251_reg_write32(wl, 0x00305848, 0x3039);
168
169
170
171
172
173
174 tmp = (LUT[ref_freq][LUT_PARAM_ATTN_BB] << 16) |
175 (LUT[ref_freq][LUT_PARAM_ALPHA_BB] << 12) | 0x1;
176 wl1251_reg_write32(wl, 0x00305854, tmp);
177
178
179
180
181
182 tmp = LUT[ref_freq][LUT_PARAM_STOP_TIME_BB] | 0x000A0000;
183 wl1251_reg_write32(wl, 0x00305858, tmp);
184
185
186
187
188
189
190 tmp = LUT[ref_freq][LUT_PARAM_BB_PLL_LOOP_FILTER] | 0x00000030;
191 wl1251_reg_write32(wl, 0x003058f8, tmp);
192
193
194
195
196
197
198
199 wl1251_reg_write32(wl, 0x003058f0, 0x29);
200
201
202 wl1251_reg_write32(wl, ELP_CMD, elp_cmd | 0x1);
203
204
205 udelay(2000);
206
207 return 0;
208}
209
210static void wl1251_boot_set_ecpu_ctrl(struct wl1251 *wl, u32 flag)
211{
212 u32 cpu_ctrl;
213
214
215 cpu_ctrl = wl1251_reg_read32(wl, ACX_REG_ECPU_CONTROL);
216
217
218 cpu_ctrl &= ~flag;
219 wl1251_reg_write32(wl, ACX_REG_ECPU_CONTROL, cpu_ctrl);
220}
221
222int wl1251_boot_run_firmware(struct wl1251 *wl)
223{
224 int loop, ret;
225 u32 chip_id, acx_intr;
226
227 wl1251_boot_set_ecpu_ctrl(wl, ECPU_CONTROL_HALT);
228
229 chip_id = wl1251_reg_read32(wl, CHIP_ID_B);
230
231 wl1251_debug(DEBUG_BOOT, "chip id after firmware boot: 0x%x", chip_id);
232
233 if (chip_id != wl->chip_id) {
234 wl1251_error("chip id doesn't match after firmware boot");
235 return -EIO;
236 }
237
238
239 loop = 0;
240 while (loop++ < INIT_LOOP) {
241 udelay(INIT_LOOP_DELAY);
242 acx_intr = wl1251_reg_read32(wl, ACX_REG_INTERRUPT_NO_CLEAR);
243
244 if (acx_intr == 0xffffffff) {
245 wl1251_error("error reading hardware complete "
246 "init indication");
247 return -EIO;
248 }
249
250 else if (acx_intr & WL1251_ACX_INTR_INIT_COMPLETE) {
251 wl1251_reg_write32(wl, ACX_REG_INTERRUPT_ACK,
252 WL1251_ACX_INTR_INIT_COMPLETE);
253 break;
254 }
255 }
256
257 if (loop > INIT_LOOP) {
258 wl1251_error("timeout waiting for the hardware to "
259 "complete initialization");
260 return -EIO;
261 }
262
263
264 wl->cmd_box_addr = wl1251_reg_read32(wl, REG_COMMAND_MAILBOX_PTR);
265
266
267 wl->event_box_addr = wl1251_reg_read32(wl, REG_EVENT_MAILBOX_PTR);
268
269
270 wl1251_set_partition(wl, WL1251_PART_WORK_MEM_START,
271 WL1251_PART_WORK_MEM_SIZE,
272 WL1251_PART_WORK_REG_START,
273 WL1251_PART_WORK_REG_SIZE);
274
275 wl1251_debug(DEBUG_MAILBOX, "cmd_box_addr 0x%x event_box_addr 0x%x",
276 wl->cmd_box_addr, wl->event_box_addr);
277
278 wl1251_acx_fw_version(wl, wl->fw_ver, sizeof(wl->fw_ver));
279
280
281
282
283
284
285
286 wl1251_enable_interrupts(wl);
287
288
289 wl->intr_mask = WL1251_ACX_INTR_RX0_DATA |
290 WL1251_ACX_INTR_RX1_DATA |
291 WL1251_ACX_INTR_TX_RESULT |
292 WL1251_ACX_INTR_EVENT_A |
293 WL1251_ACX_INTR_EVENT_B |
294 WL1251_ACX_INTR_INIT_COMPLETE;
295 wl1251_boot_target_enable_interrupts(wl);
296
297 wl->event_mask = SCAN_COMPLETE_EVENT_ID | BSS_LOSE_EVENT_ID |
298 SYNCHRONIZATION_TIMEOUT_EVENT_ID |
299 ROAMING_TRIGGER_LOW_RSSI_EVENT_ID |
300 ROAMING_TRIGGER_REGAINED_RSSI_EVENT_ID |
301 REGAINED_BSS_EVENT_ID | BT_PTA_SENSE_EVENT_ID |
302 BT_PTA_PREDICTION_EVENT_ID | JOIN_EVENT_COMPLETE_ID |
303 PS_REPORT_EVENT_ID;
304
305 ret = wl1251_event_unmask(wl);
306 if (ret < 0) {
307 wl1251_error("EVENT mask setting failed");
308 return ret;
309 }
310
311 wl1251_event_mbox_config(wl);
312
313
314 return 0;
315}
316
317static int wl1251_boot_upload_firmware(struct wl1251 *wl)
318{
319 int addr, chunk_num, partition_limit;
320 size_t fw_data_len, len;
321 u8 *p, *buf;
322
323
324
325 wl1251_debug(DEBUG_BOOT, "chip id before fw upload: 0x%x",
326 wl1251_reg_read32(wl, CHIP_ID_B));
327
328
329 fw_data_len = (wl->fw[4] << 24) | (wl->fw[5] << 16) |
330 (wl->fw[6] << 8) | (wl->fw[7]);
331
332 wl1251_debug(DEBUG_BOOT, "fw_data_len %zu chunk_size %d", fw_data_len,
333 CHUNK_SIZE);
334
335 if ((fw_data_len % 4) != 0) {
336 wl1251_error("firmware length not multiple of four");
337 return -EIO;
338 }
339
340 buf = kmalloc(CHUNK_SIZE, GFP_KERNEL);
341 if (!buf) {
342 wl1251_error("allocation for firmware upload chunk failed");
343 return -ENOMEM;
344 }
345
346 wl1251_set_partition(wl, WL1251_PART_DOWN_MEM_START,
347 WL1251_PART_DOWN_MEM_SIZE,
348 WL1251_PART_DOWN_REG_START,
349 WL1251_PART_DOWN_REG_SIZE);
350
351
352 chunk_num = 0;
353 partition_limit = WL1251_PART_DOWN_MEM_SIZE;
354
355 while (chunk_num < fw_data_len / CHUNK_SIZE) {
356
357 addr = WL1251_PART_DOWN_MEM_START +
358 (chunk_num + 2) * CHUNK_SIZE;
359 if (addr > partition_limit) {
360 addr = WL1251_PART_DOWN_MEM_START +
361 chunk_num * CHUNK_SIZE;
362 partition_limit = chunk_num * CHUNK_SIZE +
363 WL1251_PART_DOWN_MEM_SIZE;
364 wl1251_set_partition(wl,
365 addr,
366 WL1251_PART_DOWN_MEM_SIZE,
367 WL1251_PART_DOWN_REG_START,
368 WL1251_PART_DOWN_REG_SIZE);
369 }
370
371
372 addr = WL1251_PART_DOWN_MEM_START + chunk_num * CHUNK_SIZE;
373 p = wl->fw + FW_HDR_SIZE + chunk_num * CHUNK_SIZE;
374 wl1251_debug(DEBUG_BOOT, "uploading fw chunk 0x%p to 0x%x",
375 p, addr);
376
377
378 len = CHUNK_SIZE;
379 memcpy(buf, p, len);
380 wl1251_mem_write(wl, addr, buf, len);
381
382 chunk_num++;
383 }
384
385
386 addr = WL1251_PART_DOWN_MEM_START + chunk_num * CHUNK_SIZE;
387 p = wl->fw + FW_HDR_SIZE + chunk_num * CHUNK_SIZE;
388
389
390 len = fw_data_len % CHUNK_SIZE;
391 memcpy(buf, p, len);
392
393 wl1251_debug(DEBUG_BOOT, "uploading fw last chunk (%zu B) 0x%p to 0x%x",
394 len, p, addr);
395 wl1251_mem_write(wl, addr, buf, len);
396
397 kfree(buf);
398
399 return 0;
400}
401
402static int wl1251_boot_upload_nvs(struct wl1251 *wl)
403{
404 size_t nvs_len, nvs_bytes_written, burst_len;
405 int nvs_start, i;
406 u32 dest_addr, val;
407 u8 *nvs_ptr, *nvs;
408
409 nvs = wl->nvs;
410 if (nvs == NULL)
411 return -ENODEV;
412
413 nvs_ptr = nvs;
414
415 nvs_len = wl->nvs_len;
416 nvs_start = wl->fw_len;
417
418
419
420
421
422
423
424
425
426
427 while (nvs_ptr[0]) {
428 burst_len = nvs_ptr[0];
429 dest_addr = (nvs_ptr[1] & 0xfe) | ((u32)(nvs_ptr[2] << 8));
430
431
432 nvs_ptr += 3;
433
434 for (i = 0; i < burst_len; i++) {
435 val = (nvs_ptr[0] | (nvs_ptr[1] << 8)
436 | (nvs_ptr[2] << 16) | (nvs_ptr[3] << 24));
437
438 wl1251_debug(DEBUG_BOOT,
439 "nvs burst write 0x%x: 0x%x",
440 dest_addr, val);
441 wl1251_mem_write32(wl, dest_addr, val);
442
443 nvs_ptr += 4;
444 dest_addr += 4;
445 }
446 }
447
448
449
450
451
452 nvs_ptr += 7;
453 nvs_len -= nvs_ptr - nvs;
454 nvs_len = ALIGN(nvs_len, 4);
455
456
457 wl1251_set_partition(wl, nvs_start,
458 WL1251_PART_DOWN_MEM_SIZE,
459 WL1251_PART_DOWN_REG_START,
460 WL1251_PART_DOWN_REG_SIZE);
461
462
463 nvs_bytes_written = 0;
464 while (nvs_bytes_written < nvs_len) {
465 val = (nvs_ptr[0] | (nvs_ptr[1] << 8)
466 | (nvs_ptr[2] << 16) | (nvs_ptr[3] << 24));
467
468 wl1251_debug(DEBUG_BOOT,
469 "nvs write table 0x%x: 0x%x",
470 nvs_start, val);
471 wl1251_mem_write32(wl, nvs_start, val);
472
473 nvs_ptr += 4;
474 nvs_bytes_written += 4;
475 nvs_start += 4;
476 }
477
478 return 0;
479}
480
481int wl1251_boot(struct wl1251 *wl)
482{
483 int ret = 0, minor_minor_e2_ver;
484 u32 tmp, boot_data;
485
486
487 wl1251_reg_write32(wl, ACX_REG_ECPU_CONTROL, ECPU_CONTROL_HALT);
488
489 ret = wl1251_boot_soft_reset(wl);
490 if (ret < 0)
491 goto out;
492
493
494 if (wl->use_eeprom) {
495 wl1251_reg_write32(wl, ACX_REG_EE_START, START_EEPROM_MGR);
496
497 msleep(40);
498 wl1251_reg_write32(wl, ACX_EEPROMLESS_IND_REG, USE_EEPROM);
499 } else {
500 ret = wl1251_boot_upload_nvs(wl);
501 if (ret < 0)
502 goto out;
503
504
505
506 wl1251_reg_write32(wl, ACX_EEPROMLESS_IND_REG, wl->fw_len);
507 }
508
509
510 tmp = wl1251_reg_read32(wl, SCR_PAD2);
511
512
513 wl->boot_attr.radio_type = (tmp & 0x0000FF00) >> 8;
514 wl->boot_attr.major = (tmp & 0x00FF0000) >> 16;
515 tmp = wl1251_reg_read32(wl, SCR_PAD3);
516
517
518 wl->boot_attr.minor = (tmp & 0x00FF0000) >> 16;
519 minor_minor_e2_ver = (tmp & 0xFF000000) >> 24;
520
521 wl1251_debug(DEBUG_BOOT, "radioType 0x%x majorE2Ver 0x%x "
522 "minorE2Ver 0x%x minor_minor_e2_ver 0x%x",
523 wl->boot_attr.radio_type, wl->boot_attr.major,
524 wl->boot_attr.minor, minor_minor_e2_ver);
525
526 ret = wl1251_boot_init_seq(wl);
527 if (ret < 0)
528 goto out;
529
530
531 boot_data = wl1251_reg_read32(wl, ACX_REG_ECPU_CONTROL);
532
533 wl1251_debug(DEBUG_BOOT, "halt boot_data 0x%x", boot_data);
534
535
536
537
538 if ((boot_data & ECPU_CONTROL_HALT) == 0) {
539 wl1251_error("boot failed, ECPU_CONTROL_HALT not set");
540 ret = -EIO;
541 goto out;
542 }
543
544 ret = wl1251_boot_upload_firmware(wl);
545 if (ret < 0)
546 goto out;
547
548
549 ret = wl1251_boot_run_firmware(wl);
550 if (ret < 0)
551 goto out;
552
553out:
554 return ret;
555}
556