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22#ifndef __WLCORE_H__
23#define __WLCORE_H__
24
25#include <linux/platform_device.h>
26
27#include "wlcore_i.h"
28#include "event.h"
29#include "boot.h"
30
31
32#define WLCORE_MAX_TX_DESCRIPTORS 32
33
34
35
36
37
38#define WLCORE_NUM_MAC_ADDRESSES 3
39
40
41#define WLCORE_MAX_TXPWR 25
42
43
44struct wl1271_tx_hw_descr;
45enum wl_rx_buf_align;
46struct wl1271_rx_descriptor;
47
48struct wlcore_ops {
49 int (*setup)(struct wl1271 *wl);
50 int (*identify_chip)(struct wl1271 *wl);
51 int (*identify_fw)(struct wl1271 *wl);
52 int (*boot)(struct wl1271 *wl);
53 int (*plt_init)(struct wl1271 *wl);
54 int (*trigger_cmd)(struct wl1271 *wl, int cmd_box_addr,
55 void *buf, size_t len);
56 int (*ack_event)(struct wl1271 *wl);
57 int (*wait_for_event)(struct wl1271 *wl, enum wlcore_wait_event event,
58 bool *timeout);
59 int (*process_mailbox_events)(struct wl1271 *wl);
60 u32 (*calc_tx_blocks)(struct wl1271 *wl, u32 len, u32 spare_blks);
61 void (*set_tx_desc_blocks)(struct wl1271 *wl,
62 struct wl1271_tx_hw_descr *desc,
63 u32 blks, u32 spare_blks);
64 void (*set_tx_desc_data_len)(struct wl1271 *wl,
65 struct wl1271_tx_hw_descr *desc,
66 struct sk_buff *skb);
67 enum wl_rx_buf_align (*get_rx_buf_align)(struct wl1271 *wl,
68 u32 rx_desc);
69 int (*prepare_read)(struct wl1271 *wl, u32 rx_desc, u32 len);
70 u32 (*get_rx_packet_len)(struct wl1271 *wl, void *rx_data,
71 u32 data_len);
72 int (*tx_delayed_compl)(struct wl1271 *wl);
73 void (*tx_immediate_compl)(struct wl1271 *wl);
74 int (*hw_init)(struct wl1271 *wl);
75 int (*init_vif)(struct wl1271 *wl, struct wl12xx_vif *wlvif);
76 void (*convert_fw_status)(struct wl1271 *wl, void *raw_fw_status,
77 struct wl_fw_status *fw_status);
78 u32 (*sta_get_ap_rate_mask)(struct wl1271 *wl,
79 struct wl12xx_vif *wlvif);
80 int (*get_pg_ver)(struct wl1271 *wl, s8 *ver);
81 int (*get_mac)(struct wl1271 *wl);
82 void (*set_tx_desc_csum)(struct wl1271 *wl,
83 struct wl1271_tx_hw_descr *desc,
84 struct sk_buff *skb);
85 void (*set_rx_csum)(struct wl1271 *wl,
86 struct wl1271_rx_descriptor *desc,
87 struct sk_buff *skb);
88 u32 (*ap_get_mimo_wide_rate_mask)(struct wl1271 *wl,
89 struct wl12xx_vif *wlvif);
90 int (*debugfs_init)(struct wl1271 *wl, struct dentry *rootdir);
91 int (*handle_static_data)(struct wl1271 *wl,
92 struct wl1271_static_data *static_data);
93 int (*scan_start)(struct wl1271 *wl, struct wl12xx_vif *wlvif,
94 struct cfg80211_scan_request *req);
95 int (*scan_stop)(struct wl1271 *wl, struct wl12xx_vif *wlvif);
96 int (*sched_scan_start)(struct wl1271 *wl, struct wl12xx_vif *wlvif,
97 struct cfg80211_sched_scan_request *req,
98 struct ieee80211_scan_ies *ies);
99 void (*sched_scan_stop)(struct wl1271 *wl, struct wl12xx_vif *wlvif);
100 int (*get_spare_blocks)(struct wl1271 *wl, bool is_gem);
101 int (*set_key)(struct wl1271 *wl, enum set_key_cmd cmd,
102 struct ieee80211_vif *vif,
103 struct ieee80211_sta *sta,
104 struct ieee80211_key_conf *key_conf);
105 int (*channel_switch)(struct wl1271 *wl,
106 struct wl12xx_vif *wlvif,
107 struct ieee80211_channel_switch *ch_switch);
108 u32 (*pre_pkt_send)(struct wl1271 *wl, u32 buf_offset, u32 last_len);
109 void (*sta_rc_update)(struct wl1271 *wl, struct wl12xx_vif *wlvif,
110 struct ieee80211_sta *sta, u32 changed);
111 int (*set_peer_cap)(struct wl1271 *wl,
112 struct ieee80211_sta_ht_cap *ht_cap,
113 bool allow_ht_operation,
114 u32 rate_set, u8 hlid);
115 u32 (*convert_hwaddr)(struct wl1271 *wl, u32 hwaddr);
116 bool (*lnk_high_prio)(struct wl1271 *wl, u8 hlid,
117 struct wl1271_link *lnk);
118 bool (*lnk_low_prio)(struct wl1271 *wl, u8 hlid,
119 struct wl1271_link *lnk);
120 int (*smart_config_start)(struct wl1271 *wl, u32 group_bitmap);
121 int (*smart_config_stop)(struct wl1271 *wl);
122 int (*smart_config_set_group_key)(struct wl1271 *wl, u16 group_id,
123 u8 key_len, u8 *key);
124};
125
126enum wlcore_partitions {
127 PART_DOWN,
128 PART_WORK,
129 PART_BOOT,
130 PART_DRPW,
131 PART_TOP_PRCM_ELP_SOC,
132 PART_PHY_INIT,
133
134 PART_TABLE_LEN,
135};
136
137struct wlcore_partition {
138 u32 size;
139 u32 start;
140};
141
142struct wlcore_partition_set {
143 struct wlcore_partition mem;
144 struct wlcore_partition reg;
145 struct wlcore_partition mem2;
146 struct wlcore_partition mem3;
147};
148
149enum wlcore_registers {
150
151 REG_ECPU_CONTROL,
152 REG_INTERRUPT_NO_CLEAR,
153 REG_INTERRUPT_ACK,
154 REG_COMMAND_MAILBOX_PTR,
155 REG_EVENT_MAILBOX_PTR,
156 REG_INTERRUPT_TRIG,
157 REG_INTERRUPT_MASK,
158 REG_PC_ON_RECOVERY,
159 REG_CHIP_ID_B,
160 REG_CMD_MBOX_ADDRESS,
161
162
163 REG_SLV_MEM_DATA,
164 REG_SLV_REG_DATA,
165
166
167 REG_RAW_FW_STATUS_ADDR,
168
169 REG_TABLE_LEN,
170};
171
172struct wl1271_stats {
173 void *fw_stats;
174 unsigned long fw_stats_update;
175 size_t fw_stats_len;
176
177 unsigned int retry_count;
178 unsigned int excessive_retries;
179};
180
181struct wl1271 {
182 bool initialized;
183 struct ieee80211_hw *hw;
184 bool mac80211_registered;
185
186 struct device *dev;
187 struct platform_device *pdev;
188
189 void *if_priv;
190
191 struct wl1271_if_operations *if_ops;
192
193 int irq;
194
195 spinlock_t wl_lock;
196
197 enum wlcore_state state;
198 enum wl12xx_fw_type fw_type;
199 bool plt;
200 enum plt_mode plt_mode;
201 u8 fem_manuf;
202 u8 last_vif_count;
203 struct mutex mutex;
204
205 unsigned long flags;
206
207 struct wlcore_partition_set curr_part;
208
209 struct wl1271_chip chip;
210
211 int cmd_box_addr;
212
213 u8 *fw;
214 size_t fw_len;
215 void *nvs;
216 size_t nvs_len;
217
218 s8 hw_pg_ver;
219
220
221 u32 fuse_oui_addr;
222 u32 fuse_nic_addr;
223
224
225 struct mac_address addresses[WLCORE_NUM_MAC_ADDRESSES];
226 int channel;
227 u8 system_hlid;
228
229 unsigned long links_map[BITS_TO_LONGS(WLCORE_MAX_LINKS)];
230 unsigned long roles_map[BITS_TO_LONGS(WL12XX_MAX_ROLES)];
231 unsigned long roc_map[BITS_TO_LONGS(WL12XX_MAX_ROLES)];
232 unsigned long rate_policies_map[
233 BITS_TO_LONGS(WL12XX_MAX_RATE_POLICIES)];
234 unsigned long klv_templates_map[
235 BITS_TO_LONGS(WLCORE_MAX_KLV_TEMPLATES)];
236
237 u8 session_ids[WLCORE_MAX_LINKS];
238
239 struct list_head wlvif_list;
240
241 u8 sta_count;
242 u8 ap_count;
243
244 struct wl1271_acx_mem_map *target_mem_map;
245
246
247 u32 tx_blocks_freed;
248 u32 tx_blocks_available;
249 u32 tx_allocated_blocks;
250 u32 tx_results_count;
251
252
253 u32 tx_pkts_freed[NUM_TX_QUEUES];
254 u32 tx_allocated_pkts[NUM_TX_QUEUES];
255
256
257 u32 tx_packets_count;
258
259
260 s64 time_offset;
261
262
263 int tx_queue_count[NUM_TX_QUEUES];
264 unsigned long queue_stop_reasons[
265 NUM_TX_QUEUES * WLCORE_NUM_MAC_ADDRESSES];
266
267
268 struct sk_buff_head deferred_rx_queue;
269
270
271 struct sk_buff_head deferred_tx_queue;
272
273 struct work_struct tx_work;
274 struct workqueue_struct *freezable_wq;
275
276
277 unsigned long tx_frames_map[BITS_TO_LONGS(WLCORE_MAX_TX_DESCRIPTORS)];
278 struct sk_buff *tx_frames[WLCORE_MAX_TX_DESCRIPTORS];
279 int tx_frames_cnt;
280
281
282 u32 rx_counter;
283
284
285 u8 *aggr_buf;
286 u32 aggr_buf_size;
287
288
289 struct sk_buff *dummy_packet;
290
291
292 struct work_struct netstack_work;
293
294
295 u8 *fwlog;
296
297
298 ssize_t fwlog_size;
299
300
301 u32 fwlog_end;
302
303
304 u32 fw_mem_block_size;
305
306
307 wait_queue_head_t fwlog_waitq;
308
309
310 struct work_struct recovery_work;
311 bool watchdog_recovery;
312
313
314 u32 reg_ch_conf_last[2];
315
316 u32 reg_ch_conf_pending[2];
317
318
319 void *mbox;
320
321
322 u32 event_mask;
323
324 u32 ap_event_mask;
325
326
327 u32 mbox_size;
328 u32 mbox_ptr[2];
329
330
331 struct wl12xx_vif *scan_wlvif;
332 struct wl1271_scan scan;
333 struct delayed_work scan_complete_work;
334
335 struct ieee80211_vif *roc_vif;
336 struct delayed_work roc_complete_work;
337
338 struct wl12xx_vif *sched_vif;
339
340
341 enum ieee80211_band band;
342
343 struct completion *elp_compl;
344 struct delayed_work elp_work;
345
346
347 int power_level;
348
349 struct wl1271_stats stats;
350
351 __le32 *buffer_32;
352 u32 buffer_cmd;
353 u32 buffer_busyword[WL1271_BUSY_WORD_CNT];
354
355 void *raw_fw_status;
356 struct wl_fw_status *fw_status;
357 struct wl1271_tx_hw_res_if *tx_res_if;
358
359
360 struct wlcore_conf conf;
361
362 bool sg_enabled;
363
364 bool enable_11a;
365
366 int recovery_count;
367
368
369 s8 noise;
370
371
372 struct ieee80211_supported_band bands[WLCORE_NUM_BANDS];
373
374
375
376
377
378 bool wow_enabled;
379 bool irq_wake_enabled;
380
381
382
383
384
385 struct wl1271_link links[WLCORE_MAX_LINKS];
386
387
388 int active_link_count;
389
390
391 unsigned long fw_fast_lnk_map;
392
393
394 unsigned long ap_fw_ps_map;
395
396
397 unsigned long ap_ps_map;
398
399
400 unsigned int quirks;
401
402
403 unsigned int platform_quirks;
404
405
406 int ba_rx_session_count;
407
408
409 int ba_rx_session_count_max;
410
411
412 int active_sta_count;
413
414
415 bool ofdm_only_ap;
416
417
418 struct wl12xx_vif *last_wlvif;
419
420
421 struct delayed_work tx_watchdog_work;
422
423 struct wlcore_ops *ops;
424
425 const struct wlcore_partition_set *ptable;
426
427 const int *rtable;
428
429 const char *plt_fw_name;
430 const char *sr_fw_name;
431 const char *mr_fw_name;
432
433 u8 scan_templ_id_2_4;
434 u8 scan_templ_id_5;
435 u8 sched_scan_templ_id_2_4;
436 u8 sched_scan_templ_id_5;
437 u8 max_channels_5;
438
439
440 void *priv;
441
442
443 u32 num_tx_desc;
444
445 u32 num_rx_desc;
446
447 u8 num_links;
448
449 u8 max_ap_stations;
450
451
452 const u8 **band_rate_to_idx;
453
454
455 u8 hw_tx_rate_tbl_size;
456
457
458 u8 hw_min_ht_rate;
459
460
461 struct ieee80211_sta_ht_cap ht_cap[WLCORE_NUM_BANDS];
462
463
464 size_t fw_status_len;
465 size_t fw_status_priv_len;
466
467
468 unsigned long rx_filter_enabled[BITS_TO_LONGS(WL1271_MAX_RX_FILTERS)];
469
470
471 size_t static_data_priv_len;
472
473
474 enum nl80211_channel_type channel_type;
475
476
477 struct mutex flush_mutex;
478
479
480 int sleep_auth;
481
482
483 int num_mac_addr;
484
485
486 unsigned int min_sr_fw_ver[NUM_FW_VER];
487
488
489 unsigned int min_mr_fw_ver[NUM_FW_VER];
490
491 struct completion nvs_loading_complete;
492
493
494 const struct ieee80211_iface_combination *iface_combinations;
495 u8 n_iface_combinations;
496};
497
498int wlcore_probe(struct wl1271 *wl, struct platform_device *pdev);
499int wlcore_remove(struct platform_device *pdev);
500struct ieee80211_hw *wlcore_alloc_hw(size_t priv_size, u32 aggr_buf_size,
501 u32 mbox_size);
502int wlcore_free_hw(struct wl1271 *wl);
503int wlcore_set_key(struct wl1271 *wl, enum set_key_cmd cmd,
504 struct ieee80211_vif *vif,
505 struct ieee80211_sta *sta,
506 struct ieee80211_key_conf *key_conf);
507void wlcore_regdomain_config(struct wl1271 *wl);
508void wlcore_update_inconn_sta(struct wl1271 *wl, struct wl12xx_vif *wlvif,
509 struct wl1271_station *wl_sta, bool in_conn);
510
511static inline void
512wlcore_set_ht_cap(struct wl1271 *wl, enum ieee80211_band band,
513 struct ieee80211_sta_ht_cap *ht_cap)
514{
515 memcpy(&wl->ht_cap[band], ht_cap, sizeof(*ht_cap));
516}
517
518
519#define WLCORE_FW_VER_IGNORE -1
520
521static inline void
522wlcore_set_min_fw_ver(struct wl1271 *wl, unsigned int chip,
523 unsigned int iftype_sr, unsigned int major_sr,
524 unsigned int subtype_sr, unsigned int minor_sr,
525 unsigned int iftype_mr, unsigned int major_mr,
526 unsigned int subtype_mr, unsigned int minor_mr)
527{
528 wl->min_sr_fw_ver[FW_VER_CHIP] = chip;
529 wl->min_sr_fw_ver[FW_VER_IF_TYPE] = iftype_sr;
530 wl->min_sr_fw_ver[FW_VER_MAJOR] = major_sr;
531 wl->min_sr_fw_ver[FW_VER_SUBTYPE] = subtype_sr;
532 wl->min_sr_fw_ver[FW_VER_MINOR] = minor_sr;
533
534 wl->min_mr_fw_ver[FW_VER_CHIP] = chip;
535 wl->min_mr_fw_ver[FW_VER_IF_TYPE] = iftype_mr;
536 wl->min_mr_fw_ver[FW_VER_MAJOR] = major_mr;
537 wl->min_mr_fw_ver[FW_VER_SUBTYPE] = subtype_mr;
538 wl->min_mr_fw_ver[FW_VER_MINOR] = minor_mr;
539}
540
541
542#define CHUNK_SIZE 16384
543
544
545
546
547#define WLCORE_QUIRK_END_OF_TRANSACTION BIT(0)
548
549
550#define WLCORE_QUIRK_START_STA_FAILS BIT(1)
551
552
553#define WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN BIT(2)
554
555
556#define WLCORE_QUIRK_RX_BLOCKSIZE_ALIGN BIT(3)
557
558
559#define WLCORE_QUIRK_FWLOG_NOT_IMPLEMENTED BIT(4)
560
561
562#define WLCORE_QUIRK_LEGACY_NVS BIT(5)
563
564
565#define WLCORE_QUIRK_TX_PAD_LAST_FRAME BIT(7)
566
567
568#define WLCORE_QUIRK_TKIP_HEADER_SPACE BIT(8)
569
570
571#define WLCORE_QUIRK_NO_SCHED_SCAN_WHILE_CONN BIT(9)
572
573
574#define WLCORE_QUIRK_DUAL_PROBE_TMPL BIT(10)
575
576
577#define WLCORE_QUIRK_REGDOMAIN_CONF BIT(11)
578
579
580#define WLCORE_QUIRK_AP_ZERO_SESSION_ID BIT(12)
581
582
583#define HW_ACCESS_ELP_CTRL_REG 0x1FFFC
584
585
586#define ELPCTRL_WAKE_UP 0x1
587#define ELPCTRL_WAKE_UP_WLAN_READY 0x5
588#define ELPCTRL_SLEEP 0x0
589
590#define ELPCTRL_WLAN_READY 0x2
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605#define INTR_TRIG_TX_PROC0 BIT(2)
606
607
608
609
610
611
612#define INTR_TRIG_RX_PROC0 BIT(3)
613
614#define INTR_TRIG_DEBUG_ACK BIT(4)
615
616#define INTR_TRIG_STATE_CHANGED BIT(5)
617
618
619
620
621
622
623
624
625#define INTR_TRIG_RX_PROC1 BIT(17)
626
627
628
629
630
631
632#define INTR_TRIG_TX_PROC1 BIT(18)
633
634#define ACX_SLV_SOFT_RESET_BIT BIT(1)
635#define SOFT_RESET_MAX_TIME 1000000
636#define SOFT_RESET_STALL_TIME 1000
637
638#define ECPU_CONTROL_HALT 0x00000101
639
640#define WELP_ARM_COMMAND_VAL 0x4
641
642#endif
643