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20#ifndef _BEISCSI_MAIN_
21#define _BEISCSI_MAIN_
22
23#include <linux/kernel.h>
24#include <linux/pci.h>
25#include <linux/if_ether.h>
26#include <linux/in.h>
27#include <linux/ctype.h>
28#include <linux/module.h>
29#include <linux/aer.h>
30#include <scsi/scsi.h>
31#include <scsi/scsi_cmnd.h>
32#include <scsi/scsi_device.h>
33#include <scsi/scsi_host.h>
34#include <scsi/iscsi_proto.h>
35#include <scsi/libiscsi.h>
36#include <scsi/scsi_transport_iscsi.h>
37
38#define DRV_NAME "be2iscsi"
39#define BUILD_STR "10.4.114.0"
40#define BE_NAME "Emulex OneConnect" \
41 "Open-iSCSI Driver version" BUILD_STR
42#define DRV_DESC BE_NAME " " "Driver"
43
44#define BE_VENDOR_ID 0x19A2
45#define ELX_VENDOR_ID 0x10DF
46
47#define BE_DEVICE_ID1 0x212
48#define OC_DEVICE_ID1 0x702
49#define OC_DEVICE_ID2 0x703
50
51
52#define BE_DEVICE_ID2 0x222
53#define OC_DEVICE_ID3 0x712
54
55
56#define OC_SKH_ID1 0x722
57
58#define BE2_IO_DEPTH 1024
59#define BE2_MAX_SESSIONS 256
60#define BE2_CMDS_PER_CXN 128
61#define BE2_TMFS 16
62#define BE2_NOPOUT_REQ 16
63#define BE2_SGE 32
64#define BE2_DEFPDU_HDR_SZ 64
65#define BE2_DEFPDU_DATA_SZ 8192
66
67#define MAX_CPUS 64
68#define BEISCSI_MAX_NUM_CPUS 7
69
70#define BEISCSI_VER_STRLEN 32
71
72#define BEISCSI_SGLIST_ELEMENTS 30
73
74#define BEISCSI_CMD_PER_LUN 128
75#define BEISCSI_MAX_SECTORS 1024
76#define BEISCSI_TEMPLATE_HDR_PER_CXN_SIZE 128
77
78#define BEISCSI_MAX_CMD_LEN 16
79#define BEISCSI_NUM_MAX_LUN 256
80#define BEISCSI_NUM_DEVICES_SUPPORTED 0x01
81#define BEISCSI_MAX_FRAGS_INIT 192
82#define BE_NUM_MSIX_ENTRIES 1
83
84#define MPU_EP_CONTROL 0
85#define MPU_EP_SEMAPHORE 0xac
86#define BE2_SOFT_RESET 0x5c
87#define BE2_PCI_ONLINE0 0xb0
88#define BE2_PCI_ONLINE1 0xb4
89#define BE2_SET_RESET 0x80
90#define BE2_MPU_IRAM_ONLINE 0x00000080
91
92#define BE_SENSE_INFO_SIZE 258
93#define BE_ISCSI_PDU_HEADER_SIZE 64
94#define BE_MIN_MEM_SIZE 16384
95#define MAX_CMD_SZ 65536
96#define IIOC_SCSI_DATA 0x05
97
98#define INVALID_SESS_HANDLE 0xFFFFFFFF
99
100
101
102
103#define BE_ADAPTER_LINK_UP 0x001
104#define BE_ADAPTER_LINK_DOWN 0x002
105#define BE_ADAPTER_PCI_ERR 0x004
106#define BE_ADAPTER_STATE_SHUTDOWN 0x008
107#define BE_ADAPTER_CHECK_BOOT 0x010
108
109
110#define BEISCSI_CLEAN_UNLOAD 0x01
111#define BEISCSI_EEH_UNLOAD 0x02
112
113
114
115
116
117#define HWI_GET_ASYNC_PDU_CTX(phwi, ulp_num) \
118 (phwi->phwi_ctxt->pasync_ctx[ulp_num])
119
120
121#define PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET 0xfc
122
123
124
125
126
127
128
129#define MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK (1 << 29)
130
131
132#define CEV_ISR0_OFFSET 0xC18
133#define CEV_ISR_SIZE 4
134
135
136
137
138
139
140#define DB_TXULP0_OFFSET 0x40
141#define DB_RXULP0_OFFSET 0xA0
142
143#define DB_EQ_OFFSET DB_CQ_OFFSET
144#define DB_EQ_RING_ID_LOW_MASK 0x1FF
145
146#define DB_EQ_CLR_SHIFT (9)
147
148#define DB_EQ_EVNT_SHIFT (10)
149
150#define DB_EQ_RING_ID_HIGH_MASK 0x1F
151#define DB_EQ_HIGH_SET_SHIFT 11
152#define DB_EQ_HIGH_FEILD_SHIFT 9
153
154#define DB_EQ_NUM_POPPED_SHIFT (16)
155
156#define DB_EQ_REARM_SHIFT (29)
157
158
159#define DB_CQ_OFFSET 0x120
160#define DB_CQ_RING_ID_LOW_MASK 0x3FF
161
162#define DB_CQ_RING_ID_HIGH_MASK 0x1F
163#define DB_CQ_HIGH_SET_SHIFT 11
164#define DB_CQ_HIGH_FEILD_SHIFT 10
165
166
167#define DB_CQ_NUM_POPPED_SHIFT (16)
168
169#define DB_CQ_REARM_SHIFT (29)
170
171#define GET_HWI_CONTROLLER_WS(pc) (pc->phwi_ctrlr)
172#define HWI_GET_DEF_BUFQ_ID(pc, ulp_num) (((struct hwi_controller *)\
173 (GET_HWI_CONTROLLER_WS(pc)))->default_pdu_data[ulp_num].id)
174#define HWI_GET_DEF_HDRQ_ID(pc, ulp_num) (((struct hwi_controller *)\
175 (GET_HWI_CONTROLLER_WS(pc)))->default_pdu_hdr[ulp_num].id)
176
177#define PAGES_REQUIRED(x) \
178 ((x < PAGE_SIZE) ? 1 : ((x + PAGE_SIZE - 1) / PAGE_SIZE))
179
180#define BEISCSI_MSI_NAME 20
181
182#define MEM_DESCR_OFFSET 8
183#define BEISCSI_DEFQ_HDR 1
184#define BEISCSI_DEFQ_DATA 0
185enum be_mem_enum {
186 HWI_MEM_ADDN_CONTEXT,
187 HWI_MEM_WRB,
188 HWI_MEM_WRBH,
189 HWI_MEM_SGLH,
190 HWI_MEM_SGE,
191 HWI_MEM_TEMPLATE_HDR_ULP0,
192 HWI_MEM_ASYNC_HEADER_BUF_ULP0,
193 HWI_MEM_ASYNC_DATA_BUF_ULP0,
194 HWI_MEM_ASYNC_HEADER_RING_ULP0,
195 HWI_MEM_ASYNC_DATA_RING_ULP0,
196 HWI_MEM_ASYNC_HEADER_HANDLE_ULP0,
197 HWI_MEM_ASYNC_DATA_HANDLE_ULP0,
198 HWI_MEM_ASYNC_PDU_CONTEXT_ULP0,
199 HWI_MEM_TEMPLATE_HDR_ULP1,
200 HWI_MEM_ASYNC_HEADER_BUF_ULP1,
201 HWI_MEM_ASYNC_DATA_BUF_ULP1,
202 HWI_MEM_ASYNC_HEADER_RING_ULP1,
203 HWI_MEM_ASYNC_DATA_RING_ULP1,
204 HWI_MEM_ASYNC_HEADER_HANDLE_ULP1,
205 HWI_MEM_ASYNC_DATA_HANDLE_ULP1,
206 HWI_MEM_ASYNC_PDU_CONTEXT_ULP1,
207 ISCSI_MEM_GLOBAL_HEADER,
208 SE_MEM_MAX
209};
210
211struct be_bus_address32 {
212 unsigned int address_lo;
213 unsigned int address_hi;
214};
215
216struct be_bus_address64 {
217 unsigned long long address;
218};
219
220struct be_bus_address {
221 union {
222 struct be_bus_address32 a32;
223 struct be_bus_address64 a64;
224 } u;
225};
226
227struct mem_array {
228 struct be_bus_address bus_address;
229 void *virtual_address;
230 unsigned int size;
231};
232
233struct be_mem_descriptor {
234 unsigned int index;
235 unsigned int category;
236 unsigned int num_elements;
237
238
239 unsigned int alignment_mask;
240 unsigned int size_in_bytes;
241 struct mem_array *mem_array;
242};
243
244struct sgl_handle {
245 unsigned int sgl_index;
246 unsigned int type;
247 unsigned int cid;
248 struct iscsi_task *task;
249 struct iscsi_sge *pfrag;
250};
251
252struct hba_parameters {
253 unsigned int ios_per_ctrl;
254 unsigned int cxns_per_ctrl;
255 unsigned int asyncpdus_per_ctrl;
256 unsigned int icds_per_ctrl;
257 unsigned int num_sge_per_io;
258 unsigned int defpdu_hdr_sz;
259 unsigned int defpdu_data_sz;
260 unsigned int num_cq_entries;
261 unsigned int num_eq_entries;
262 unsigned int wrbs_per_cxn;
263 unsigned int crashmode;
264 unsigned int hba_num;
265
266 unsigned int mgmt_ws_sz;
267 unsigned int hwi_ws_sz;
268
269 unsigned int eto;
270 unsigned int ldto;
271
272 unsigned int dbg_flags;
273 unsigned int num_cxn;
274
275 unsigned int eq_timer;
276
277
278
279
280 unsigned int num_mcc_pages;
281 unsigned int num_mcc_cq_pages;
282 unsigned int num_cq_pages;
283 unsigned int num_eq_pages;
284
285 unsigned int num_async_pdu_buf_pages;
286 unsigned int num_async_pdu_buf_sgl_pages;
287 unsigned int num_async_pdu_buf_cq_pages;
288
289 unsigned int num_async_pdu_hdr_pages;
290 unsigned int num_async_pdu_hdr_sgl_pages;
291 unsigned int num_async_pdu_hdr_cq_pages;
292
293 unsigned int num_sge;
294};
295
296struct invalidate_command_table {
297 unsigned short icd;
298 unsigned short cid;
299} __packed;
300
301#define BEISCSI_GET_ULP_FROM_CRI(phwi_ctrlr, cri) \
302 (phwi_ctrlr->wrb_context[cri].ulp_num)
303struct hwi_wrb_context {
304 struct list_head wrb_handle_list;
305 struct list_head wrb_handle_drvr_list;
306 struct wrb_handle **pwrb_handle_base;
307 struct wrb_handle **pwrb_handle_basestd;
308 struct iscsi_wrb *plast_wrb;
309 unsigned short alloc_index;
310 unsigned short free_index;
311 unsigned short wrb_handles_available;
312 unsigned short cid;
313 uint8_t ulp_num;
314 uint16_t register_set;
315 uint16_t doorbell_format;
316 uint32_t doorbell_offset;
317};
318
319struct ulp_cid_info {
320 unsigned short *cid_array;
321 unsigned short avlbl_cids;
322 unsigned short cid_alloc;
323 unsigned short cid_free;
324};
325
326#include "be.h"
327#define chip_be2(phba) (phba->generation == BE_GEN2)
328#define chip_be3_r(phba) (phba->generation == BE_GEN3)
329#define is_chip_be2_be3r(phba) (chip_be3_r(phba) || (chip_be2(phba)))
330
331#define BEISCSI_ULP0 0
332#define BEISCSI_ULP1 1
333#define BEISCSI_ULP_COUNT 2
334#define BEISCSI_ULP0_LOADED 0x01
335#define BEISCSI_ULP1_LOADED 0x02
336
337#define BEISCSI_ULP_AVLBL_CID(phba, ulp_num) \
338 (((struct ulp_cid_info *)phba->cid_array_info[ulp_num])->avlbl_cids)
339#define BEISCSI_ULP0_AVLBL_CID(phba) \
340 BEISCSI_ULP_AVLBL_CID(phba, BEISCSI_ULP0)
341#define BEISCSI_ULP1_AVLBL_CID(phba) \
342 BEISCSI_ULP_AVLBL_CID(phba, BEISCSI_ULP1)
343
344struct beiscsi_hba {
345 struct hba_parameters params;
346 struct hwi_controller *phwi_ctrlr;
347 unsigned int mem_req[SE_MEM_MAX];
348
349 u8 __iomem *csr_va;
350 u8 __iomem *db_va;
351 u8 __iomem *pci_va;
352 struct be_bus_address csr_pa;
353 struct be_bus_address db_pa;
354 struct be_bus_address pci_pa;
355
356 struct pci_dev *pcidev;
357 unsigned short asic_revision;
358 unsigned int num_cpus;
359 unsigned int nxt_cqid;
360 struct msix_entry msix_entries[MAX_CPUS];
361 char *msi_name[MAX_CPUS];
362 bool msix_enabled;
363 struct be_mem_descriptor *init_mem;
364
365 unsigned short io_sgl_alloc_index;
366 unsigned short io_sgl_free_index;
367 unsigned short io_sgl_hndl_avbl;
368 struct sgl_handle **io_sgl_hndl_base;
369 struct sgl_handle **sgl_hndl_array;
370
371 unsigned short eh_sgl_alloc_index;
372 unsigned short eh_sgl_free_index;
373 unsigned short eh_sgl_hndl_avbl;
374 struct sgl_handle **eh_sgl_hndl_base;
375 spinlock_t io_sgl_lock;
376 spinlock_t mgmt_sgl_lock;
377 spinlock_t isr_lock;
378 spinlock_t async_pdu_lock;
379 unsigned int age;
380 struct list_head hba_queue;
381#define BE_MAX_SESSION 2048
382#define BE_SET_CID_TO_CRI(cri_index, cid) \
383 (phba->cid_to_cri_map[cid] = cri_index)
384#define BE_GET_CRI_FROM_CID(cid) (phba->cid_to_cri_map[cid])
385 unsigned short cid_to_cri_map[BE_MAX_SESSION];
386 struct ulp_cid_info *cid_array_info[BEISCSI_ULP_COUNT];
387 struct iscsi_endpoint **ep_array;
388 struct beiscsi_conn **conn_table;
389 struct iscsi_boot_kset *boot_kset;
390 struct Scsi_Host *shost;
391 struct iscsi_iface *ipv4_iface;
392 struct iscsi_iface *ipv6_iface;
393 struct {
394
395
396
397
398 unsigned int phys_port;
399 unsigned int eqid_count;
400 unsigned int cqid_count;
401 unsigned int iscsi_cid_start[BEISCSI_ULP_COUNT];
402#define BEISCSI_GET_CID_COUNT(phba, ulp_num) \
403 (phba->fw_config.iscsi_cid_count[ulp_num])
404 unsigned int iscsi_cid_count[BEISCSI_ULP_COUNT];
405 unsigned int iscsi_icd_count[BEISCSI_ULP_COUNT];
406 unsigned int iscsi_icd_start[BEISCSI_ULP_COUNT];
407 unsigned int iscsi_chain_start[BEISCSI_ULP_COUNT];
408 unsigned int iscsi_chain_count[BEISCSI_ULP_COUNT];
409
410 unsigned short iscsi_features;
411 uint16_t dual_ulp_aware;
412 unsigned long ulp_supported;
413 } fw_config;
414
415 unsigned int state;
416 bool fw_timeout;
417 bool ue_detected;
418 struct delayed_work beiscsi_hw_check_task;
419
420 bool mac_addr_set;
421 u8 mac_address[ETH_ALEN];
422 char fw_ver_str[BEISCSI_VER_STRLEN];
423 char wq_name[20];
424 struct workqueue_struct *wq;
425 struct be_ctrl_info ctrl;
426 unsigned int generation;
427 unsigned int interface_handle;
428 struct mgmt_session_info boot_sess;
429 struct invalidate_command_table inv_tbl[128];
430
431 struct be_aic_obj aic_obj[MAX_CPUS];
432 unsigned int attr_log_enable;
433 int (*iotask_fn)(struct iscsi_task *,
434 struct scatterlist *sg,
435 uint32_t num_sg, uint32_t xferlen,
436 uint32_t writedir);
437};
438
439struct beiscsi_session {
440 struct pci_pool *bhs_pool;
441};
442
443
444
445
446struct beiscsi_conn {
447 struct iscsi_conn *conn;
448 struct beiscsi_hba *phba;
449 u32 exp_statsn;
450 u32 doorbell_offset;
451 u32 beiscsi_conn_cid;
452 struct beiscsi_endpoint *ep;
453 unsigned short login_in_progress;
454 struct wrb_handle *plogin_wrb_handle;
455 struct sgl_handle *plogin_sgl_handle;
456 struct beiscsi_session *beiscsi_sess;
457 struct iscsi_task *task;
458};
459
460
461struct pdu_data_out {
462 u32 dw[12];
463};
464
465
466
467
468struct amap_pdu_data_out {
469 u8 opcode[6];
470 u8 rsvd0[2];
471 u8 rsvd1[7];
472 u8 final_bit;
473 u8 rsvd2[16];
474 u8 ahs_length[8];
475 u8 data_len_hi[8];
476 u8 data_len_lo[16];
477 u8 lun[64];
478 u8 itt[32];
479 u8 ttt[32];
480 u8 rsvd3[32];
481 u8 exp_stat_sn[32];
482 u8 rsvd4[32];
483 u8 data_sn[32];
484 u8 buffer_offset[32];
485 u8 rsvd5[32];
486};
487
488struct be_cmd_bhs {
489 struct iscsi_scsi_req iscsi_hdr;
490 unsigned char pad1[16];
491 struct pdu_data_out iscsi_data_pdu;
492 unsigned char pad2[BE_SENSE_INFO_SIZE -
493 sizeof(struct pdu_data_out)];
494};
495
496struct beiscsi_io_task {
497 struct wrb_handle *pwrb_handle;
498 struct sgl_handle *psgl_handle;
499 struct beiscsi_conn *conn;
500 struct scsi_cmnd *scsi_cmnd;
501 unsigned int cmd_sn;
502 unsigned int flags;
503 unsigned short cid;
504 unsigned short header_len;
505 itt_t libiscsi_itt;
506 struct be_cmd_bhs *cmd_bhs;
507 struct be_bus_address bhs_pa;
508 unsigned short bhs_len;
509 dma_addr_t mtask_addr;
510 uint32_t mtask_data_count;
511 uint8_t wrb_type;
512};
513
514struct be_nonio_bhs {
515 struct iscsi_hdr iscsi_hdr;
516 unsigned char pad1[16];
517 struct pdu_data_out iscsi_data_pdu;
518 unsigned char pad2[BE_SENSE_INFO_SIZE -
519 sizeof(struct pdu_data_out)];
520};
521
522struct be_status_bhs {
523 struct iscsi_scsi_req iscsi_hdr;
524 unsigned char pad1[16];
525
526
527
528
529 unsigned char sense_info[BE_SENSE_INFO_SIZE];
530};
531
532struct iscsi_sge {
533 u32 dw[4];
534};
535
536
537
538
539
540struct amap_iscsi_sge {
541 u8 addr_hi[32];
542 u8 addr_lo[32];
543 u8 sge_offset[22];
544 u8 rsvd0[9];
545 u8 last_sge;
546 u8 len[17];
547 u8 rsvd1[15];
548};
549
550struct beiscsi_offload_params {
551 u32 dw[6];
552};
553
554#define OFFLD_PARAMS_ERL 0x00000003
555#define OFFLD_PARAMS_DDE 0x00000004
556#define OFFLD_PARAMS_HDE 0x00000008
557#define OFFLD_PARAMS_IR2T 0x00000010
558#define OFFLD_PARAMS_IMD 0x00000020
559#define OFFLD_PARAMS_DATA_SEQ_INORDER 0x00000040
560#define OFFLD_PARAMS_PDU_SEQ_INORDER 0x00000080
561#define OFFLD_PARAMS_MAX_R2T 0x00FFFF00
562
563
564
565
566
567struct amap_beiscsi_offload_params {
568 u8 max_burst_length[32];
569 u8 max_send_data_segment_length[32];
570 u8 first_burst_length[32];
571 u8 erl[2];
572 u8 dde[1];
573 u8 hde[1];
574 u8 ir2t[1];
575 u8 imd[1];
576 u8 data_seq_inorder[1];
577 u8 pdu_seq_inorder[1];
578 u8 max_r2t[16];
579 u8 pad[8];
580 u8 exp_statsn[32];
581 u8 max_recv_data_segment_length[32];
582};
583
584
585
586
587struct async_pdu_handle {
588 struct list_head link;
589 struct be_bus_address pa;
590 void *pbuffer;
591 unsigned int consumed;
592 unsigned char index;
593 unsigned char is_header;
594 unsigned short cri;
595 unsigned long buffer_len;
596};
597
598struct hwi_async_entry {
599 struct {
600 unsigned char hdr_received;
601 unsigned char hdr_len;
602 unsigned short bytes_received;
603 unsigned int bytes_needed;
604 struct list_head list;
605 } wait_queue;
606
607 struct list_head header_busy_list;
608 struct list_head data_busy_list;
609};
610
611struct hwi_async_pdu_context {
612 struct {
613 struct be_bus_address pa_base;
614 void *va_base;
615 void *ring_base;
616 struct async_pdu_handle *handle_base;
617
618 unsigned int host_write_ptr;
619 unsigned int ep_read_ptr;
620 unsigned int writables;
621
622 unsigned int free_entries;
623 unsigned int busy_entries;
624
625 struct list_head free_list;
626 } async_header;
627
628 struct {
629 struct be_bus_address pa_base;
630 void *va_base;
631 void *ring_base;
632 struct async_pdu_handle *handle_base;
633
634 unsigned int host_write_ptr;
635 unsigned int ep_read_ptr;
636 unsigned int writables;
637
638 unsigned int free_entries;
639 unsigned int busy_entries;
640 struct list_head free_list;
641 } async_data;
642
643 unsigned int buffer_size;
644 unsigned int num_entries;
645#define BE_GET_ASYNC_CRI_FROM_CID(cid) (pasync_ctx->cid_to_async_cri_map[cid])
646 unsigned short cid_to_async_cri_map[BE_MAX_SESSION];
647
648
649
650
651 struct hwi_async_entry *async_entry;
652};
653
654#define PDUCQE_CODE_MASK 0x0000003F
655#define PDUCQE_DPL_MASK 0xFFFF0000
656#define PDUCQE_INDEX_MASK 0x0000FFFF
657
658struct i_t_dpdu_cqe {
659 u32 dw[4];
660} __packed;
661
662
663
664
665
666struct amap_i_t_dpdu_cqe {
667 u8 db_addr_hi[32];
668 u8 db_addr_lo[32];
669 u8 code[6];
670 u8 cid[10];
671 u8 dpl[16];
672 u8 index[16];
673 u8 num_cons[10];
674 u8 rsvd0[4];
675 u8 final;
676 u8 valid;
677} __packed;
678
679struct amap_i_t_dpdu_cqe_v2 {
680 u8 db_addr_hi[32];
681 u8 db_addr_lo[32];
682 u8 code[6];
683 u8 num_cons;
684 u8 rsvd0[8];
685 u8 dpl[17];
686 u8 index[16];
687 u8 cid[13];
688 u8 rsvd1;
689 u8 final;
690 u8 valid;
691} __packed;
692
693#define CQE_VALID_MASK 0x80000000
694#define CQE_CODE_MASK 0x0000003F
695#define CQE_CID_MASK 0x0000FFC0
696
697#define EQE_VALID_MASK 0x00000001
698#define EQE_MAJORCODE_MASK 0x0000000E
699#define EQE_RESID_MASK 0xFFFF0000
700
701struct be_eq_entry {
702 u32 dw[1];
703} __packed;
704
705
706
707
708
709struct amap_eq_entry {
710 u8 valid;
711 u8 major_code[3];
712 u8 minor_code[12];
713 u8 resource_id[16];
714
715} __packed;
716
717struct cq_db {
718 u32 dw[1];
719} __packed;
720
721
722
723
724
725struct amap_cq_db {
726 u8 qid[10];
727 u8 event[1];
728 u8 rsvd0[5];
729 u8 num_popped[13];
730 u8 rearm[1];
731 u8 rsvd1[2];
732} __packed;
733
734void beiscsi_process_eq(struct beiscsi_hba *phba);
735
736struct iscsi_wrb {
737 u32 dw[16];
738} __packed;
739
740#define WRB_TYPE_MASK 0xF0000000
741#define SKH_WRB_TYPE_OFFSET 27
742#define BE_WRB_TYPE_OFFSET 28
743
744#define ADAPTER_SET_WRB_TYPE(pwrb, wrb_type, type_offset) \
745 (pwrb->dw[0] |= (wrb_type << type_offset))
746
747
748
749
750
751struct amap_iscsi_wrb {
752 u8 lun[14];
753 u8 lt;
754 u8 invld;
755 u8 wrb_idx[8];
756 u8 dsp;
757 u8 dmsg;
758 u8 undr_run;
759 u8 over_run;
760 u8 type[4];
761 u8 ptr2nextwrb[8];
762 u8 r2t_exp_dtl[24];
763 u8 sgl_icd_idx[12];
764 u8 rsvd0[20];
765 u8 exp_data_sn[32];
766 u8 iscsi_bhs_addr_hi[32];
767 u8 iscsi_bhs_addr_lo[32];
768 u8 cmdsn_itt[32];
769 u8 dif_ref_tag[32];
770 u8 sge0_addr_hi[32];
771 u8 sge0_addr_lo[32];
772 u8 sge0_offset[22];
773 u8 pbs;
774 u8 dif_mode[2];
775 u8 rsvd1[6];
776 u8 sge0_last;
777 u8 sge0_len[17];
778 u8 dif_meta_tag[14];
779 u8 sge0_in_ddr;
780 u8 sge1_addr_hi[32];
781 u8 sge1_addr_lo[32];
782 u8 sge1_r2t_offset[22];
783 u8 rsvd2[9];
784 u8 sge1_last;
785 u8 sge1_len[17];
786 u8 ref_sgl_icd_idx[12];
787 u8 rsvd3[2];
788 u8 sge1_in_ddr;
789
790} __packed;
791
792struct amap_iscsi_wrb_v2 {
793 u8 r2t_exp_dtl[25];
794 u8 rsvd0[2];
795 u8 type[5];
796 u8 ptr2nextwrb[8];
797 u8 wrb_idx[8];
798 u8 lun[16];
799 u8 sgl_idx[16];
800 u8 ref_sgl_icd_idx[16];
801 u8 exp_data_sn[32];
802 u8 iscsi_bhs_addr_hi[32];
803 u8 iscsi_bhs_addr_lo[32];
804 u8 cq_id[16];
805 u8 rsvd1[16];
806 u8 cmdsn_itt[32];
807 u8 sge0_addr_hi[32];
808 u8 sge0_addr_lo[32];
809 u8 sge0_offset[24];
810 u8 rsvd2[7];
811 u8 sge0_last;
812 u8 sge0_len[17];
813 u8 rsvd3[7];
814 u8 diff_enbl;
815 u8 u_run;
816 u8 o_run;
817 u8 invalid;
818 u8 dsp;
819 u8 dmsg;
820 u8 rsvd4;
821 u8 lt;
822 u8 sge1_addr_hi[32];
823 u8 sge1_addr_lo[32];
824 u8 sge1_r2t_offset[24];
825 u8 rsvd5[7];
826 u8 sge1_last;
827 u8 sge1_len[17];
828 u8 rsvd6[15];
829} __packed;
830
831
832struct wrb_handle *alloc_wrb_handle(struct beiscsi_hba *phba, unsigned int cid);
833void
834free_mgmt_sgl_handle(struct beiscsi_hba *phba, struct sgl_handle *psgl_handle);
835
836void beiscsi_process_all_cqs(struct work_struct *work);
837void beiscsi_free_mgmt_task_handles(struct beiscsi_conn *beiscsi_conn,
838 struct iscsi_task *task);
839
840void hwi_ring_cq_db(struct beiscsi_hba *phba,
841 unsigned int id, unsigned int num_processed,
842 unsigned char rearm, unsigned char event);
843
844unsigned int beiscsi_process_cq(struct be_eq_obj *pbe_eq);
845
846static inline bool beiscsi_error(struct beiscsi_hba *phba)
847{
848 return phba->ue_detected || phba->fw_timeout;
849}
850
851struct pdu_nop_out {
852 u32 dw[12];
853};
854
855
856
857
858
859struct amap_pdu_nop_out {
860 u8 opcode[6];
861 u8 i_bit;
862 u8 x_bit;
863 u8 fp_bit_filler1[7];
864 u8 f_bit;
865 u8 reserved1[16];
866 u8 ahs_length[8];
867 u8 data_len_hi[8];
868 u8 data_len_lo[16];
869 u8 lun[64];
870 u8 itt[32];
871 u8 ttt[32];
872 u8 cmd_sn[32];
873 u8 exp_stat_sn[32];
874 u8 reserved5[128];
875};
876
877#define PDUBASE_OPCODE_MASK 0x0000003F
878#define PDUBASE_DATALENHI_MASK 0x0000FF00
879#define PDUBASE_DATALENLO_MASK 0xFFFF0000
880
881struct pdu_base {
882 u32 dw[16];
883} __packed;
884
885
886
887
888
889struct amap_pdu_base {
890 u8 opcode[6];
891 u8 i_bit;
892 u8 x_bit;
893 u8 reserved1[24];
894 u8 ahs_length[8];
895 u8 data_len_hi[8];
896 u8 data_len_lo[16];
897 u8 lun[64];
898 u8 itt[32];
899 u8 reserved4[224];
900};
901
902struct iscsi_target_context_update_wrb {
903 u32 dw[16];
904} __packed;
905
906
907
908
909
910#define BE_TGT_CTX_UPDT_CMD 0x07
911struct amap_iscsi_target_context_update_wrb {
912 u8 lun[14];
913 u8 lt;
914 u8 invld;
915 u8 wrb_idx[8];
916 u8 dsp;
917 u8 dmsg;
918 u8 undr_run;
919 u8 over_run;
920 u8 type[4];
921 u8 ptr2nextwrb[8];
922 u8 max_burst_length[19];
923 u8 rsvd0[5];
924 u8 rsvd1[15];
925 u8 max_send_data_segment_length[17];
926 u8 first_burst_length[14];
927 u8 rsvd2[2];
928 u8 tx_wrbindex_drv_msg[8];
929 u8 rsvd3[5];
930 u8 session_state[3];
931 u8 rsvd4[16];
932 u8 tx_jumbo;
933 u8 hde;
934 u8 dde;
935 u8 erl[2];
936 u8 domain_id[5];
937 u8 mode;
938 u8 imd;
939 u8 ir2t;
940 u8 notpredblq[2];
941 u8 compltonack;
942 u8 stat_sn[32];
943 u8 pad_buffer_addr_hi[32];
944 u8 pad_buffer_addr_lo[32];
945 u8 pad_addr_hi[32];
946 u8 pad_addr_lo[32];
947 u8 rsvd5[32];
948 u8 rsvd6[32];
949 u8 rsvd7[32];
950 u8 rsvd8[32];
951 u8 rsvd9[32];
952 u8 rsvd10[32];
953
954} __packed;
955
956#define BEISCSI_MAX_RECV_DATASEG_LEN (64 * 1024)
957#define BEISCSI_MAX_CXNS 1
958struct amap_iscsi_target_context_update_wrb_v2 {
959 u8 max_burst_length[24];
960 u8 rsvd0[3];
961 u8 type[5];
962 u8 ptr2nextwrb[8];
963 u8 wrb_idx[8];
964 u8 rsvd1[16];
965 u8 max_send_data_segment_length[24];
966 u8 rsvd2[8];
967 u8 first_burst_length[24];
968 u8 rsvd3[8];
969 u8 max_r2t[16];
970 u8 rsvd4;
971 u8 hde;
972 u8 dde;
973 u8 erl[2];
974 u8 rsvd5[6];
975 u8 imd;
976 u8 ir2t;
977 u8 rsvd6[3];
978 u8 stat_sn[32];
979 u8 rsvd7[32];
980 u8 rsvd8[32];
981 u8 max_recv_dataseg_len[24];
982 u8 rsvd9[8];
983 u8 rsvd10[32];
984 u8 rsvd11[32];
985 u8 max_cxns[16];
986 u8 rsvd12[11];
987 u8 invld;
988 u8 rsvd13;
989 u8 dmsg;
990 u8 data_seq_inorder;
991 u8 pdu_seq_inorder;
992 u8 rsvd14[32];
993 u8 rsvd15[32];
994 u8 rsvd16[32];
995 u8 rsvd17[32];
996} __packed;
997
998
999struct be_ring {
1000 u32 pages;
1001 u32 id;
1002 u32 num;
1003 u32 cidx;
1004 u32 pidx;
1005 u32 item_size;
1006 u8 ulp_num;
1007 u16 register_set;
1008 u16 doorbell_format;
1009 u32 doorbell_offset;
1010
1011 void *va;
1012
1013
1014
1015};
1016
1017struct hwi_controller {
1018 struct list_head io_sgl_list;
1019 struct list_head eh_sgl_list;
1020 struct sgl_handle *psgl_handle_base;
1021 unsigned int wrb_mem_index;
1022
1023 struct hwi_wrb_context *wrb_context;
1024 struct mcc_wrb *pmcc_wrb_base;
1025 struct be_ring default_pdu_hdr[BEISCSI_ULP_COUNT];
1026 struct be_ring default_pdu_data[BEISCSI_ULP_COUNT];
1027 struct hwi_context_memory *phwi_ctxt;
1028};
1029
1030enum hwh_type_enum {
1031 HWH_TYPE_IO = 1,
1032 HWH_TYPE_LOGOUT = 2,
1033 HWH_TYPE_TMF = 3,
1034 HWH_TYPE_NOP = 4,
1035 HWH_TYPE_IO_RD = 5,
1036 HWH_TYPE_LOGIN = 11,
1037 HWH_TYPE_INVALID = 0xFFFFFFFF
1038};
1039
1040struct wrb_handle {
1041 enum hwh_type_enum type;
1042 unsigned short wrb_index;
1043 unsigned short nxt_wrb_index;
1044
1045 struct iscsi_task *pio_handle;
1046 struct iscsi_wrb *pwrb;
1047};
1048
1049struct hwi_context_memory {
1050
1051 u16 min_eqd;
1052 u16 max_eqd;
1053 u16 cur_eqd;
1054 struct be_eq_obj be_eq[MAX_CPUS];
1055 struct be_queue_info be_cq[MAX_CPUS - 1];
1056
1057 struct be_queue_info *be_wrbq;
1058 struct be_queue_info be_def_hdrq[BEISCSI_ULP_COUNT];
1059 struct be_queue_info be_def_dataq[BEISCSI_ULP_COUNT];
1060 struct hwi_async_pdu_context *pasync_ctx[BEISCSI_ULP_COUNT];
1061};
1062
1063
1064#define BEISCSI_LOG_INIT 0x0001
1065#define BEISCSI_LOG_MBOX 0x0002
1066#define BEISCSI_LOG_MISC 0x0004
1067#define BEISCSI_LOG_EH 0x0008
1068#define BEISCSI_LOG_IO 0x0010
1069#define BEISCSI_LOG_CONFIG 0x0020
1070#define BEISCSI_LOG_ISCSI 0x0040
1071
1072#define beiscsi_log(phba, level, mask, fmt, arg...) \
1073do { \
1074 uint32_t log_value = phba->attr_log_enable; \
1075 if (((mask) & log_value) || (level[1] <= '3')) \
1076 shost_printk(level, phba->shost, \
1077 fmt, __LINE__, ##arg); \
1078} while (0)
1079
1080#endif
1081