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26#ifndef _MV_DEFS_H_
27#define _MV_DEFS_H_
28
29#define PCI_DEVICE_ID_ARECA_1300 0x1300
30#define PCI_DEVICE_ID_ARECA_1320 0x1320
31
32enum chip_flavors {
33 chip_6320,
34 chip_6440,
35 chip_6485,
36 chip_9480,
37 chip_9180,
38 chip_9445,
39 chip_9485,
40 chip_1300,
41 chip_1320
42};
43
44
45enum driver_configuration {
46 MVS_TX_RING_SZ = 1024,
47 MVS_RX_RING_SZ = 1024,
48
49
50 MVS_SOC_SLOTS = 64,
51 MVS_SOC_TX_RING_SZ = MVS_SOC_SLOTS * 2,
52 MVS_SOC_RX_RING_SZ = MVS_SOC_SLOTS * 2,
53
54 MVS_SLOT_BUF_SZ = 8192,
55 MVS_SSP_CMD_SZ = 64,
56 MVS_ATA_CMD_SZ = 96,
57 MVS_OAF_SZ = 64,
58 MVS_QUEUE_SIZE = 64,
59 MVS_SOC_CAN_QUEUE = MVS_SOC_SLOTS - 2,
60};
61
62
63enum hardware_details {
64 MVS_MAX_PHYS = 8,
65 MVS_MAX_PORTS = 8,
66 MVS_SOC_PHYS = 4,
67 MVS_SOC_PORTS = 4,
68 MVS_MAX_DEVICES = 1024,
69};
70
71
72enum peripheral_registers {
73 SPI_CTL = 0x10,
74 SPI_CMD = 0x14,
75 SPI_DATA = 0x18,
76};
77
78enum peripheral_register_bits {
79 TWSI_RDY = (1U << 7),
80 TWSI_RD = (1U << 4),
81
82 SPI_ADDR_MASK = 0x3ffff,
83};
84
85enum hw_register_bits {
86
87 INT_EN = (1U << 1),
88 HBA_RST = (1U << 0),
89
90
91 INT_XOR = (1U << 4),
92 INT_SAS_SATA = (1U << 0),
93
94
95 SATA_TARGET = (1U << 16),
96 MODE_AUTO_DET_PORT7 = (1U << 15),
97 MODE_AUTO_DET_PORT6 = (1U << 14),
98 MODE_AUTO_DET_PORT5 = (1U << 13),
99 MODE_AUTO_DET_PORT4 = (1U << 12),
100 MODE_AUTO_DET_PORT3 = (1U << 11),
101 MODE_AUTO_DET_PORT2 = (1U << 10),
102 MODE_AUTO_DET_PORT1 = (1U << 9),
103 MODE_AUTO_DET_PORT0 = (1U << 8),
104 MODE_AUTO_DET_EN = MODE_AUTO_DET_PORT0 | MODE_AUTO_DET_PORT1 |
105 MODE_AUTO_DET_PORT2 | MODE_AUTO_DET_PORT3 |
106 MODE_AUTO_DET_PORT4 | MODE_AUTO_DET_PORT5 |
107 MODE_AUTO_DET_PORT6 | MODE_AUTO_DET_PORT7,
108 MODE_SAS_PORT7_MASK = (1U << 7),
109 MODE_SAS_PORT6_MASK = (1U << 6),
110 MODE_SAS_PORT5_MASK = (1U << 5),
111 MODE_SAS_PORT4_MASK = (1U << 4),
112 MODE_SAS_PORT3_MASK = (1U << 3),
113 MODE_SAS_PORT2_MASK = (1U << 2),
114 MODE_SAS_PORT1_MASK = (1U << 1),
115 MODE_SAS_PORT0_MASK = (1U << 0),
116 MODE_SAS_SATA = MODE_SAS_PORT0_MASK | MODE_SAS_PORT1_MASK |
117 MODE_SAS_PORT2_MASK | MODE_SAS_PORT3_MASK |
118 MODE_SAS_PORT4_MASK | MODE_SAS_PORT5_MASK |
119 MODE_SAS_PORT6_MASK | MODE_SAS_PORT7_MASK,
120
121
122
123
124
125
126
127 TX_EN = (1U << 16),
128 TX_RING_SZ_MASK = 0xfff,
129
130
131 RX_EN = (1U << 16),
132 RX_RING_SZ_MASK = 0xfff,
133
134
135 COAL_EN = (1U << 16),
136
137
138 CINT_I2C = (1U << 31),
139 CINT_SW0 = (1U << 30),
140 CINT_SW1 = (1U << 29),
141 CINT_PRD_BC = (1U << 28),
142 CINT_DMA_PCIE = (1U << 27),
143 CINT_MEM = (1U << 26),
144 CINT_I2C_SLAVE = (1U << 25),
145 CINT_NON_SPEC_NCQ_ERROR = (1U << 25),
146 CINT_SRS = (1U << 3),
147 CINT_CI_STOP = (1U << 1),
148 CINT_DONE = (1U << 0),
149
150
151 CINT_PORT_STOPPED = (1U << 16),
152 CINT_PORT = (1U << 8),
153 CINT_PORT_MASK_OFFSET = 8,
154 CINT_PORT_MASK = (0xFF << CINT_PORT_MASK_OFFSET),
155 CINT_PHY_MASK_OFFSET = 4,
156 CINT_PHY_MASK = (0x0F << CINT_PHY_MASK_OFFSET),
157
158
159 TXQ_CMD_SHIFT = 29,
160 TXQ_CMD_SSP = 1,
161 TXQ_CMD_SMP = 2,
162 TXQ_CMD_STP = 3,
163 TXQ_CMD_SSP_FREE_LIST = 4,
164 TXQ_CMD_SLOT_RESET = 7,
165 TXQ_MODE_I = (1U << 28),
166 TXQ_MODE_TARGET = 0,
167 TXQ_MODE_INITIATOR = 1,
168 TXQ_PRIO_HI = (1U << 27),
169 TXQ_PRI_NORMAL = 0,
170 TXQ_PRI_HIGH = 1,
171 TXQ_SRS_SHIFT = 20,
172 TXQ_SRS_MASK = 0x7f,
173 TXQ_PHY_SHIFT = 12,
174 TXQ_PHY_MASK = 0xff,
175 TXQ_SLOT_MASK = 0xfff,
176
177
178 RXQ_GOOD = (1U << 23),
179 RXQ_SLOT_RESET = (1U << 21),
180 RXQ_CMD_RX = (1U << 20),
181 RXQ_ATTN = (1U << 19),
182 RXQ_RSP = (1U << 18),
183 RXQ_ERR = (1U << 17),
184 RXQ_DONE = (1U << 16),
185 RXQ_SLOT_MASK = 0xfff,
186
187
188 MCH_PRD_LEN_SHIFT = 16,
189 MCH_SSP_FR_TYPE_SHIFT = 13,
190
191
192 MCH_SSP_FR_CMD = 0x0,
193
194
195 MCH_SSP_FR_TASK = 0x1,
196
197
198 MCH_SSP_FR_XFER_RDY = 0x4,
199 MCH_SSP_FR_RESP = 0x5,
200 MCH_SSP_FR_READ = 0x6,
201 MCH_SSP_FR_READ_RESP = 0x7,
202
203 MCH_SSP_MODE_PASSTHRU = 1,
204 MCH_SSP_MODE_NORMAL = 0,
205 MCH_PASSTHRU = (1U << 12),
206 MCH_FBURST = (1U << 11),
207 MCH_CHK_LEN = (1U << 10),
208 MCH_RETRY = (1U << 9),
209 MCH_PROTECTION = (1U << 8),
210 MCH_RESET = (1U << 7),
211 MCH_FPDMA = (1U << 6),
212 MCH_ATAPI = (1U << 5),
213 MCH_BIST = (1U << 4),
214 MCH_PMP_MASK = 0xf,
215
216 CCTL_RST = (1U << 5),
217
218
219 CCTL_ENDIAN_DATA = (1U << 3),
220 CCTL_ENDIAN_RSP = (1U << 2),
221 CCTL_ENDIAN_OPEN = (1U << 1),
222 CCTL_ENDIAN_CMD = (1U << 0),
223
224
225 PHY_SSP_RST = (1U << 3),
226 PHY_BCAST_CHG = (1U << 2),
227 PHY_RST_HARD = (1U << 1),
228 PHY_RST = (1U << 0),
229 PHY_READY_MASK = (1U << 20),
230
231
232 PHYEV_DEC_ERR = (1U << 24),
233 PHYEV_DCDR_ERR = (1U << 23),
234 PHYEV_CRC_ERR = (1U << 22),
235 PHYEV_UNASSOC_FIS = (1U << 19),
236 PHYEV_AN = (1U << 18),
237 PHYEV_BIST_ACT = (1U << 17),
238 PHYEV_SIG_FIS = (1U << 16),
239 PHYEV_POOF = (1U << 12),
240 PHYEV_IU_BIG = (1U << 11),
241 PHYEV_IU_SMALL = (1U << 10),
242 PHYEV_UNK_TAG = (1U << 9),
243 PHYEV_BROAD_CH = (1U << 8),
244 PHYEV_COMWAKE = (1U << 7),
245 PHYEV_PORT_SEL = (1U << 6),
246 PHYEV_HARD_RST = (1U << 5),
247 PHYEV_ID_TMOUT = (1U << 4),
248 PHYEV_ID_FAIL = (1U << 3),
249 PHYEV_ID_DONE = (1U << 2),
250 PHYEV_HARD_RST_DONE = (1U << 1),
251 PHYEV_RDY_CH = (1U << 0),
252
253
254 PCS_EN_SATA_REG_SHIFT = (16),
255 PCS_EN_PORT_XMT_SHIFT = (12),
256 PCS_EN_PORT_XMT_SHIFT2 = (8),
257 PCS_SATA_RETRY = (1U << 8),
258 PCS_RSP_RX_EN = (1U << 7),
259 PCS_SATA_RETRY_2 = (1U << 6),
260 PCS_SELF_CLEAR = (1U << 5),
261 PCS_FIS_RX_EN = (1U << 4),
262 PCS_CMD_STOP_ERR = (1U << 3),
263 PCS_CMD_RST = (1U << 1),
264 PCS_CMD_EN = (1U << 0),
265
266
267 PORT_DEV_SSP_TRGT = (1U << 19),
268 PORT_DEV_SMP_TRGT = (1U << 18),
269 PORT_DEV_STP_TRGT = (1U << 17),
270 PORT_DEV_SSP_INIT = (1U << 11),
271 PORT_DEV_SMP_INIT = (1U << 10),
272 PORT_DEV_STP_INIT = (1U << 9),
273 PORT_PHY_ID_MASK = (0xFFU << 24),
274 PORT_SSP_TRGT_MASK = (0x1U << 19),
275 PORT_SSP_INIT_MASK = (0x1U << 11),
276 PORT_DEV_TRGT_MASK = (0x7U << 17),
277 PORT_DEV_INIT_MASK = (0x7U << 9),
278 PORT_DEV_TYPE_MASK = (0x7U << 0),
279
280
281 PHY_RDY = (1U << 2),
282 PHY_DW_SYNC = (1U << 1),
283 PHY_OOB_DTCTD = (1U << 0),
284
285
286
287 PHY_MODE6_LATECLK = (1U << 29),
288 PHY_MODE6_DTL_SPEED = (1U << 27),
289 PHY_MODE6_FC_ORDER = (1U << 26),
290 PHY_MODE6_MUCNT_EN = (1U << 24),
291 PHY_MODE6_SEL_MUCNT_LEN = (1U << 22),
292 PHY_MODE6_SELMUPI = (1U << 20),
293 PHY_MODE6_SELMUPF = (1U << 18),
294 PHY_MODE6_SELMUFF = (1U << 16),
295 PHY_MODE6_SELMUFI = (1U << 14),
296 PHY_MODE6_FREEZE_LOOP = (1U << 12),
297 PHY_MODE6_INT_RXFOFFS = (1U << 3),
298 PHY_MODE6_FRC_RXFOFFS = (1U << 2),
299 PHY_MODE6_STAU_0D8 = (1U << 1),
300 PHY_MODE6_RXSAT_DIS = (1U << 0),
301};
302
303
304enum sas_sata_config_port_regs {
305 PHYR_IDENTIFY = 0x00,
306 PHYR_ADDR_LO = 0x04,
307 PHYR_ADDR_HI = 0x08,
308 PHYR_ATT_DEV_INFO = 0x0C,
309 PHYR_ATT_ADDR_LO = 0x10,
310 PHYR_ATT_ADDR_HI = 0x14,
311 PHYR_SATA_CTL = 0x18,
312 PHYR_PHY_STAT = 0x1C,
313 PHYR_SATA_SIG0 = 0x20,
314 PHYR_SATA_SIG1 = 0x24,
315 PHYR_SATA_SIG2 = 0x28,
316 PHYR_SATA_SIG3 = 0x2c,
317 PHYR_R_ERR_COUNT = 0x30,
318 PHYR_CRC_ERR_COUNT = 0x34,
319 PHYR_WIDE_PORT = 0x38,
320 PHYR_CURRENT0 = 0x80,
321 PHYR_CURRENT1 = 0x84,
322 PHYR_CURRENT2 = 0x88,
323 CONFIG_ID_FRAME0 = 0x100,
324 CONFIG_ID_FRAME1 = 0x104,
325 CONFIG_ID_FRAME2 = 0x108,
326 CONFIG_ID_FRAME3 = 0x10c,
327 CONFIG_ID_FRAME4 = 0x110,
328 CONFIG_ID_FRAME5 = 0x114,
329 CONFIG_ID_FRAME6 = 0x118,
330 CONFIG_ATT_ID_FRAME0 = 0x11c,
331 CONFIG_ATT_ID_FRAME1 = 0x120,
332 CONFIG_ATT_ID_FRAME2 = 0x124,
333 CONFIG_ATT_ID_FRAME3 = 0x128,
334 CONFIG_ATT_ID_FRAME4 = 0x12c,
335 CONFIG_ATT_ID_FRAME5 = 0x130,
336 CONFIG_ATT_ID_FRAME6 = 0x134,
337};
338
339enum sas_cmd_port_registers {
340 CMD_CMRST_OOB_DET = 0x100,
341 CMD_CMWK_OOB_DET = 0x104,
342 CMD_CMSAS_OOB_DET = 0x108,
343 CMD_BRST_OOB_DET = 0x10c,
344 CMD_OOB_SPACE = 0x110,
345 CMD_OOB_BURST = 0x114,
346 CMD_PHY_TIMER = 0x118,
347 CMD_PHY_CONFIG0 = 0x11c,
348 CMD_PHY_CONFIG1 = 0x120,
349 CMD_SAS_CTL0 = 0x124,
350 CMD_SAS_CTL1 = 0x128,
351 CMD_SAS_CTL2 = 0x12c,
352 CMD_SAS_CTL3 = 0x130,
353 CMD_ID_TEST = 0x134,
354 CMD_PL_TIMER = 0x138,
355 CMD_WD_TIMER = 0x13c,
356 CMD_PORT_SEL_COUNT = 0x140,
357 CMD_APP_MEM_CTL = 0x144,
358 CMD_XOR_MEM_CTL = 0x148,
359 CMD_DMA_MEM_CTL = 0x14c,
360 CMD_PORT_MEM_CTL0 = 0x150,
361 CMD_PORT_MEM_CTL1 = 0x154,
362 CMD_SATA_PORT_MEM_CTL0 = 0x158,
363 CMD_SATA_PORT_MEM_CTL1 = 0x15c,
364 CMD_XOR_MEM_BIST_CTL = 0x160,
365 CMD_XOR_MEM_BIST_STAT = 0x164,
366 CMD_DMA_MEM_BIST_CTL = 0x168,
367 CMD_DMA_MEM_BIST_STAT = 0x16c,
368 CMD_PORT_MEM_BIST_CTL = 0x170,
369 CMD_PORT_MEM_BIST_STAT0 = 0x174,
370 CMD_PORT_MEM_BIST_STAT1 = 0x178,
371 CMD_STP_MEM_BIST_CTL = 0x17c,
372 CMD_STP_MEM_BIST_STAT0 = 0x180,
373 CMD_STP_MEM_BIST_STAT1 = 0x184,
374 CMD_RESET_COUNT = 0x188,
375 CMD_MONTR_DATA_SEL = 0x18C,
376 CMD_PLL_PHY_CONFIG = 0x190,
377 CMD_PHY_CTL = 0x194,
378 CMD_PHY_TEST_COUNT0 = 0x198,
379 CMD_PHY_TEST_COUNT1 = 0x19C,
380 CMD_PHY_TEST_COUNT2 = 0x1A0,
381 CMD_APP_ERR_CONFIG = 0x1A4,
382 CMD_PND_FIFO_CTL0 = 0x1A8,
383 CMD_HOST_CTL = 0x1AC,
384 CMD_HOST_WR_DATA = 0x1B0,
385 CMD_HOST_RD_DATA = 0x1B4,
386 CMD_PHY_MODE_21 = 0x1B8,
387 CMD_SL_MODE0 = 0x1BC,
388 CMD_SL_MODE1 = 0x1C0,
389 CMD_PND_FIFO_CTL1 = 0x1C4,
390 CMD_PORT_LAYER_TIMER1 = 0x1E0,
391 CMD_LINK_TIMER = 0x1E4,
392};
393
394enum mvs_info_flags {
395 MVF_PHY_PWR_FIX = (1U << 1),
396 MVF_FLAG_SOC = (1U << 2),
397};
398
399enum mvs_event_flags {
400 PHY_PLUG_EVENT = (3U),
401 PHY_PLUG_IN = (1U << 0),
402 PHY_PLUG_OUT = (1U << 1),
403 EXP_BRCT_CHG = (1U << 2),
404};
405
406enum mvs_port_type {
407 PORT_TGT_MASK = (1U << 5),
408 PORT_INIT_PORT = (1U << 4),
409 PORT_TGT_PORT = (1U << 3),
410 PORT_INIT_TGT_PORT = (PORT_INIT_PORT | PORT_TGT_PORT),
411 PORT_TYPE_SAS = (1U << 1),
412 PORT_TYPE_SATA = (1U << 0),
413};
414
415
416enum ct_format {
417
418 SSP_F_H = 0x00,
419 SSP_F_IU = 0x18,
420 SSP_F_MAX = 0x4D,
421
422 STP_CMD_FIS = 0x00,
423 STP_ATAPI_CMD = 0x40,
424 STP_F_MAX = 0x10,
425
426 SMP_F_T = 0x00,
427 SMP_F_DEP = 0x01,
428 SMP_F_MAX = 0x101,
429};
430
431enum status_buffer {
432 SB_EIR_OFF = 0x00,
433 SB_RFB_OFF = 0x08,
434 SB_RFB_MAX = 0x400,
435};
436
437enum error_info_rec {
438 CMD_ISS_STPD = (1U << 31),
439 CMD_PI_ERR = (1U << 30),
440 RSP_OVER = (1U << 29),
441 RETRY_LIM = (1U << 28),
442 UNK_FIS = (1U << 27),
443 DMA_TERM = (1U << 26),
444 SYNC_ERR = (1U << 25),
445 TFILE_ERR = (1U << 24),
446 R_ERR = (1U << 23),
447 RD_OFS = (1U << 20),
448 XFER_RDY_OFS = (1U << 19),
449 UNEXP_XFER_RDY = (1U << 18),
450 DATA_OVER_UNDER = (1U << 16),
451 INTERLOCK = (1U << 15),
452 NAK = (1U << 14),
453 ACK_NAK_TO = (1U << 13),
454 CXN_CLOSED = (1U << 12),
455 OPEN_TO = (1U << 11),
456 PATH_BLOCKED = (1U << 10),
457 NO_DEST = (1U << 9),
458 STP_RES_BSY = (1U << 8),
459 BREAK = (1U << 7),
460 BAD_DEST = (1U << 6),
461 BAD_PROTO = (1U << 5),
462 BAD_RATE = (1U << 4),
463 WRONG_DEST = (1U << 3),
464 CREDIT_TO = (1U << 2),
465 WDOG_TO = (1U << 1),
466 BUF_PAR = (1U << 0),
467};
468
469enum error_info_rec_2 {
470 SLOT_BSY_ERR = (1U << 31),
471 GRD_CHK_ERR = (1U << 14),
472 APP_CHK_ERR = (1U << 13),
473 REF_CHK_ERR = (1U << 12),
474 USR_BLK_NM = (1U << 0),
475};
476
477enum pci_cfg_register_bits {
478 PCTL_PWR_OFF = (0xFU << 24),
479 PCTL_COM_ON = (0xFU << 20),
480 PCTL_LINK_RST = (0xFU << 16),
481 PCTL_LINK_OFFS = (16),
482 PCTL_PHY_DSBL = (0xFU << 12),
483 PCTL_PHY_DSBL_OFFS = (12),
484 PRD_REQ_SIZE = (0x4000),
485 PRD_REQ_MASK = (0x00007000),
486 PLS_NEG_LINK_WD = (0x3FU << 4),
487 PLS_NEG_LINK_WD_OFFS = 4,
488 PLS_LINK_SPD = (0x0FU << 0),
489 PLS_LINK_SPD_OFFS = 0,
490};
491
492enum open_frame_protocol {
493 PROTOCOL_SMP = 0x0,
494 PROTOCOL_SSP = 0x1,
495 PROTOCOL_STP = 0x2,
496};
497
498
499enum datapres_field {
500 NO_DATA = 0,
501 RESPONSE_DATA = 1,
502 SENSE_DATA = 2,
503};
504
505
506struct mvs_tmf_task{
507 u8 tmf;
508 u16 tag_of_task_to_be_managed;
509};
510#endif
511