1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37#ifndef T128_H
38#define T128_H
39
40#define T128_PUBLIC_RELEASE 3
41
42#define TDEBUG 0
43#define TDEBUG_INIT 0x1
44#define TDEBUG_TRANSFER 0x2
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60#define T_ROM_OFFSET 0
61
62
63
64
65
66#define T_RAM_OFFSET 0x1800
67
68
69
70
71
72#define T_CONTROL_REG_OFFSET 0x1c00
73#define T_CR_INT 0x10
74#define T_CR_CT 0x02
75
76#define T_STATUS_REG_OFFSET 0x1c20
77#define T_ST_BOOT 0x80
78#define T_ST_S3 0x40
79#define T_ST_S2 0x20
80#define T_ST_S1 0x10
81#define T_ST_PS2 0x08
82#define T_ST_RDY 0x04
83#define T_ST_TIM 0x02
84#define T_ST_ZERO 0x01
85
86#define T_5380_OFFSET 0x1d00
87
88#define T_DATA_REG_OFFSET 0x1e00
89
90#ifndef ASM
91static int t128_abort(struct scsi_cmnd *);
92static int t128_biosparam(struct scsi_device *, struct block_device *,
93 sector_t, int*);
94static int t128_detect(struct scsi_host_template *);
95static int t128_queue_command(struct Scsi_Host *, struct scsi_cmnd *);
96static int t128_bus_reset(struct scsi_cmnd *);
97
98#ifndef CMD_PER_LUN
99#define CMD_PER_LUN 2
100#endif
101
102#ifndef CAN_QUEUE
103#define CAN_QUEUE 32
104#endif
105
106#define NCR5380_implementation_fields \
107 void __iomem *base
108
109#define NCR5380_local_declare() \
110 void __iomem *base
111
112#define NCR5380_setup(instance) \
113 base = ((struct NCR5380_hostdata *)(instance->hostdata))->base
114
115#define T128_address(reg) (base + T_5380_OFFSET + ((reg) * 0x20))
116
117#if !(TDEBUG & TDEBUG_TRANSFER)
118#define NCR5380_read(reg) readb(T128_address(reg))
119#define NCR5380_write(reg, value) writeb((value),(T128_address(reg)))
120#else
121#define NCR5380_read(reg) \
122 (((unsigned char) printk("scsi%d : read register %d at address %08x\n"\
123 , instance->hostno, (reg), T128_address(reg))), readb(T128_address(reg)))
124
125#define NCR5380_write(reg, value) { \
126 printk("scsi%d : write %02x to register %d at address %08x\n", \
127 instance->hostno, (value), (reg), T128_address(reg)); \
128 writeb((value), (T128_address(reg))); \
129}
130#endif
131
132#define NCR5380_intr t128_intr
133#define do_NCR5380_intr do_t128_intr
134#define NCR5380_queue_command t128_queue_command
135#define NCR5380_abort t128_abort
136#define NCR5380_bus_reset t128_bus_reset
137#define NCR5380_show_info t128_show_info
138#define NCR5380_write_info t128_write_info
139
140
141
142
143#define T128_IRQS 0xc4a8
144
145#endif
146#endif
147