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11#include <linux/types.h>
12#include <linux/mutex.h>
13#include <linux/device.h>
14#include <linux/spi/spi.h>
15#include <linux/slab.h>
16#include <linux/sysfs.h>
17#include <linux/delay.h>
18#include <linux/gpio.h>
19#include <linux/module.h>
20
21#include <linux/iio/iio.h>
22#include <linux/iio/sysfs.h>
23#include "ad2s1210.h"
24
25#define DRV_NAME "ad2s1210"
26
27#define AD2S1210_DEF_CONTROL 0x7E
28
29#define AD2S1210_MSB_IS_HIGH 0x80
30#define AD2S1210_MSB_IS_LOW 0x7F
31#define AD2S1210_PHASE_LOCK_RANGE_44 0x20
32#define AD2S1210_ENABLE_HYSTERESIS 0x10
33#define AD2S1210_SET_ENRES1 0x08
34#define AD2S1210_SET_ENRES0 0x04
35#define AD2S1210_SET_RES1 0x02
36#define AD2S1210_SET_RES0 0x01
37
38#define AD2S1210_SET_ENRESOLUTION (AD2S1210_SET_ENRES1 | \
39 AD2S1210_SET_ENRES0)
40#define AD2S1210_SET_RESOLUTION (AD2S1210_SET_RES1 | AD2S1210_SET_RES0)
41
42#define AD2S1210_REG_POSITION 0x80
43#define AD2S1210_REG_VELOCITY 0x82
44#define AD2S1210_REG_LOS_THRD 0x88
45#define AD2S1210_REG_DOS_OVR_THRD 0x89
46#define AD2S1210_REG_DOS_MIS_THRD 0x8A
47#define AD2S1210_REG_DOS_RST_MAX_THRD 0x8B
48#define AD2S1210_REG_DOS_RST_MIN_THRD 0x8C
49#define AD2S1210_REG_LOT_HIGH_THRD 0x8D
50#define AD2S1210_REG_LOT_LOW_THRD 0x8E
51#define AD2S1210_REG_EXCIT_FREQ 0x91
52#define AD2S1210_REG_CONTROL 0x92
53#define AD2S1210_REG_SOFT_RESET 0xF0
54#define AD2S1210_REG_FAULT 0xFF
55
56
57#define AD2S1210_SAA 3
58#define AD2S1210_PN (AD2S1210_SAA + AD2S1210_RES)
59
60#define AD2S1210_MIN_CLKIN 6144000
61#define AD2S1210_MAX_CLKIN 10240000
62#define AD2S1210_MIN_EXCIT 2000
63#define AD2S1210_MAX_EXCIT 20000
64#define AD2S1210_MIN_FCW 0x4
65#define AD2S1210_MAX_FCW 0x50
66
67
68#define AD2S1210_DEF_CLKIN 8192000
69
70#define AD2S1210_DEF_TCK (1000000000/AD2S1210_DEF_CLKIN)
71#define AD2S1210_DEF_EXCIT 10000
72
73enum ad2s1210_mode {
74 MOD_POS = 0,
75 MOD_VEL,
76 MOD_CONFIG,
77 MOD_RESERVED,
78};
79
80static const unsigned int ad2s1210_resolution_value[] = { 10, 12, 14, 16 };
81
82struct ad2s1210_state {
83 const struct ad2s1210_platform_data *pdata;
84 struct mutex lock;
85 struct spi_device *sdev;
86 unsigned int fclkin;
87 unsigned int fexcit;
88 bool hysteresis;
89 bool old_data;
90 u8 resolution;
91 enum ad2s1210_mode mode;
92 u8 rx[2] ____cacheline_aligned;
93 u8 tx[2] ____cacheline_aligned;
94};
95
96static const int ad2s1210_mode_vals[4][2] = {
97 [MOD_POS] = { 0, 0 },
98 [MOD_VEL] = { 0, 1 },
99 [MOD_CONFIG] = { 1, 0 },
100};
101static inline void ad2s1210_set_mode(enum ad2s1210_mode mode,
102 struct ad2s1210_state *st)
103{
104 gpio_set_value(st->pdata->a[0], ad2s1210_mode_vals[mode][0]);
105 gpio_set_value(st->pdata->a[1], ad2s1210_mode_vals[mode][1]);
106 st->mode = mode;
107}
108
109
110static int ad2s1210_config_write(struct ad2s1210_state *st, u8 data)
111{
112 int ret;
113
114 ad2s1210_set_mode(MOD_CONFIG, st);
115 st->tx[0] = data;
116 ret = spi_write(st->sdev, st->tx, 1);
117 if (ret < 0)
118 return ret;
119 st->old_data = true;
120
121 return 0;
122}
123
124
125static int ad2s1210_config_read(struct ad2s1210_state *st,
126 unsigned char address)
127{
128 struct spi_transfer xfer = {
129 .len = 2,
130 .rx_buf = st->rx,
131 .tx_buf = st->tx,
132 };
133 int ret = 0;
134
135 ad2s1210_set_mode(MOD_CONFIG, st);
136 st->tx[0] = address | AD2S1210_MSB_IS_HIGH;
137 st->tx[1] = AD2S1210_REG_FAULT;
138 ret = spi_sync_transfer(st->sdev, &xfer, 1);
139 if (ret < 0)
140 return ret;
141 st->old_data = true;
142
143 return st->rx[1];
144}
145
146static inline
147int ad2s1210_update_frequency_control_word(struct ad2s1210_state *st)
148{
149 int ret;
150 unsigned char fcw;
151
152 fcw = (unsigned char)(st->fexcit * (1 << 15) / st->fclkin);
153 if (fcw < AD2S1210_MIN_FCW || fcw > AD2S1210_MAX_FCW) {
154 pr_err("ad2s1210: FCW out of range\n");
155 return -ERANGE;
156 }
157
158 ret = ad2s1210_config_write(st, AD2S1210_REG_EXCIT_FREQ);
159 if (ret < 0)
160 return ret;
161
162 return ad2s1210_config_write(st, fcw);
163}
164
165static unsigned char ad2s1210_read_resolution_pin(struct ad2s1210_state *st)
166{
167 return ad2s1210_resolution_value[
168 (gpio_get_value(st->pdata->res[0]) << 1) |
169 gpio_get_value(st->pdata->res[1])];
170}
171
172static const int ad2s1210_res_pins[4][2] = {
173 { 0, 0 }, {0, 1}, {1, 0}, {1, 1}
174};
175
176static inline void ad2s1210_set_resolution_pin(struct ad2s1210_state *st)
177{
178 gpio_set_value(st->pdata->res[0],
179 ad2s1210_res_pins[(st->resolution - 10)/2][0]);
180 gpio_set_value(st->pdata->res[1],
181 ad2s1210_res_pins[(st->resolution - 10)/2][1]);
182}
183
184static inline int ad2s1210_soft_reset(struct ad2s1210_state *st)
185{
186 int ret;
187
188 ret = ad2s1210_config_write(st, AD2S1210_REG_SOFT_RESET);
189 if (ret < 0)
190 return ret;
191
192 return ad2s1210_config_write(st, 0x0);
193}
194
195static ssize_t ad2s1210_show_fclkin(struct device *dev,
196 struct device_attribute *attr,
197 char *buf)
198{
199 struct ad2s1210_state *st = iio_priv(dev_to_iio_dev(dev));
200
201 return sprintf(buf, "%d\n", st->fclkin);
202}
203
204static ssize_t ad2s1210_store_fclkin(struct device *dev,
205 struct device_attribute *attr,
206 const char *buf,
207 size_t len)
208{
209 struct ad2s1210_state *st = iio_priv(dev_to_iio_dev(dev));
210 unsigned int fclkin;
211 int ret;
212
213 ret = kstrtouint(buf, 10, &fclkin);
214 if (ret)
215 return ret;
216 if (fclkin < AD2S1210_MIN_CLKIN || fclkin > AD2S1210_MAX_CLKIN) {
217 pr_err("ad2s1210: fclkin out of range\n");
218 return -EINVAL;
219 }
220
221 mutex_lock(&st->lock);
222 st->fclkin = fclkin;
223
224 ret = ad2s1210_update_frequency_control_word(st);
225 if (ret < 0)
226 goto error_ret;
227 ret = ad2s1210_soft_reset(st);
228error_ret:
229 mutex_unlock(&st->lock);
230
231 return ret < 0 ? ret : len;
232}
233
234static ssize_t ad2s1210_show_fexcit(struct device *dev,
235 struct device_attribute *attr,
236 char *buf)
237{
238 struct ad2s1210_state *st = iio_priv(dev_to_iio_dev(dev));
239
240 return sprintf(buf, "%d\n", st->fexcit);
241}
242
243static ssize_t ad2s1210_store_fexcit(struct device *dev,
244 struct device_attribute *attr,
245 const char *buf, size_t len)
246{
247 struct ad2s1210_state *st = iio_priv(dev_to_iio_dev(dev));
248 unsigned int fexcit;
249 int ret;
250
251 ret = kstrtouint(buf, 10, &fexcit);
252 if (ret < 0)
253 return ret;
254 if (fexcit < AD2S1210_MIN_EXCIT || fexcit > AD2S1210_MAX_EXCIT) {
255 pr_err("ad2s1210: excitation frequency out of range\n");
256 return -EINVAL;
257 }
258 mutex_lock(&st->lock);
259 st->fexcit = fexcit;
260 ret = ad2s1210_update_frequency_control_word(st);
261 if (ret < 0)
262 goto error_ret;
263 ret = ad2s1210_soft_reset(st);
264error_ret:
265 mutex_unlock(&st->lock);
266
267 return ret < 0 ? ret : len;
268}
269
270static ssize_t ad2s1210_show_control(struct device *dev,
271 struct device_attribute *attr,
272 char *buf)
273{
274 struct ad2s1210_state *st = iio_priv(dev_to_iio_dev(dev));
275 int ret;
276
277 mutex_lock(&st->lock);
278 ret = ad2s1210_config_read(st, AD2S1210_REG_CONTROL);
279 mutex_unlock(&st->lock);
280 return ret < 0 ? ret : sprintf(buf, "0x%x\n", ret);
281}
282
283static ssize_t ad2s1210_store_control(struct device *dev,
284 struct device_attribute *attr,
285 const char *buf, size_t len)
286{
287 struct ad2s1210_state *st = iio_priv(dev_to_iio_dev(dev));
288 unsigned char udata;
289 unsigned char data;
290 int ret;
291
292 ret = kstrtou8(buf, 16, &udata);
293 if (ret)
294 return -EINVAL;
295
296 mutex_lock(&st->lock);
297 ret = ad2s1210_config_write(st, AD2S1210_REG_CONTROL);
298 if (ret < 0)
299 goto error_ret;
300 data = udata & AD2S1210_MSB_IS_LOW;
301 ret = ad2s1210_config_write(st, data);
302 if (ret < 0)
303 goto error_ret;
304
305 ret = ad2s1210_config_read(st, AD2S1210_REG_CONTROL);
306 if (ret < 0)
307 goto error_ret;
308 if (ret & AD2S1210_MSB_IS_HIGH) {
309 ret = -EIO;
310 pr_err("ad2s1210: write control register fail\n");
311 goto error_ret;
312 }
313 st->resolution
314 = ad2s1210_resolution_value[data & AD2S1210_SET_RESOLUTION];
315 if (st->pdata->gpioin) {
316 data = ad2s1210_read_resolution_pin(st);
317 if (data != st->resolution)
318 pr_warn("ad2s1210: resolution settings not match\n");
319 } else
320 ad2s1210_set_resolution_pin(st);
321
322 ret = len;
323 st->hysteresis = !!(data & AD2S1210_ENABLE_HYSTERESIS);
324
325error_ret:
326 mutex_unlock(&st->lock);
327 return ret;
328}
329
330static ssize_t ad2s1210_show_resolution(struct device *dev,
331 struct device_attribute *attr, char *buf)
332{
333 struct ad2s1210_state *st = iio_priv(dev_to_iio_dev(dev));
334
335 return sprintf(buf, "%d\n", st->resolution);
336}
337
338static ssize_t ad2s1210_store_resolution(struct device *dev,
339 struct device_attribute *attr,
340 const char *buf, size_t len)
341{
342 struct ad2s1210_state *st = iio_priv(dev_to_iio_dev(dev));
343 unsigned char data;
344 unsigned char udata;
345 int ret;
346
347 ret = kstrtou8(buf, 10, &udata);
348 if (ret || udata < 10 || udata > 16) {
349 pr_err("ad2s1210: resolution out of range\n");
350 return -EINVAL;
351 }
352 mutex_lock(&st->lock);
353 ret = ad2s1210_config_read(st, AD2S1210_REG_CONTROL);
354 if (ret < 0)
355 goto error_ret;
356 data = ret;
357 data &= ~AD2S1210_SET_RESOLUTION;
358 data |= (udata - 10) >> 1;
359 ret = ad2s1210_config_write(st, AD2S1210_REG_CONTROL);
360 if (ret < 0)
361 goto error_ret;
362 ret = ad2s1210_config_write(st, data & AD2S1210_MSB_IS_LOW);
363 if (ret < 0)
364 goto error_ret;
365 ret = ad2s1210_config_read(st, AD2S1210_REG_CONTROL);
366 if (ret < 0)
367 goto error_ret;
368 data = ret;
369 if (data & AD2S1210_MSB_IS_HIGH) {
370 ret = -EIO;
371 pr_err("ad2s1210: setting resolution fail\n");
372 goto error_ret;
373 }
374 st->resolution
375 = ad2s1210_resolution_value[data & AD2S1210_SET_RESOLUTION];
376 if (st->pdata->gpioin) {
377 data = ad2s1210_read_resolution_pin(st);
378 if (data != st->resolution)
379 pr_warn("ad2s1210: resolution settings not match\n");
380 } else
381 ad2s1210_set_resolution_pin(st);
382 ret = len;
383error_ret:
384 mutex_unlock(&st->lock);
385 return ret;
386}
387
388
389static ssize_t ad2s1210_show_fault(struct device *dev,
390 struct device_attribute *attr, char *buf)
391{
392 struct ad2s1210_state *st = iio_priv(dev_to_iio_dev(dev));
393 int ret;
394
395 mutex_lock(&st->lock);
396 ret = ad2s1210_config_read(st, AD2S1210_REG_FAULT);
397 mutex_unlock(&st->lock);
398
399 return ret ? ret : sprintf(buf, "0x%x\n", ret);
400}
401
402static ssize_t ad2s1210_clear_fault(struct device *dev,
403 struct device_attribute *attr,
404 const char *buf,
405 size_t len)
406{
407 struct ad2s1210_state *st = iio_priv(dev_to_iio_dev(dev));
408 int ret;
409
410 mutex_lock(&st->lock);
411 gpio_set_value(st->pdata->sample, 0);
412
413 udelay(1);
414 gpio_set_value(st->pdata->sample, 1);
415 ret = ad2s1210_config_read(st, AD2S1210_REG_FAULT);
416 if (ret < 0)
417 goto error_ret;
418 gpio_set_value(st->pdata->sample, 0);
419 gpio_set_value(st->pdata->sample, 1);
420error_ret:
421 mutex_unlock(&st->lock);
422
423 return ret < 0 ? ret : len;
424}
425
426static ssize_t ad2s1210_show_reg(struct device *dev,
427 struct device_attribute *attr,
428 char *buf)
429{
430 struct ad2s1210_state *st = iio_priv(dev_to_iio_dev(dev));
431 struct iio_dev_attr *iattr = to_iio_dev_attr(attr);
432 int ret;
433
434 mutex_lock(&st->lock);
435 ret = ad2s1210_config_read(st, iattr->address);
436 mutex_unlock(&st->lock);
437
438 return ret < 0 ? ret : sprintf(buf, "%d\n", ret);
439}
440
441static ssize_t ad2s1210_store_reg(struct device *dev,
442 struct device_attribute *attr, const char *buf, size_t len)
443{
444 struct ad2s1210_state *st = iio_priv(dev_to_iio_dev(dev));
445 unsigned char data;
446 int ret;
447 struct iio_dev_attr *iattr = to_iio_dev_attr(attr);
448
449 ret = kstrtou8(buf, 10, &data);
450 if (ret)
451 return -EINVAL;
452 mutex_lock(&st->lock);
453 ret = ad2s1210_config_write(st, iattr->address);
454 if (ret < 0)
455 goto error_ret;
456 ret = ad2s1210_config_write(st, data & AD2S1210_MSB_IS_LOW);
457error_ret:
458 mutex_unlock(&st->lock);
459 return ret < 0 ? ret : len;
460}
461
462static int ad2s1210_read_raw(struct iio_dev *indio_dev,
463 struct iio_chan_spec const *chan,
464 int *val,
465 int *val2,
466 long m)
467{
468 struct ad2s1210_state *st = iio_priv(indio_dev);
469 bool negative;
470 int ret = 0;
471 u16 pos;
472 s16 vel;
473
474 mutex_lock(&st->lock);
475 gpio_set_value(st->pdata->sample, 0);
476
477 udelay(1);
478
479 switch (chan->type) {
480 case IIO_ANGL:
481 ad2s1210_set_mode(MOD_POS, st);
482 break;
483 case IIO_ANGL_VEL:
484 ad2s1210_set_mode(MOD_VEL, st);
485 break;
486 default:
487 ret = -EINVAL;
488 break;
489 }
490 if (ret < 0)
491 goto error_ret;
492 ret = spi_read(st->sdev, st->rx, 2);
493 if (ret < 0)
494 goto error_ret;
495
496 switch (chan->type) {
497 case IIO_ANGL:
498 pos = be16_to_cpup((__be16 *) st->rx);
499 if (st->hysteresis)
500 pos >>= 16 - st->resolution;
501 *val = pos;
502 ret = IIO_VAL_INT;
503 break;
504 case IIO_ANGL_VEL:
505 negative = st->rx[0] & 0x80;
506 vel = be16_to_cpup((__be16 *) st->rx);
507 vel >>= 16 - st->resolution;
508 if (vel & 0x8000) {
509 negative = (0xffff >> st->resolution) << st->resolution;
510 vel |= negative;
511 }
512 *val = vel;
513 ret = IIO_VAL_INT;
514 break;
515 default:
516 mutex_unlock(&st->lock);
517 return -EINVAL;
518 }
519
520error_ret:
521 gpio_set_value(st->pdata->sample, 1);
522
523 udelay(1);
524 mutex_unlock(&st->lock);
525 return ret;
526}
527
528static IIO_DEVICE_ATTR(fclkin, S_IRUGO | S_IWUSR,
529 ad2s1210_show_fclkin, ad2s1210_store_fclkin, 0);
530static IIO_DEVICE_ATTR(fexcit, S_IRUGO | S_IWUSR,
531 ad2s1210_show_fexcit, ad2s1210_store_fexcit, 0);
532static IIO_DEVICE_ATTR(control, S_IRUGO | S_IWUSR,
533 ad2s1210_show_control, ad2s1210_store_control, 0);
534static IIO_DEVICE_ATTR(bits, S_IRUGO | S_IWUSR,
535 ad2s1210_show_resolution, ad2s1210_store_resolution, 0);
536static IIO_DEVICE_ATTR(fault, S_IRUGO | S_IWUSR,
537 ad2s1210_show_fault, ad2s1210_clear_fault, 0);
538
539static IIO_DEVICE_ATTR(los_thrd, S_IRUGO | S_IWUSR,
540 ad2s1210_show_reg, ad2s1210_store_reg,
541 AD2S1210_REG_LOS_THRD);
542static IIO_DEVICE_ATTR(dos_ovr_thrd, S_IRUGO | S_IWUSR,
543 ad2s1210_show_reg, ad2s1210_store_reg,
544 AD2S1210_REG_DOS_OVR_THRD);
545static IIO_DEVICE_ATTR(dos_mis_thrd, S_IRUGO | S_IWUSR,
546 ad2s1210_show_reg, ad2s1210_store_reg,
547 AD2S1210_REG_DOS_MIS_THRD);
548static IIO_DEVICE_ATTR(dos_rst_max_thrd, S_IRUGO | S_IWUSR,
549 ad2s1210_show_reg, ad2s1210_store_reg,
550 AD2S1210_REG_DOS_RST_MAX_THRD);
551static IIO_DEVICE_ATTR(dos_rst_min_thrd, S_IRUGO | S_IWUSR,
552 ad2s1210_show_reg, ad2s1210_store_reg,
553 AD2S1210_REG_DOS_RST_MIN_THRD);
554static IIO_DEVICE_ATTR(lot_high_thrd, S_IRUGO | S_IWUSR,
555 ad2s1210_show_reg, ad2s1210_store_reg,
556 AD2S1210_REG_LOT_HIGH_THRD);
557static IIO_DEVICE_ATTR(lot_low_thrd, S_IRUGO | S_IWUSR,
558 ad2s1210_show_reg, ad2s1210_store_reg,
559 AD2S1210_REG_LOT_LOW_THRD);
560
561
562static const struct iio_chan_spec ad2s1210_channels[] = {
563 {
564 .type = IIO_ANGL,
565 .indexed = 1,
566 .channel = 0,
567 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
568 }, {
569 .type = IIO_ANGL_VEL,
570 .indexed = 1,
571 .channel = 0,
572 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
573 }
574};
575
576static struct attribute *ad2s1210_attributes[] = {
577 &iio_dev_attr_fclkin.dev_attr.attr,
578 &iio_dev_attr_fexcit.dev_attr.attr,
579 &iio_dev_attr_control.dev_attr.attr,
580 &iio_dev_attr_bits.dev_attr.attr,
581 &iio_dev_attr_fault.dev_attr.attr,
582 &iio_dev_attr_los_thrd.dev_attr.attr,
583 &iio_dev_attr_dos_ovr_thrd.dev_attr.attr,
584 &iio_dev_attr_dos_mis_thrd.dev_attr.attr,
585 &iio_dev_attr_dos_rst_max_thrd.dev_attr.attr,
586 &iio_dev_attr_dos_rst_min_thrd.dev_attr.attr,
587 &iio_dev_attr_lot_high_thrd.dev_attr.attr,
588 &iio_dev_attr_lot_low_thrd.dev_attr.attr,
589 NULL,
590};
591
592static const struct attribute_group ad2s1210_attribute_group = {
593 .attrs = ad2s1210_attributes,
594};
595
596static int ad2s1210_initial(struct ad2s1210_state *st)
597{
598 unsigned char data;
599 int ret;
600
601 mutex_lock(&st->lock);
602 if (st->pdata->gpioin)
603 st->resolution = ad2s1210_read_resolution_pin(st);
604 else
605 ad2s1210_set_resolution_pin(st);
606
607 ret = ad2s1210_config_write(st, AD2S1210_REG_CONTROL);
608 if (ret < 0)
609 goto error_ret;
610 data = AD2S1210_DEF_CONTROL & ~(AD2S1210_SET_RESOLUTION);
611 data |= (st->resolution - 10) >> 1;
612 ret = ad2s1210_config_write(st, data);
613 if (ret < 0)
614 goto error_ret;
615 ret = ad2s1210_config_read(st, AD2S1210_REG_CONTROL);
616 if (ret < 0)
617 goto error_ret;
618
619 if (ret & AD2S1210_MSB_IS_HIGH) {
620 ret = -EIO;
621 goto error_ret;
622 }
623
624 ret = ad2s1210_update_frequency_control_word(st);
625 if (ret < 0)
626 goto error_ret;
627 ret = ad2s1210_soft_reset(st);
628error_ret:
629 mutex_unlock(&st->lock);
630 return ret;
631}
632
633static const struct iio_info ad2s1210_info = {
634 .read_raw = &ad2s1210_read_raw,
635 .attrs = &ad2s1210_attribute_group,
636 .driver_module = THIS_MODULE,
637};
638
639static int ad2s1210_setup_gpios(struct ad2s1210_state *st)
640{
641 unsigned long flags = st->pdata->gpioin ? GPIOF_DIR_IN : GPIOF_DIR_OUT;
642 struct gpio ad2s1210_gpios[] = {
643 { st->pdata->sample, GPIOF_DIR_IN, "sample" },
644 { st->pdata->a[0], flags, "a0" },
645 { st->pdata->a[1], flags, "a1" },
646 { st->pdata->res[0], flags, "res0" },
647 { st->pdata->res[0], flags, "res1" },
648 };
649
650 return gpio_request_array(ad2s1210_gpios, ARRAY_SIZE(ad2s1210_gpios));
651}
652
653static void ad2s1210_free_gpios(struct ad2s1210_state *st)
654{
655 unsigned long flags = st->pdata->gpioin ? GPIOF_DIR_IN : GPIOF_DIR_OUT;
656 struct gpio ad2s1210_gpios[] = {
657 { st->pdata->sample, GPIOF_DIR_IN, "sample" },
658 { st->pdata->a[0], flags, "a0" },
659 { st->pdata->a[1], flags, "a1" },
660 { st->pdata->res[0], flags, "res0" },
661 { st->pdata->res[0], flags, "res1" },
662 };
663
664 gpio_free_array(ad2s1210_gpios, ARRAY_SIZE(ad2s1210_gpios));
665}
666
667static int ad2s1210_probe(struct spi_device *spi)
668{
669 struct iio_dev *indio_dev;
670 struct ad2s1210_state *st;
671 int ret;
672
673 if (spi->dev.platform_data == NULL)
674 return -EINVAL;
675
676 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
677 if (!indio_dev)
678 return -ENOMEM;
679 st = iio_priv(indio_dev);
680 st->pdata = spi->dev.platform_data;
681 ret = ad2s1210_setup_gpios(st);
682 if (ret < 0)
683 return ret;
684
685 spi_set_drvdata(spi, indio_dev);
686
687 mutex_init(&st->lock);
688 st->sdev = spi;
689 st->hysteresis = true;
690 st->mode = MOD_CONFIG;
691 st->resolution = 12;
692 st->fexcit = AD2S1210_DEF_EXCIT;
693
694 indio_dev->dev.parent = &spi->dev;
695 indio_dev->info = &ad2s1210_info;
696 indio_dev->modes = INDIO_DIRECT_MODE;
697 indio_dev->channels = ad2s1210_channels;
698 indio_dev->num_channels = ARRAY_SIZE(ad2s1210_channels);
699 indio_dev->name = spi_get_device_id(spi)->name;
700
701 ret = iio_device_register(indio_dev);
702 if (ret)
703 goto error_free_gpios;
704
705 st->fclkin = spi->max_speed_hz;
706 spi->mode = SPI_MODE_3;
707 spi_setup(spi);
708 ad2s1210_initial(st);
709
710 return 0;
711
712error_free_gpios:
713 ad2s1210_free_gpios(st);
714 return ret;
715}
716
717static int ad2s1210_remove(struct spi_device *spi)
718{
719 struct iio_dev *indio_dev = spi_get_drvdata(spi);
720
721 iio_device_unregister(indio_dev);
722 ad2s1210_free_gpios(iio_priv(indio_dev));
723
724 return 0;
725}
726
727static const struct spi_device_id ad2s1210_id[] = {
728 { "ad2s1210" },
729 {}
730};
731MODULE_DEVICE_TABLE(spi, ad2s1210_id);
732
733static struct spi_driver ad2s1210_driver = {
734 .driver = {
735 .name = DRV_NAME,
736 .owner = THIS_MODULE,
737 },
738 .probe = ad2s1210_probe,
739 .remove = ad2s1210_remove,
740 .id_table = ad2s1210_id,
741};
742module_spi_driver(ad2s1210_driver);
743
744MODULE_AUTHOR("Graff Yang <graff.yang@gmail.com>");
745MODULE_DESCRIPTION("Analog Devices AD2S1210 Resolver to Digital SPI driver");
746MODULE_LICENSE("GPL v2");
747
