linux/drivers/usb/gadget/udc/mv_u3d_core.c
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   1/*
   2 * Copyright (C) 2011 Marvell International Ltd. All rights reserved.
   3 *
   4 * This program is free software; you can redistribute it and/or modify it
   5 * under the terms and conditions of the GNU General Public License,
   6 * version 2, as published by the Free Software Foundation.
   7 */
   8
   9#include <linux/module.h>
  10#include <linux/dma-mapping.h>
  11#include <linux/dmapool.h>
  12#include <linux/kernel.h>
  13#include <linux/delay.h>
  14#include <linux/ioport.h>
  15#include <linux/sched.h>
  16#include <linux/slab.h>
  17#include <linux/errno.h>
  18#include <linux/timer.h>
  19#include <linux/list.h>
  20#include <linux/notifier.h>
  21#include <linux/interrupt.h>
  22#include <linux/moduleparam.h>
  23#include <linux/device.h>
  24#include <linux/usb/ch9.h>
  25#include <linux/usb/gadget.h>
  26#include <linux/pm.h>
  27#include <linux/io.h>
  28#include <linux/irq.h>
  29#include <linux/platform_device.h>
  30#include <linux/platform_data/mv_usb.h>
  31#include <linux/clk.h>
  32
  33#include "mv_u3d.h"
  34
  35#define DRIVER_DESC             "Marvell PXA USB3.0 Device Controller driver"
  36
  37static const char driver_name[] = "mv_u3d";
  38static const char driver_desc[] = DRIVER_DESC;
  39
  40static void mv_u3d_nuke(struct mv_u3d_ep *ep, int status);
  41static void mv_u3d_stop_activity(struct mv_u3d *u3d,
  42                        struct usb_gadget_driver *driver);
  43
  44/* for endpoint 0 operations */
  45static const struct usb_endpoint_descriptor mv_u3d_ep0_desc = {
  46        .bLength =              USB_DT_ENDPOINT_SIZE,
  47        .bDescriptorType =      USB_DT_ENDPOINT,
  48        .bEndpointAddress =     0,
  49        .bmAttributes =         USB_ENDPOINT_XFER_CONTROL,
  50        .wMaxPacketSize =       MV_U3D_EP0_MAX_PKT_SIZE,
  51};
  52
  53static void mv_u3d_ep0_reset(struct mv_u3d *u3d)
  54{
  55        struct mv_u3d_ep *ep;
  56        u32 epxcr;
  57        int i;
  58
  59        for (i = 0; i < 2; i++) {
  60                ep = &u3d->eps[i];
  61                ep->u3d = u3d;
  62
  63                /* ep0 ep context, ep0 in and out share the same ep context */
  64                ep->ep_context = &u3d->ep_context[1];
  65        }
  66
  67        /* reset ep state machine */
  68        /* reset ep0 out */
  69        epxcr = ioread32(&u3d->vuc_regs->epcr[0].epxoutcr0);
  70        epxcr |= MV_U3D_EPXCR_EP_INIT;
  71        iowrite32(epxcr, &u3d->vuc_regs->epcr[0].epxoutcr0);
  72        udelay(5);
  73        epxcr &= ~MV_U3D_EPXCR_EP_INIT;
  74        iowrite32(epxcr, &u3d->vuc_regs->epcr[0].epxoutcr0);
  75
  76        epxcr = ((MV_U3D_EP0_MAX_PKT_SIZE
  77                << MV_U3D_EPXCR_MAX_PACKET_SIZE_SHIFT)
  78                | (1 << MV_U3D_EPXCR_MAX_BURST_SIZE_SHIFT)
  79                | (1 << MV_U3D_EPXCR_EP_ENABLE_SHIFT)
  80                | MV_U3D_EPXCR_EP_TYPE_CONTROL);
  81        iowrite32(epxcr, &u3d->vuc_regs->epcr[0].epxoutcr1);
  82
  83        /* reset ep0 in */
  84        epxcr = ioread32(&u3d->vuc_regs->epcr[0].epxincr0);
  85        epxcr |= MV_U3D_EPXCR_EP_INIT;
  86        iowrite32(epxcr, &u3d->vuc_regs->epcr[0].epxincr0);
  87        udelay(5);
  88        epxcr &= ~MV_U3D_EPXCR_EP_INIT;
  89        iowrite32(epxcr, &u3d->vuc_regs->epcr[0].epxincr0);
  90
  91        epxcr = ((MV_U3D_EP0_MAX_PKT_SIZE
  92                << MV_U3D_EPXCR_MAX_PACKET_SIZE_SHIFT)
  93                | (1 << MV_U3D_EPXCR_MAX_BURST_SIZE_SHIFT)
  94                | (1 << MV_U3D_EPXCR_EP_ENABLE_SHIFT)
  95                | MV_U3D_EPXCR_EP_TYPE_CONTROL);
  96        iowrite32(epxcr, &u3d->vuc_regs->epcr[0].epxincr1);
  97}
  98
  99static void mv_u3d_ep0_stall(struct mv_u3d *u3d)
 100{
 101        u32 tmp;
 102        dev_dbg(u3d->dev, "%s\n", __func__);
 103
 104        /* set TX and RX to stall */
 105        tmp = ioread32(&u3d->vuc_regs->epcr[0].epxoutcr0);
 106        tmp |= MV_U3D_EPXCR_EP_HALT;
 107        iowrite32(tmp, &u3d->vuc_regs->epcr[0].epxoutcr0);
 108
 109        tmp = ioread32(&u3d->vuc_regs->epcr[0].epxincr0);
 110        tmp |= MV_U3D_EPXCR_EP_HALT;
 111        iowrite32(tmp, &u3d->vuc_regs->epcr[0].epxincr0);
 112
 113        /* update ep0 state */
 114        u3d->ep0_state = MV_U3D_WAIT_FOR_SETUP;
 115        u3d->ep0_dir = MV_U3D_EP_DIR_OUT;
 116}
 117
 118static int mv_u3d_process_ep_req(struct mv_u3d *u3d, int index,
 119        struct mv_u3d_req *curr_req)
 120{
 121        struct mv_u3d_trb       *curr_trb;
 122        dma_addr_t cur_deq_lo;
 123        struct mv_u3d_ep_context        *curr_ep_context;
 124        int trb_complete, actual, remaining_length = 0;
 125        int direction, ep_num;
 126        int retval = 0;
 127        u32 tmp, status, length;
 128
 129        curr_ep_context = &u3d->ep_context[index];
 130        direction = index % 2;
 131        ep_num = index / 2;
 132
 133        trb_complete = 0;
 134        actual = curr_req->req.length;
 135
 136        while (!list_empty(&curr_req->trb_list)) {
 137                curr_trb = list_entry(curr_req->trb_list.next,
 138                                        struct mv_u3d_trb, trb_list);
 139                if (!curr_trb->trb_hw->ctrl.own) {
 140                        dev_err(u3d->dev, "%s, TRB own error!\n",
 141                                u3d->eps[index].name);
 142                        return 1;
 143                }
 144
 145                curr_trb->trb_hw->ctrl.own = 0;
 146                if (direction == MV_U3D_EP_DIR_OUT) {
 147                        tmp = ioread32(&u3d->vuc_regs->rxst[ep_num].statuslo);
 148                        cur_deq_lo =
 149                                ioread32(&u3d->vuc_regs->rxst[ep_num].curdeqlo);
 150                } else {
 151                        tmp = ioread32(&u3d->vuc_regs->txst[ep_num].statuslo);
 152                        cur_deq_lo =
 153                                ioread32(&u3d->vuc_regs->txst[ep_num].curdeqlo);
 154                }
 155
 156                status = tmp >> MV_U3D_XFERSTATUS_COMPLETE_SHIFT;
 157                length = tmp & MV_U3D_XFERSTATUS_TRB_LENGTH_MASK;
 158
 159                if (status == MV_U3D_COMPLETE_SUCCESS ||
 160                        (status == MV_U3D_COMPLETE_SHORT_PACKET &&
 161                        direction == MV_U3D_EP_DIR_OUT)) {
 162                        remaining_length += length;
 163                        actual -= remaining_length;
 164                } else {
 165                        dev_err(u3d->dev,
 166                                "complete_tr error: ep=%d %s: error = 0x%x\n",
 167                                index >> 1, direction ? "SEND" : "RECV",
 168                                status);
 169                        retval = -EPROTO;
 170                }
 171
 172                list_del_init(&curr_trb->trb_list);
 173        }
 174        if (retval)
 175                return retval;
 176
 177        curr_req->req.actual = actual;
 178        return 0;
 179}
 180
 181/*
 182 * mv_u3d_done() - retire a request; caller blocked irqs
 183 * @status : request status to be set, only works when
 184 * request is still in progress.
 185 */
 186static
 187void mv_u3d_done(struct mv_u3d_ep *ep, struct mv_u3d_req *req, int status)
 188        __releases(&ep->udc->lock)
 189        __acquires(&ep->udc->lock)
 190{
 191        struct mv_u3d *u3d = (struct mv_u3d *)ep->u3d;
 192
 193        dev_dbg(u3d->dev, "mv_u3d_done: remove req->queue\n");
 194        /* Removed the req from ep queue */
 195        list_del_init(&req->queue);
 196
 197        /* req.status should be set as -EINPROGRESS in ep_queue() */
 198        if (req->req.status == -EINPROGRESS)
 199                req->req.status = status;
 200        else
 201                status = req->req.status;
 202
 203        /* Free trb for the request */
 204        if (!req->chain)
 205                dma_pool_free(u3d->trb_pool,
 206                        req->trb_head->trb_hw, req->trb_head->trb_dma);
 207        else {
 208                dma_unmap_single(ep->u3d->gadget.dev.parent,
 209                        (dma_addr_t)req->trb_head->trb_dma,
 210                        req->trb_count * sizeof(struct mv_u3d_trb_hw),
 211                        DMA_BIDIRECTIONAL);
 212                kfree(req->trb_head->trb_hw);
 213        }
 214        kfree(req->trb_head);
 215
 216        usb_gadget_unmap_request(&u3d->gadget, &req->req, mv_u3d_ep_dir(ep));
 217
 218        if (status && (status != -ESHUTDOWN)) {
 219                dev_dbg(u3d->dev, "complete %s req %p stat %d len %u/%u",
 220                        ep->ep.name, &req->req, status,
 221                        req->req.actual, req->req.length);
 222        }
 223
 224        spin_unlock(&ep->u3d->lock);
 225
 226        usb_gadget_giveback_request(&ep->ep, &req->req);
 227
 228        spin_lock(&ep->u3d->lock);
 229}
 230
 231static int mv_u3d_queue_trb(struct mv_u3d_ep *ep, struct mv_u3d_req *req)
 232{
 233        u32 tmp, direction;
 234        struct mv_u3d *u3d;
 235        struct mv_u3d_ep_context *ep_context;
 236        int retval = 0;
 237
 238        u3d = ep->u3d;
 239        direction = mv_u3d_ep_dir(ep);
 240
 241        /* ep0 in and out share the same ep context slot 1*/
 242        if (ep->ep_num == 0)
 243                ep_context = &(u3d->ep_context[1]);
 244        else
 245                ep_context = &(u3d->ep_context[ep->ep_num * 2 + direction]);
 246
 247        /* check if the pipe is empty or not */
 248        if (!list_empty(&ep->queue)) {
 249                dev_err(u3d->dev, "add trb to non-empty queue!\n");
 250                retval = -ENOMEM;
 251                WARN_ON(1);
 252        } else {
 253                ep_context->rsvd0 = cpu_to_le32(1);
 254                ep_context->rsvd1 = 0;
 255
 256                /* Configure the trb address and set the DCS bit.
 257                 * Both DCS bit and own bit in trb should be set.
 258                 */
 259                ep_context->trb_addr_lo =
 260                        cpu_to_le32(req->trb_head->trb_dma | DCS_ENABLE);
 261                ep_context->trb_addr_hi = 0;
 262
 263                /* Ensure that updates to the EP Context will
 264                 * occure before Ring Bell.
 265                 */
 266                wmb();
 267
 268                /* ring bell the ep */
 269                if (ep->ep_num == 0)
 270                        tmp = 0x1;
 271                else
 272                        tmp = ep->ep_num * 2
 273                                + ((direction == MV_U3D_EP_DIR_OUT) ? 0 : 1);
 274
 275                iowrite32(tmp, &u3d->op_regs->doorbell);
 276        }
 277        return retval;
 278}
 279
 280static struct mv_u3d_trb *mv_u3d_build_trb_one(struct mv_u3d_req *req,
 281                                unsigned *length, dma_addr_t *dma)
 282{
 283        u32 temp;
 284        unsigned int direction;
 285        struct mv_u3d_trb *trb;
 286        struct mv_u3d_trb_hw *trb_hw;
 287        struct mv_u3d *u3d;
 288
 289        /* how big will this transfer be? */
 290        *length = req->req.length - req->req.actual;
 291        BUG_ON(*length > (unsigned)MV_U3D_EP_MAX_LENGTH_TRANSFER);
 292
 293        u3d = req->ep->u3d;
 294
 295        trb = kzalloc(sizeof(*trb), GFP_ATOMIC);
 296        if (!trb)
 297                return NULL;
 298
 299        /*
 300         * Be careful that no _GFP_HIGHMEM is set,
 301         * or we can not use dma_to_virt
 302         * cannot use GFP_KERNEL in spin lock
 303         */
 304        trb_hw = dma_pool_alloc(u3d->trb_pool, GFP_ATOMIC, dma);
 305        if (!trb_hw) {
 306                kfree(trb);
 307                dev_err(u3d->dev,
 308                        "%s, dma_pool_alloc fail\n", __func__);
 309                return NULL;
 310        }
 311        trb->trb_dma = *dma;
 312        trb->trb_hw = trb_hw;
 313
 314        /* initialize buffer page pointers */
 315        temp = (u32)(req->req.dma + req->req.actual);
 316
 317        trb_hw->buf_addr_lo = cpu_to_le32(temp);
 318        trb_hw->buf_addr_hi = 0;
 319        trb_hw->trb_len = cpu_to_le32(*length);
 320        trb_hw->ctrl.own = 1;
 321
 322        if (req->ep->ep_num == 0)
 323                trb_hw->ctrl.type = TYPE_DATA;
 324        else
 325                trb_hw->ctrl.type = TYPE_NORMAL;
 326
 327        req->req.actual += *length;
 328
 329        direction = mv_u3d_ep_dir(req->ep);
 330        if (direction == MV_U3D_EP_DIR_IN)
 331                trb_hw->ctrl.dir = 1;
 332        else
 333                trb_hw->ctrl.dir = 0;
 334
 335        /* Enable interrupt for the last trb of a request */
 336        if (!req->req.no_interrupt)
 337                trb_hw->ctrl.ioc = 1;
 338
 339        trb_hw->ctrl.chain = 0;
 340
 341        wmb();
 342        return trb;
 343}
 344
 345static int mv_u3d_build_trb_chain(struct mv_u3d_req *req, unsigned *length,
 346                struct mv_u3d_trb *trb, int *is_last)
 347{
 348        u32 temp;
 349        unsigned int direction;
 350        struct mv_u3d *u3d;
 351
 352        /* how big will this transfer be? */
 353        *length = min(req->req.length - req->req.actual,
 354                        (unsigned)MV_U3D_EP_MAX_LENGTH_TRANSFER);
 355
 356        u3d = req->ep->u3d;
 357
 358        trb->trb_dma = 0;
 359
 360        /* initialize buffer page pointers */
 361        temp = (u32)(req->req.dma + req->req.actual);
 362
 363        trb->trb_hw->buf_addr_lo = cpu_to_le32(temp);
 364        trb->trb_hw->buf_addr_hi = 0;
 365        trb->trb_hw->trb_len = cpu_to_le32(*length);
 366        trb->trb_hw->ctrl.own = 1;
 367
 368        if (req->ep->ep_num == 0)
 369                trb->trb_hw->ctrl.type = TYPE_DATA;
 370        else
 371                trb->trb_hw->ctrl.type = TYPE_NORMAL;
 372
 373        req->req.actual += *length;
 374
 375        direction = mv_u3d_ep_dir(req->ep);
 376        if (direction == MV_U3D_EP_DIR_IN)
 377                trb->trb_hw->ctrl.dir = 1;
 378        else
 379                trb->trb_hw->ctrl.dir = 0;
 380
 381        /* zlp is needed if req->req.zero is set */
 382        if (req->req.zero) {
 383                if (*length == 0 || (*length % req->ep->ep.maxpacket) != 0)
 384                        *is_last = 1;
 385                else
 386                        *is_last = 0;
 387        } else if (req->req.length == req->req.actual)
 388                *is_last = 1;
 389        else
 390                *is_last = 0;
 391
 392        /* Enable interrupt for the last trb of a request */
 393        if (*is_last && !req->req.no_interrupt)
 394                trb->trb_hw->ctrl.ioc = 1;
 395
 396        if (*is_last)
 397                trb->trb_hw->ctrl.chain = 0;
 398        else {
 399                trb->trb_hw->ctrl.chain = 1;
 400                dev_dbg(u3d->dev, "chain trb\n");
 401        }
 402
 403        wmb();
 404
 405        return 0;
 406}
 407
 408/* generate TRB linked list for a request
 409 * usb controller only supports continous trb chain,
 410 * that trb structure physical address should be continous.
 411 */
 412static int mv_u3d_req_to_trb(struct mv_u3d_req *req)
 413{
 414        unsigned count;
 415        int is_last;
 416        struct mv_u3d_trb *trb;
 417        struct mv_u3d_trb_hw *trb_hw;
 418        struct mv_u3d *u3d;
 419        dma_addr_t dma;
 420        unsigned length;
 421        unsigned trb_num;
 422
 423        u3d = req->ep->u3d;
 424
 425        INIT_LIST_HEAD(&req->trb_list);
 426
 427        length = req->req.length - req->req.actual;
 428        /* normally the request transfer length is less than 16KB.
 429         * we use buil_trb_one() to optimize it.
 430         */
 431        if (length <= (unsigned)MV_U3D_EP_MAX_LENGTH_TRANSFER) {
 432                trb = mv_u3d_build_trb_one(req, &count, &dma);
 433                list_add_tail(&trb->trb_list, &req->trb_list);
 434                req->trb_head = trb;
 435                req->trb_count = 1;
 436                req->chain = 0;
 437        } else {
 438                trb_num = length / MV_U3D_EP_MAX_LENGTH_TRANSFER;
 439                if (length % MV_U3D_EP_MAX_LENGTH_TRANSFER)
 440                        trb_num++;
 441
 442                trb = kcalloc(trb_num, sizeof(*trb), GFP_ATOMIC);
 443                if (!trb)
 444                        return -ENOMEM;
 445
 446                trb_hw = kcalloc(trb_num, sizeof(*trb_hw), GFP_ATOMIC);
 447                if (!trb_hw) {
 448                        kfree(trb);
 449                        return -ENOMEM;
 450                }
 451
 452                do {
 453                        trb->trb_hw = trb_hw;
 454                        if (mv_u3d_build_trb_chain(req, &count,
 455                                                trb, &is_last)) {
 456                                dev_err(u3d->dev,
 457                                        "%s, mv_u3d_build_trb_chain fail\n",
 458                                        __func__);
 459                                return -EIO;
 460                        }
 461
 462                        list_add_tail(&trb->trb_list, &req->trb_list);
 463                        req->trb_count++;
 464                        trb++;
 465                        trb_hw++;
 466                } while (!is_last);
 467
 468                req->trb_head = list_entry(req->trb_list.next,
 469                                        struct mv_u3d_trb, trb_list);
 470                req->trb_head->trb_dma = dma_map_single(u3d->gadget.dev.parent,
 471                                        req->trb_head->trb_hw,
 472                                        trb_num * sizeof(*trb_hw),
 473                                        DMA_BIDIRECTIONAL);
 474
 475                req->chain = 1;
 476        }
 477
 478        return 0;
 479}
 480
 481static int
 482mv_u3d_start_queue(struct mv_u3d_ep *ep)
 483{
 484        struct mv_u3d *u3d = ep->u3d;
 485        struct mv_u3d_req *req;
 486        int ret;
 487
 488        if (!list_empty(&ep->req_list) && !ep->processing)
 489                req = list_entry(ep->req_list.next, struct mv_u3d_req, list);
 490        else
 491                return 0;
 492
 493        ep->processing = 1;
 494
 495        /* set up dma mapping */
 496        ret = usb_gadget_map_request(&u3d->gadget, &req->req,
 497                                        mv_u3d_ep_dir(ep));
 498        if (ret)
 499                return ret;
 500
 501        req->req.status = -EINPROGRESS;
 502        req->req.actual = 0;
 503        req->trb_count = 0;
 504
 505        /* build trbs and push them to device queue */
 506        if (!mv_u3d_req_to_trb(req)) {
 507                ret = mv_u3d_queue_trb(ep, req);
 508                if (ret) {
 509                        ep->processing = 0;
 510                        return ret;
 511                }
 512        } else {
 513                ep->processing = 0;
 514                dev_err(u3d->dev, "%s, mv_u3d_req_to_trb fail\n", __func__);
 515                return -ENOMEM;
 516        }
 517
 518        /* irq handler advances the queue */
 519        if (req)
 520                list_add_tail(&req->queue, &ep->queue);
 521
 522        return 0;
 523}
 524
 525static int mv_u3d_ep_enable(struct usb_ep *_ep,
 526                const struct usb_endpoint_descriptor *desc)
 527{
 528        struct mv_u3d *u3d;
 529        struct mv_u3d_ep *ep;
 530        struct mv_u3d_ep_context *ep_context;
 531        u16 max = 0;
 532        unsigned maxburst = 0;
 533        u32 epxcr, direction;
 534
 535        if (!_ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT)
 536                return -EINVAL;
 537
 538        ep = container_of(_ep, struct mv_u3d_ep, ep);
 539        u3d = ep->u3d;
 540
 541        if (!u3d->driver || u3d->gadget.speed == USB_SPEED_UNKNOWN)
 542                return -ESHUTDOWN;
 543
 544        direction = mv_u3d_ep_dir(ep);
 545        max = le16_to_cpu(desc->wMaxPacketSize);
 546
 547        if (!_ep->maxburst)
 548                _ep->maxburst = 1;
 549        maxburst = _ep->maxburst;
 550
 551        /* Get the endpoint context address */
 552        ep_context = (struct mv_u3d_ep_context *)ep->ep_context;
 553
 554        /* Set the max burst size */
 555        switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
 556        case USB_ENDPOINT_XFER_BULK:
 557                if (maxburst > 16) {
 558                        dev_dbg(u3d->dev,
 559                                "max burst should not be greater "
 560                                "than 16 on bulk ep\n");
 561                        maxburst = 1;
 562                        _ep->maxburst = maxburst;
 563                }
 564                dev_dbg(u3d->dev,
 565                        "maxburst: %d on bulk %s\n", maxburst, ep->name);
 566                break;
 567        case USB_ENDPOINT_XFER_CONTROL:
 568                /* control transfer only supports maxburst as one */
 569                maxburst = 1;
 570                _ep->maxburst = maxburst;
 571                break;
 572        case USB_ENDPOINT_XFER_INT:
 573                if (maxburst != 1) {
 574                        dev_dbg(u3d->dev,
 575                                "max burst should be 1 on int ep "
 576                                "if transfer size is not 1024\n");
 577                        maxburst = 1;
 578                        _ep->maxburst = maxburst;
 579                }
 580                break;
 581        case USB_ENDPOINT_XFER_ISOC:
 582                if (maxburst != 1) {
 583                        dev_dbg(u3d->dev,
 584                                "max burst should be 1 on isoc ep "
 585                                "if transfer size is not 1024\n");
 586                        maxburst = 1;
 587                        _ep->maxburst = maxburst;
 588                }
 589                break;
 590        default:
 591                goto en_done;
 592        }
 593
 594        ep->ep.maxpacket = max;
 595        ep->ep.desc = desc;
 596        ep->enabled = 1;
 597
 598        /* Enable the endpoint for Rx or Tx and set the endpoint type */
 599        if (direction == MV_U3D_EP_DIR_OUT) {
 600                epxcr = ioread32(&u3d->vuc_regs->epcr[ep->ep_num].epxoutcr0);
 601                epxcr |= MV_U3D_EPXCR_EP_INIT;
 602                iowrite32(epxcr, &u3d->vuc_regs->epcr[ep->ep_num].epxoutcr0);
 603                udelay(5);
 604                epxcr &= ~MV_U3D_EPXCR_EP_INIT;
 605                iowrite32(epxcr, &u3d->vuc_regs->epcr[ep->ep_num].epxoutcr0);
 606
 607                epxcr = ((max << MV_U3D_EPXCR_MAX_PACKET_SIZE_SHIFT)
 608                      | ((maxburst - 1) << MV_U3D_EPXCR_MAX_BURST_SIZE_SHIFT)
 609                      | (1 << MV_U3D_EPXCR_EP_ENABLE_SHIFT)
 610                      | (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK));
 611                iowrite32(epxcr, &u3d->vuc_regs->epcr[ep->ep_num].epxoutcr1);
 612        } else {
 613                epxcr = ioread32(&u3d->vuc_regs->epcr[ep->ep_num].epxincr0);
 614                epxcr |= MV_U3D_EPXCR_EP_INIT;
 615                iowrite32(epxcr, &u3d->vuc_regs->epcr[ep->ep_num].epxincr0);
 616                udelay(5);
 617                epxcr &= ~MV_U3D_EPXCR_EP_INIT;
 618                iowrite32(epxcr, &u3d->vuc_regs->epcr[ep->ep_num].epxincr0);
 619
 620                epxcr = ((max << MV_U3D_EPXCR_MAX_PACKET_SIZE_SHIFT)
 621                      | ((maxburst - 1) << MV_U3D_EPXCR_MAX_BURST_SIZE_SHIFT)
 622                      | (1 << MV_U3D_EPXCR_EP_ENABLE_SHIFT)
 623                      | (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK));
 624                iowrite32(epxcr, &u3d->vuc_regs->epcr[ep->ep_num].epxincr1);
 625        }
 626
 627        return 0;
 628en_done:
 629        return -EINVAL;
 630}
 631
 632static int  mv_u3d_ep_disable(struct usb_ep *_ep)
 633{
 634        struct mv_u3d *u3d;
 635        struct mv_u3d_ep *ep;
 636        struct mv_u3d_ep_context *ep_context;
 637        u32 epxcr, direction;
 638        unsigned long flags;
 639
 640        if (!_ep)
 641                return -EINVAL;
 642
 643        ep = container_of(_ep, struct mv_u3d_ep, ep);
 644        if (!ep->ep.desc)
 645                return -EINVAL;
 646
 647        u3d = ep->u3d;
 648
 649        /* Get the endpoint context address */
 650        ep_context = ep->ep_context;
 651
 652        direction = mv_u3d_ep_dir(ep);
 653
 654        /* nuke all pending requests (does flush) */
 655        spin_lock_irqsave(&u3d->lock, flags);
 656        mv_u3d_nuke(ep, -ESHUTDOWN);
 657        spin_unlock_irqrestore(&u3d->lock, flags);
 658
 659        /* Disable the endpoint for Rx or Tx and reset the endpoint type */
 660        if (direction == MV_U3D_EP_DIR_OUT) {
 661                epxcr = ioread32(&u3d->vuc_regs->epcr[ep->ep_num].epxoutcr1);
 662                epxcr &= ~((1 << MV_U3D_EPXCR_EP_ENABLE_SHIFT)
 663                      | USB_ENDPOINT_XFERTYPE_MASK);
 664                iowrite32(epxcr, &u3d->vuc_regs->epcr[ep->ep_num].epxoutcr1);
 665        } else {
 666                epxcr = ioread32(&u3d->vuc_regs->epcr[ep->ep_num].epxincr1);
 667                epxcr &= ~((1 << MV_U3D_EPXCR_EP_ENABLE_SHIFT)
 668                      | USB_ENDPOINT_XFERTYPE_MASK);
 669                iowrite32(epxcr, &u3d->vuc_regs->epcr[ep->ep_num].epxincr1);
 670        }
 671
 672        ep->enabled = 0;
 673
 674        ep->ep.desc = NULL;
 675        return 0;
 676}
 677
 678static struct usb_request *
 679mv_u3d_alloc_request(struct usb_ep *_ep, gfp_t gfp_flags)
 680{
 681        struct mv_u3d_req *req = NULL;
 682
 683        req = kzalloc(sizeof *req, gfp_flags);
 684        if (!req)
 685                return NULL;
 686
 687        INIT_LIST_HEAD(&req->queue);
 688
 689        return &req->req;
 690}
 691
 692static void mv_u3d_free_request(struct usb_ep *_ep, struct usb_request *_req)
 693{
 694        struct mv_u3d_req *req = container_of(_req, struct mv_u3d_req, req);
 695
 696        kfree(req);
 697}
 698
 699static void mv_u3d_ep_fifo_flush(struct usb_ep *_ep)
 700{
 701        struct mv_u3d *u3d;
 702        u32 direction;
 703        struct mv_u3d_ep *ep = container_of(_ep, struct mv_u3d_ep, ep);
 704        unsigned int loops;
 705        u32 tmp;
 706
 707        /* if endpoint is not enabled, cannot flush endpoint */
 708        if (!ep->enabled)
 709                return;
 710
 711        u3d = ep->u3d;
 712        direction = mv_u3d_ep_dir(ep);
 713
 714        /* ep0 need clear bit after flushing fifo. */
 715        if (!ep->ep_num) {
 716                if (direction == MV_U3D_EP_DIR_OUT) {
 717                        tmp = ioread32(&u3d->vuc_regs->epcr[0].epxoutcr0);
 718                        tmp |= MV_U3D_EPXCR_EP_FLUSH;
 719                        iowrite32(tmp, &u3d->vuc_regs->epcr[0].epxoutcr0);
 720                        udelay(10);
 721                        tmp &= ~MV_U3D_EPXCR_EP_FLUSH;
 722                        iowrite32(tmp, &u3d->vuc_regs->epcr[0].epxoutcr0);
 723                } else {
 724                        tmp = ioread32(&u3d->vuc_regs->epcr[0].epxincr0);
 725                        tmp |= MV_U3D_EPXCR_EP_FLUSH;
 726                        iowrite32(tmp, &u3d->vuc_regs->epcr[0].epxincr0);
 727                        udelay(10);
 728                        tmp &= ~MV_U3D_EPXCR_EP_FLUSH;
 729                        iowrite32(tmp, &u3d->vuc_regs->epcr[0].epxincr0);
 730                }
 731                return;
 732        }
 733
 734        if (direction == MV_U3D_EP_DIR_OUT) {
 735                tmp = ioread32(&u3d->vuc_regs->epcr[ep->ep_num].epxoutcr0);
 736                tmp |= MV_U3D_EPXCR_EP_FLUSH;
 737                iowrite32(tmp, &u3d->vuc_regs->epcr[ep->ep_num].epxoutcr0);
 738
 739                /* Wait until flushing completed */
 740                loops = LOOPS(MV_U3D_FLUSH_TIMEOUT);
 741                while (ioread32(&u3d->vuc_regs->epcr[ep->ep_num].epxoutcr0) &
 742                        MV_U3D_EPXCR_EP_FLUSH) {
 743                        /*
 744                         * EP_FLUSH bit should be cleared to indicate this
 745                         * operation is complete
 746                         */
 747                        if (loops == 0) {
 748                                dev_dbg(u3d->dev,
 749                                    "EP FLUSH TIMEOUT for ep%d%s\n", ep->ep_num,
 750                                    direction ? "in" : "out");
 751                                return;
 752                        }
 753                        loops--;
 754                        udelay(LOOPS_USEC);
 755                }
 756        } else {        /* EP_DIR_IN */
 757                tmp = ioread32(&u3d->vuc_regs->epcr[ep->ep_num].epxincr0);
 758                tmp |= MV_U3D_EPXCR_EP_FLUSH;
 759                iowrite32(tmp, &u3d->vuc_regs->epcr[ep->ep_num].epxincr0);
 760
 761                /* Wait until flushing completed */
 762                loops = LOOPS(MV_U3D_FLUSH_TIMEOUT);
 763                while (ioread32(&u3d->vuc_regs->epcr[ep->ep_num].epxincr0) &
 764                        MV_U3D_EPXCR_EP_FLUSH) {
 765                        /*
 766                        * EP_FLUSH bit should be cleared to indicate this
 767                        * operation is complete
 768                        */
 769                        if (loops == 0) {
 770                                dev_dbg(u3d->dev,
 771                                    "EP FLUSH TIMEOUT for ep%d%s\n", ep->ep_num,
 772                                    direction ? "in" : "out");
 773                                return;
 774                        }
 775                        loops--;
 776                        udelay(LOOPS_USEC);
 777                }
 778        }
 779}
 780
 781/* queues (submits) an I/O request to an endpoint */
 782static int
 783mv_u3d_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
 784{
 785        struct mv_u3d_ep *ep;
 786        struct mv_u3d_req *req;
 787        struct mv_u3d *u3d;
 788        unsigned long flags;
 789        int is_first_req = 0;
 790
 791        if (unlikely(!_ep || !_req))
 792                return -EINVAL;
 793
 794        ep = container_of(_ep, struct mv_u3d_ep, ep);
 795        u3d = ep->u3d;
 796
 797        req = container_of(_req, struct mv_u3d_req, req);
 798
 799        if (!ep->ep_num
 800                && u3d->ep0_state == MV_U3D_STATUS_STAGE
 801                && !_req->length) {
 802                dev_dbg(u3d->dev, "ep0 status stage\n");
 803                u3d->ep0_state = MV_U3D_WAIT_FOR_SETUP;
 804                return 0;
 805        }
 806
 807        dev_dbg(u3d->dev, "%s: %s, req: 0x%p\n",
 808                        __func__, _ep->name, req);
 809
 810        /* catch various bogus parameters */
 811        if (!req->req.complete || !req->req.buf
 812                        || !list_empty(&req->queue)) {
 813                dev_err(u3d->dev,
 814                        "%s, bad params, _req: 0x%p,"
 815                        "req->req.complete: 0x%p, req->req.buf: 0x%p,"
 816                        "list_empty: 0x%x\n",
 817                        __func__, _req,
 818                        req->req.complete, req->req.buf,
 819                        list_empty(&req->queue));
 820                return -EINVAL;
 821        }
 822        if (unlikely(!ep->ep.desc)) {
 823                dev_err(u3d->dev, "%s, bad ep\n", __func__);
 824                return -EINVAL;
 825        }
 826        if (ep->ep.desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
 827                if (req->req.length > ep->ep.maxpacket)
 828                        return -EMSGSIZE;
 829        }
 830
 831        if (!u3d->driver || u3d->gadget.speed == USB_SPEED_UNKNOWN) {
 832                dev_err(u3d->dev,
 833                        "bad params of driver/speed\n");
 834                return -ESHUTDOWN;
 835        }
 836
 837        req->ep = ep;
 838
 839        /* Software list handles usb request. */
 840        spin_lock_irqsave(&ep->req_lock, flags);
 841        is_first_req = list_empty(&ep->req_list);
 842        list_add_tail(&req->list, &ep->req_list);
 843        spin_unlock_irqrestore(&ep->req_lock, flags);
 844        if (!is_first_req) {
 845                dev_dbg(u3d->dev, "list is not empty\n");
 846                return 0;
 847        }
 848
 849        dev_dbg(u3d->dev, "call mv_u3d_start_queue from usb_ep_queue\n");
 850        spin_lock_irqsave(&u3d->lock, flags);
 851        mv_u3d_start_queue(ep);
 852        spin_unlock_irqrestore(&u3d->lock, flags);
 853        return 0;
 854}
 855
 856/* dequeues (cancels, unlinks) an I/O request from an endpoint */
 857static int mv_u3d_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
 858{
 859        struct mv_u3d_ep *ep;
 860        struct mv_u3d_req *req;
 861        struct mv_u3d *u3d;
 862        struct mv_u3d_ep_context *ep_context;
 863        struct mv_u3d_req *next_req;
 864
 865        unsigned long flags;
 866        int ret = 0;
 867
 868        if (!_ep || !_req)
 869                return -EINVAL;
 870
 871        ep = container_of(_ep, struct mv_u3d_ep, ep);
 872        u3d = ep->u3d;
 873
 874        spin_lock_irqsave(&ep->u3d->lock, flags);
 875
 876        /* make sure it's actually queued on this endpoint */
 877        list_for_each_entry(req, &ep->queue, queue) {
 878                if (&req->req == _req)
 879                        break;
 880        }
 881        if (&req->req != _req) {
 882                ret = -EINVAL;
 883                goto out;
 884        }
 885
 886        /* The request is in progress, or completed but not dequeued */
 887        if (ep->queue.next == &req->queue) {
 888                _req->status = -ECONNRESET;
 889                mv_u3d_ep_fifo_flush(_ep);
 890
 891                /* The request isn't the last request in this ep queue */
 892                if (req->queue.next != &ep->queue) {
 893                        dev_dbg(u3d->dev,
 894                                "it is the last request in this ep queue\n");
 895                        ep_context = ep->ep_context;
 896                        next_req = list_entry(req->queue.next,
 897                                        struct mv_u3d_req, queue);
 898
 899                        /* Point first TRB of next request to the EP context. */
 900                        iowrite32((unsigned long) next_req->trb_head,
 901                                        &ep_context->trb_addr_lo);
 902                } else {
 903                        struct mv_u3d_ep_context *ep_context;
 904                        ep_context = ep->ep_context;
 905                        ep_context->trb_addr_lo = 0;
 906                        ep_context->trb_addr_hi = 0;
 907                }
 908
 909        } else
 910                WARN_ON(1);
 911
 912        mv_u3d_done(ep, req, -ECONNRESET);
 913
 914        /* remove the req from the ep req list */
 915        if (!list_empty(&ep->req_list)) {
 916                struct mv_u3d_req *curr_req;
 917                curr_req = list_entry(ep->req_list.next,
 918                                        struct mv_u3d_req, list);
 919                if (curr_req == req) {
 920                        list_del_init(&req->list);
 921                        ep->processing = 0;
 922                }
 923        }
 924
 925out:
 926        spin_unlock_irqrestore(&ep->u3d->lock, flags);
 927        return ret;
 928}
 929
 930static void
 931mv_u3d_ep_set_stall(struct mv_u3d *u3d, u8 ep_num, u8 direction, int stall)
 932{
 933        u32 tmp;
 934        struct mv_u3d_ep *ep = u3d->eps;
 935
 936        dev_dbg(u3d->dev, "%s\n", __func__);
 937        if (direction == MV_U3D_EP_DIR_OUT) {
 938                tmp = ioread32(&u3d->vuc_regs->epcr[ep->ep_num].epxoutcr0);
 939                if (stall)
 940                        tmp |= MV_U3D_EPXCR_EP_HALT;
 941                else
 942                        tmp &= ~MV_U3D_EPXCR_EP_HALT;
 943                iowrite32(tmp, &u3d->vuc_regs->epcr[ep->ep_num].epxoutcr0);
 944        } else {
 945                tmp = ioread32(&u3d->vuc_regs->epcr[ep->ep_num].epxincr0);
 946                if (stall)
 947                        tmp |= MV_U3D_EPXCR_EP_HALT;
 948                else
 949                        tmp &= ~MV_U3D_EPXCR_EP_HALT;
 950                iowrite32(tmp, &u3d->vuc_regs->epcr[ep->ep_num].epxincr0);
 951        }
 952}
 953
 954static int mv_u3d_ep_set_halt_wedge(struct usb_ep *_ep, int halt, int wedge)
 955{
 956        struct mv_u3d_ep *ep;
 957        unsigned long flags = 0;
 958        int status = 0;
 959        struct mv_u3d *u3d;
 960
 961        ep = container_of(_ep, struct mv_u3d_ep, ep);
 962        u3d = ep->u3d;
 963        if (!ep->ep.desc) {
 964                status = -EINVAL;
 965                goto out;
 966        }
 967
 968        if (ep->ep.desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
 969                status = -EOPNOTSUPP;
 970                goto out;
 971        }
 972
 973        /*
 974         * Attempt to halt IN ep will fail if any transfer requests
 975         * are still queue
 976         */
 977        if (halt && (mv_u3d_ep_dir(ep) == MV_U3D_EP_DIR_IN)
 978                        && !list_empty(&ep->queue)) {
 979                status = -EAGAIN;
 980                goto out;
 981        }
 982
 983        spin_lock_irqsave(&ep->u3d->lock, flags);
 984        mv_u3d_ep_set_stall(u3d, ep->ep_num, mv_u3d_ep_dir(ep), halt);
 985        if (halt && wedge)
 986                ep->wedge = 1;
 987        else if (!halt)
 988                ep->wedge = 0;
 989        spin_unlock_irqrestore(&ep->u3d->lock, flags);
 990
 991        if (ep->ep_num == 0)
 992                u3d->ep0_dir = MV_U3D_EP_DIR_OUT;
 993out:
 994        return status;
 995}
 996
 997static int mv_u3d_ep_set_halt(struct usb_ep *_ep, int halt)
 998{
 999        return mv_u3d_ep_set_halt_wedge(_ep, halt, 0);
1000}
1001
1002static int mv_u3d_ep_set_wedge(struct usb_ep *_ep)
1003{
1004        return mv_u3d_ep_set_halt_wedge(_ep, 1, 1);
1005}
1006
1007static struct usb_ep_ops mv_u3d_ep_ops = {
1008        .enable         = mv_u3d_ep_enable,
1009        .disable        = mv_u3d_ep_disable,
1010
1011        .alloc_request  = mv_u3d_alloc_request,
1012        .free_request   = mv_u3d_free_request,
1013
1014        .queue          = mv_u3d_ep_queue,
1015        .dequeue        = mv_u3d_ep_dequeue,
1016
1017        .set_wedge      = mv_u3d_ep_set_wedge,
1018        .set_halt       = mv_u3d_ep_set_halt,
1019        .fifo_flush     = mv_u3d_ep_fifo_flush,
1020};
1021
1022static void mv_u3d_controller_stop(struct mv_u3d *u3d)
1023{
1024        u32 tmp;
1025
1026        if (!u3d->clock_gating && u3d->vbus_valid_detect)
1027                iowrite32(MV_U3D_INTR_ENABLE_VBUS_VALID,
1028                                &u3d->vuc_regs->intrenable);
1029        else
1030                iowrite32(0, &u3d->vuc_regs->intrenable);
1031        iowrite32(~0x0, &u3d->vuc_regs->endcomplete);
1032        iowrite32(~0x0, &u3d->vuc_regs->trbunderrun);
1033        iowrite32(~0x0, &u3d->vuc_regs->trbcomplete);
1034        iowrite32(~0x0, &u3d->vuc_regs->linkchange);
1035        iowrite32(0x1, &u3d->vuc_regs->setuplock);
1036
1037        /* Reset the RUN bit in the command register to stop USB */
1038        tmp = ioread32(&u3d->op_regs->usbcmd);
1039        tmp &= ~MV_U3D_CMD_RUN_STOP;
1040        iowrite32(tmp, &u3d->op_regs->usbcmd);
1041        dev_dbg(u3d->dev, "after u3d_stop, USBCMD 0x%x\n",
1042                ioread32(&u3d->op_regs->usbcmd));
1043}
1044
1045static void mv_u3d_controller_start(struct mv_u3d *u3d)
1046{
1047        u32 usbintr;
1048        u32 temp;
1049
1050        /* enable link LTSSM state machine */
1051        temp = ioread32(&u3d->vuc_regs->ltssm);
1052        temp |= MV_U3D_LTSSM_PHY_INIT_DONE;
1053        iowrite32(temp, &u3d->vuc_regs->ltssm);
1054
1055        /* Enable interrupts */
1056        usbintr = MV_U3D_INTR_ENABLE_LINK_CHG | MV_U3D_INTR_ENABLE_TXDESC_ERR |
1057                MV_U3D_INTR_ENABLE_RXDESC_ERR | MV_U3D_INTR_ENABLE_TX_COMPLETE |
1058                MV_U3D_INTR_ENABLE_RX_COMPLETE | MV_U3D_INTR_ENABLE_SETUP |
1059                (u3d->vbus_valid_detect ? MV_U3D_INTR_ENABLE_VBUS_VALID : 0);
1060        iowrite32(usbintr, &u3d->vuc_regs->intrenable);
1061
1062        /* Enable ctrl ep */
1063        iowrite32(0x1, &u3d->vuc_regs->ctrlepenable);
1064
1065        /* Set the Run bit in the command register */
1066        iowrite32(MV_U3D_CMD_RUN_STOP, &u3d->op_regs->usbcmd);
1067        dev_dbg(u3d->dev, "after u3d_start, USBCMD 0x%x\n",
1068                ioread32(&u3d->op_regs->usbcmd));
1069}
1070
1071static int mv_u3d_controller_reset(struct mv_u3d *u3d)
1072{
1073        unsigned int loops;
1074        u32 tmp;
1075
1076        /* Stop the controller */
1077        tmp = ioread32(&u3d->op_regs->usbcmd);
1078        tmp &= ~MV_U3D_CMD_RUN_STOP;
1079        iowrite32(tmp, &u3d->op_regs->usbcmd);
1080
1081        /* Reset the controller to get default values */
1082        iowrite32(MV_U3D_CMD_CTRL_RESET, &u3d->op_regs->usbcmd);
1083
1084        /* wait for reset to complete */
1085        loops = LOOPS(MV_U3D_RESET_TIMEOUT);
1086        while (ioread32(&u3d->op_regs->usbcmd) & MV_U3D_CMD_CTRL_RESET) {
1087                if (loops == 0) {
1088                        dev_err(u3d->dev,
1089                                "Wait for RESET completed TIMEOUT\n");
1090                        return -ETIMEDOUT;
1091                }
1092                loops--;
1093                udelay(LOOPS_USEC);
1094        }
1095
1096        /* Configure the Endpoint Context Address */
1097        iowrite32(u3d->ep_context_dma, &u3d->op_regs->dcbaapl);
1098        iowrite32(0, &u3d->op_regs->dcbaaph);
1099
1100        return 0;
1101}
1102
1103static int mv_u3d_enable(struct mv_u3d *u3d)
1104{
1105        struct mv_usb_platform_data *pdata = dev_get_platdata(u3d->dev);
1106        int retval;
1107
1108        if (u3d->active)
1109                return 0;
1110
1111        if (!u3d->clock_gating) {
1112                u3d->active = 1;
1113                return 0;
1114        }
1115
1116        dev_dbg(u3d->dev, "enable u3d\n");
1117        clk_enable(u3d->clk);
1118        if (pdata->phy_init) {
1119                retval = pdata->phy_init(u3d->phy_regs);
1120                if (retval) {
1121                        dev_err(u3d->dev,
1122                                "init phy error %d\n", retval);
1123                        clk_disable(u3d->clk);
1124                        return retval;
1125                }
1126        }
1127        u3d->active = 1;
1128
1129        return 0;
1130}
1131
1132static void mv_u3d_disable(struct mv_u3d *u3d)
1133{
1134        struct mv_usb_platform_data *pdata = dev_get_platdata(u3d->dev);
1135        if (u3d->clock_gating && u3d->active) {
1136                dev_dbg(u3d->dev, "disable u3d\n");
1137                if (pdata->phy_deinit)
1138                        pdata->phy_deinit(u3d->phy_regs);
1139                clk_disable(u3d->clk);
1140                u3d->active = 0;
1141        }
1142}
1143
1144static int mv_u3d_vbus_session(struct usb_gadget *gadget, int is_active)
1145{
1146        struct mv_u3d *u3d;
1147        unsigned long flags;
1148        int retval = 0;
1149
1150        u3d = container_of(gadget, struct mv_u3d, gadget);
1151
1152        spin_lock_irqsave(&u3d->lock, flags);
1153
1154        u3d->vbus_active = (is_active != 0);
1155        dev_dbg(u3d->dev, "%s: softconnect %d, vbus_active %d\n",
1156                __func__, u3d->softconnect, u3d->vbus_active);
1157        /*
1158         * 1. external VBUS detect: we can disable/enable clock on demand.
1159         * 2. UDC VBUS detect: we have to enable clock all the time.
1160         * 3. No VBUS detect: we have to enable clock all the time.
1161         */
1162        if (u3d->driver && u3d->softconnect && u3d->vbus_active) {
1163                retval = mv_u3d_enable(u3d);
1164                if (retval == 0) {
1165                        /*
1166                         * after clock is disabled, we lost all the register
1167                         *  context. We have to re-init registers
1168                         */
1169                        mv_u3d_controller_reset(u3d);
1170                        mv_u3d_ep0_reset(u3d);
1171                        mv_u3d_controller_start(u3d);
1172                }
1173        } else if (u3d->driver && u3d->softconnect) {
1174                if (!u3d->active)
1175                        goto out;
1176
1177                /* stop all the transfer in queue*/
1178                mv_u3d_stop_activity(u3d, u3d->driver);
1179                mv_u3d_controller_stop(u3d);
1180                mv_u3d_disable(u3d);
1181        }
1182
1183out:
1184        spin_unlock_irqrestore(&u3d->lock, flags);
1185        return retval;
1186}
1187
1188/* constrain controller's VBUS power usage
1189 * This call is used by gadget drivers during SET_CONFIGURATION calls,
1190 * reporting how much power the device may consume.  For example, this
1191 * could affect how quickly batteries are recharged.
1192 *
1193 * Returns zero on success, else negative errno.
1194 */
1195static int mv_u3d_vbus_draw(struct usb_gadget *gadget, unsigned mA)
1196{
1197        struct mv_u3d *u3d = container_of(gadget, struct mv_u3d, gadget);
1198
1199        u3d->power = mA;
1200
1201        return 0;
1202}
1203
1204static int mv_u3d_pullup(struct usb_gadget *gadget, int is_on)
1205{
1206        struct mv_u3d *u3d = container_of(gadget, struct mv_u3d, gadget);
1207        unsigned long flags;
1208        int retval = 0;
1209
1210        spin_lock_irqsave(&u3d->lock, flags);
1211
1212        dev_dbg(u3d->dev, "%s: softconnect %d, vbus_active %d\n",
1213                __func__, u3d->softconnect, u3d->vbus_active);
1214        u3d->softconnect = (is_on != 0);
1215        if (u3d->driver && u3d->softconnect && u3d->vbus_active) {
1216                retval = mv_u3d_enable(u3d);
1217                if (retval == 0) {
1218                        /*
1219                         * after clock is disabled, we lost all the register
1220                         *  context. We have to re-init registers
1221                         */
1222                        mv_u3d_controller_reset(u3d);
1223                        mv_u3d_ep0_reset(u3d);
1224                        mv_u3d_controller_start(u3d);
1225                }
1226        } else if (u3d->driver && u3d->vbus_active) {
1227                /* stop all the transfer in queue*/
1228                mv_u3d_stop_activity(u3d, u3d->driver);
1229                mv_u3d_controller_stop(u3d);
1230                mv_u3d_disable(u3d);
1231        }
1232
1233        spin_unlock_irqrestore(&u3d->lock, flags);
1234
1235        return retval;
1236}
1237
1238static int mv_u3d_start(struct usb_gadget *g,
1239                struct usb_gadget_driver *driver)
1240{
1241        struct mv_u3d *u3d = container_of(g, struct mv_u3d, gadget);
1242        struct mv_usb_platform_data *pdata = dev_get_platdata(u3d->dev);
1243        unsigned long flags;
1244
1245        if (u3d->driver)
1246                return -EBUSY;
1247
1248        spin_lock_irqsave(&u3d->lock, flags);
1249
1250        if (!u3d->clock_gating) {
1251                clk_enable(u3d->clk);
1252                if (pdata->phy_init)
1253                        pdata->phy_init(u3d->phy_regs);
1254        }
1255
1256        /* hook up the driver ... */
1257        driver->driver.bus = NULL;
1258        u3d->driver = driver;
1259
1260        u3d->ep0_dir = USB_DIR_OUT;
1261
1262        spin_unlock_irqrestore(&u3d->lock, flags);
1263
1264        u3d->vbus_valid_detect = 1;
1265
1266        return 0;
1267}
1268
1269static int mv_u3d_stop(struct usb_gadget *g,
1270                struct usb_gadget_driver *driver)
1271{
1272        struct mv_u3d *u3d = container_of(g, struct mv_u3d, gadget);
1273        struct mv_usb_platform_data *pdata = dev_get_platdata(u3d->dev);
1274        unsigned long flags;
1275
1276        u3d->vbus_valid_detect = 0;
1277        spin_lock_irqsave(&u3d->lock, flags);
1278
1279        /* enable clock to access controller register */
1280        clk_enable(u3d->clk);
1281        if (pdata->phy_init)
1282                pdata->phy_init(u3d->phy_regs);
1283
1284        mv_u3d_controller_stop(u3d);
1285        /* stop all usb activities */
1286        u3d->gadget.speed = USB_SPEED_UNKNOWN;
1287        mv_u3d_stop_activity(u3d, driver);
1288        mv_u3d_disable(u3d);
1289
1290        if (pdata->phy_deinit)
1291                pdata->phy_deinit(u3d->phy_regs);
1292        clk_disable(u3d->clk);
1293
1294        spin_unlock_irqrestore(&u3d->lock, flags);
1295
1296        u3d->driver = NULL;
1297
1298        return 0;
1299}
1300
1301/* device controller usb_gadget_ops structure */
1302static const struct usb_gadget_ops mv_u3d_ops = {
1303        /* notify controller that VBUS is powered or not */
1304        .vbus_session   = mv_u3d_vbus_session,
1305
1306        /* constrain controller's VBUS power usage */
1307        .vbus_draw      = mv_u3d_vbus_draw,
1308
1309        .pullup         = mv_u3d_pullup,
1310        .udc_start      = mv_u3d_start,
1311        .udc_stop       = mv_u3d_stop,
1312};
1313
1314static int mv_u3d_eps_init(struct mv_u3d *u3d)
1315{
1316        struct mv_u3d_ep        *ep;
1317        char name[14];
1318        int i;
1319
1320        /* initialize ep0, ep0 in/out use eps[1] */
1321        ep = &u3d->eps[1];
1322        ep->u3d = u3d;
1323        strncpy(ep->name, "ep0", sizeof(ep->name));
1324        ep->ep.name = ep->name;
1325        ep->ep.ops = &mv_u3d_ep_ops;
1326        ep->wedge = 0;
1327        usb_ep_set_maxpacket_limit(&ep->ep, MV_U3D_EP0_MAX_PKT_SIZE);
1328        ep->ep_num = 0;
1329        ep->ep.desc = &mv_u3d_ep0_desc;
1330        INIT_LIST_HEAD(&ep->queue);
1331        INIT_LIST_HEAD(&ep->req_list);
1332        ep->ep_type = USB_ENDPOINT_XFER_CONTROL;
1333
1334        /* add ep0 ep_context */
1335        ep->ep_context = &u3d->ep_context[1];
1336
1337        /* initialize other endpoints */
1338        for (i = 2; i < u3d->max_eps * 2; i++) {
1339                ep = &u3d->eps[i];
1340                if (i & 1) {
1341                        snprintf(name, sizeof(name), "ep%din", i >> 1);
1342                        ep->direction = MV_U3D_EP_DIR_IN;
1343                } else {
1344                        snprintf(name, sizeof(name), "ep%dout", i >> 1);
1345                        ep->direction = MV_U3D_EP_DIR_OUT;
1346                }
1347                ep->u3d = u3d;
1348                strncpy(ep->name, name, sizeof(ep->name));
1349                ep->ep.name = ep->name;
1350
1351                ep->ep.ops = &mv_u3d_ep_ops;
1352                usb_ep_set_maxpacket_limit(&ep->ep, (unsigned short) ~0);
1353                ep->ep_num = i / 2;
1354
1355                INIT_LIST_HEAD(&ep->queue);
1356                list_add_tail(&ep->ep.ep_list, &u3d->gadget.ep_list);
1357
1358                INIT_LIST_HEAD(&ep->req_list);
1359                spin_lock_init(&ep->req_lock);
1360                ep->ep_context = &u3d->ep_context[i];
1361        }
1362
1363        return 0;
1364}
1365
1366/* delete all endpoint requests, called with spinlock held */
1367static void mv_u3d_nuke(struct mv_u3d_ep *ep, int status)
1368{
1369        /* endpoint fifo flush */
1370        mv_u3d_ep_fifo_flush(&ep->ep);
1371
1372        while (!list_empty(&ep->queue)) {
1373                struct mv_u3d_req *req = NULL;
1374                req = list_entry(ep->queue.next, struct mv_u3d_req, queue);
1375                mv_u3d_done(ep, req, status);
1376        }
1377}
1378
1379/* stop all USB activities */
1380static
1381void mv_u3d_stop_activity(struct mv_u3d *u3d, struct usb_gadget_driver *driver)
1382{
1383        struct mv_u3d_ep        *ep;
1384
1385        mv_u3d_nuke(&u3d->eps[1], -ESHUTDOWN);
1386
1387        list_for_each_entry(ep, &u3d->gadget.ep_list, ep.ep_list) {
1388                mv_u3d_nuke(ep, -ESHUTDOWN);
1389        }
1390
1391        /* report disconnect; the driver is already quiesced */
1392        if (driver) {
1393                spin_unlock(&u3d->lock);
1394                driver->disconnect(&u3d->gadget);
1395                spin_lock(&u3d->lock);
1396        }
1397}
1398
1399static void mv_u3d_irq_process_error(struct mv_u3d *u3d)
1400{
1401        /* Increment the error count */
1402        u3d->errors++;
1403        dev_err(u3d->dev, "%s\n", __func__);
1404}
1405
1406static void mv_u3d_irq_process_link_change(struct mv_u3d *u3d)
1407{
1408        u32 linkchange;
1409
1410        linkchange = ioread32(&u3d->vuc_regs->linkchange);
1411        iowrite32(linkchange, &u3d->vuc_regs->linkchange);
1412
1413        dev_dbg(u3d->dev, "linkchange: 0x%x\n", linkchange);
1414
1415        if (linkchange & MV_U3D_LINK_CHANGE_LINK_UP) {
1416                dev_dbg(u3d->dev, "link up: ltssm state: 0x%x\n",
1417                        ioread32(&u3d->vuc_regs->ltssmstate));
1418
1419                u3d->usb_state = USB_STATE_DEFAULT;
1420                u3d->ep0_dir = MV_U3D_EP_DIR_OUT;
1421                u3d->ep0_state = MV_U3D_WAIT_FOR_SETUP;
1422
1423                /* set speed */
1424                u3d->gadget.speed = USB_SPEED_SUPER;
1425        }
1426
1427        if (linkchange & MV_U3D_LINK_CHANGE_SUSPEND) {
1428                dev_dbg(u3d->dev, "link suspend\n");
1429                u3d->resume_state = u3d->usb_state;
1430                u3d->usb_state = USB_STATE_SUSPENDED;
1431        }
1432
1433        if (linkchange & MV_U3D_LINK_CHANGE_RESUME) {
1434                dev_dbg(u3d->dev, "link resume\n");
1435                u3d->usb_state = u3d->resume_state;
1436                u3d->resume_state = 0;
1437        }
1438
1439        if (linkchange & MV_U3D_LINK_CHANGE_WRESET) {
1440                dev_dbg(u3d->dev, "warm reset\n");
1441                u3d->usb_state = USB_STATE_POWERED;
1442        }
1443
1444        if (linkchange & MV_U3D_LINK_CHANGE_HRESET) {
1445                dev_dbg(u3d->dev, "hot reset\n");
1446                u3d->usb_state = USB_STATE_DEFAULT;
1447        }
1448
1449        if (linkchange & MV_U3D_LINK_CHANGE_INACT)
1450                dev_dbg(u3d->dev, "inactive\n");
1451
1452        if (linkchange & MV_U3D_LINK_CHANGE_DISABLE_AFTER_U0)
1453                dev_dbg(u3d->dev, "ss.disabled\n");
1454
1455        if (linkchange & MV_U3D_LINK_CHANGE_VBUS_INVALID) {
1456                dev_dbg(u3d->dev, "vbus invalid\n");
1457                u3d->usb_state = USB_STATE_ATTACHED;
1458                u3d->vbus_valid_detect = 1;
1459                /* if external vbus detect is not supported,
1460                 * we handle it here.
1461                 */
1462                if (!u3d->vbus) {
1463                        spin_unlock(&u3d->lock);
1464                        mv_u3d_vbus_session(&u3d->gadget, 0);
1465                        spin_lock(&u3d->lock);
1466                }
1467        }
1468}
1469
1470static void mv_u3d_ch9setaddress(struct mv_u3d *u3d,
1471                                struct usb_ctrlrequest *setup)
1472{
1473        u32 tmp;
1474
1475        if (u3d->usb_state != USB_STATE_DEFAULT) {
1476                dev_err(u3d->dev,
1477                        "%s, cannot setaddr in this state (%d)\n",
1478                        __func__, u3d->usb_state);
1479                goto err;
1480        }
1481
1482        u3d->dev_addr = (u8)setup->wValue;
1483
1484        dev_dbg(u3d->dev, "%s: 0x%x\n", __func__, u3d->dev_addr);
1485
1486        if (u3d->dev_addr > 127) {
1487                dev_err(u3d->dev,
1488                        "%s, u3d address is wrong (out of range)\n", __func__);
1489                u3d->dev_addr = 0;
1490                goto err;
1491        }
1492
1493        /* update usb state */
1494        u3d->usb_state = USB_STATE_ADDRESS;
1495
1496        /* set the new address */
1497        tmp = ioread32(&u3d->vuc_regs->devaddrtiebrkr);
1498        tmp &= ~0x7F;
1499        tmp |= (u32)u3d->dev_addr;
1500        iowrite32(tmp, &u3d->vuc_regs->devaddrtiebrkr);
1501
1502        return;
1503err:
1504        mv_u3d_ep0_stall(u3d);
1505}
1506
1507static int mv_u3d_is_set_configuration(struct usb_ctrlrequest *setup)
1508{
1509        if ((setup->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD)
1510                if (setup->bRequest == USB_REQ_SET_CONFIGURATION)
1511                        return 1;
1512
1513        return 0;
1514}
1515
1516static void mv_u3d_handle_setup_packet(struct mv_u3d *u3d, u8 ep_num,
1517        struct usb_ctrlrequest *setup)
1518        __releases(&u3c->lock)
1519        __acquires(&u3c->lock)
1520{
1521        bool delegate = false;
1522
1523        mv_u3d_nuke(&u3d->eps[ep_num * 2 + MV_U3D_EP_DIR_IN], -ESHUTDOWN);
1524
1525        dev_dbg(u3d->dev, "SETUP %02x.%02x v%04x i%04x l%04x\n",
1526                        setup->bRequestType, setup->bRequest,
1527                        setup->wValue, setup->wIndex, setup->wLength);
1528
1529        /* We process some stardard setup requests here */
1530        if ((setup->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
1531                switch (setup->bRequest) {
1532                case USB_REQ_GET_STATUS:
1533                        delegate = true;
1534                        break;
1535
1536                case USB_REQ_SET_ADDRESS:
1537                        mv_u3d_ch9setaddress(u3d, setup);
1538                        break;
1539
1540                case USB_REQ_CLEAR_FEATURE:
1541                        delegate = true;
1542                        break;
1543
1544                case USB_REQ_SET_FEATURE:
1545                        delegate = true;
1546                        break;
1547
1548                default:
1549                        delegate = true;
1550                }
1551        } else
1552                delegate = true;
1553
1554        /* delegate USB standard requests to the gadget driver */
1555        if (delegate == true) {
1556                /* USB requests handled by gadget */
1557                if (setup->wLength) {
1558                        /* DATA phase from gadget, STATUS phase from u3d */
1559                        u3d->ep0_dir = (setup->bRequestType & USB_DIR_IN)
1560                                        ? MV_U3D_EP_DIR_IN : MV_U3D_EP_DIR_OUT;
1561                        spin_unlock(&u3d->lock);
1562                        if (u3d->driver->setup(&u3d->gadget,
1563                                &u3d->local_setup_buff) < 0) {
1564                                dev_err(u3d->dev, "setup error!\n");
1565                                mv_u3d_ep0_stall(u3d);
1566                        }
1567                        spin_lock(&u3d->lock);
1568                } else {
1569                        /* no DATA phase, STATUS phase from gadget */
1570                        u3d->ep0_dir = MV_U3D_EP_DIR_IN;
1571                        u3d->ep0_state = MV_U3D_STATUS_STAGE;
1572                        spin_unlock(&u3d->lock);
1573                        if (u3d->driver->setup(&u3d->gadget,
1574                                &u3d->local_setup_buff) < 0)
1575                                mv_u3d_ep0_stall(u3d);
1576                        spin_lock(&u3d->lock);
1577                }
1578
1579                if (mv_u3d_is_set_configuration(setup)) {
1580                        dev_dbg(u3d->dev, "u3d configured\n");
1581                        u3d->usb_state = USB_STATE_CONFIGURED;
1582                }
1583        }
1584}
1585
1586static void mv_u3d_get_setup_data(struct mv_u3d *u3d, u8 ep_num, u8 *buffer_ptr)
1587{
1588        struct mv_u3d_ep_context *epcontext;
1589
1590        epcontext = &u3d->ep_context[ep_num * 2 + MV_U3D_EP_DIR_IN];
1591
1592        /* Copy the setup packet to local buffer */
1593        memcpy(buffer_ptr, (u8 *) &epcontext->setup_buffer, 8);
1594}
1595
1596static void mv_u3d_irq_process_setup(struct mv_u3d *u3d)
1597{
1598        u32 tmp, i;
1599        /* Process all Setup packet received interrupts */
1600        tmp = ioread32(&u3d->vuc_regs->setuplock);
1601        if (tmp) {
1602                for (i = 0; i < u3d->max_eps; i++) {
1603                        if (tmp & (1 << i)) {
1604                                mv_u3d_get_setup_data(u3d, i,
1605                                        (u8 *)(&u3d->local_setup_buff));
1606                                mv_u3d_handle_setup_packet(u3d, i,
1607                                        &u3d->local_setup_buff);
1608                        }
1609                }
1610        }
1611
1612        iowrite32(tmp, &u3d->vuc_regs->setuplock);
1613}
1614
1615static void mv_u3d_irq_process_tr_complete(struct mv_u3d *u3d)
1616{
1617        u32 tmp, bit_pos;
1618        int i, ep_num = 0, direction = 0;
1619        struct mv_u3d_ep        *curr_ep;
1620        struct mv_u3d_req *curr_req, *temp_req;
1621        int status;
1622
1623        tmp = ioread32(&u3d->vuc_regs->endcomplete);
1624
1625        dev_dbg(u3d->dev, "tr_complete: ep: 0x%x\n", tmp);
1626        if (!tmp)
1627                return;
1628        iowrite32(tmp, &u3d->vuc_regs->endcomplete);
1629
1630        for (i = 0; i < u3d->max_eps * 2; i++) {
1631                ep_num = i >> 1;
1632                direction = i % 2;
1633
1634                bit_pos = 1 << (ep_num + 16 * direction);
1635
1636                if (!(bit_pos & tmp))
1637                        continue;
1638
1639                if (i == 0)
1640                        curr_ep = &u3d->eps[1];
1641                else
1642                        curr_ep = &u3d->eps[i];
1643
1644                /* remove req out of ep request list after completion */
1645                dev_dbg(u3d->dev, "tr comp: check req_list\n");
1646                spin_lock(&curr_ep->req_lock);
1647                if (!list_empty(&curr_ep->req_list)) {
1648                        struct mv_u3d_req *req;
1649                        req = list_entry(curr_ep->req_list.next,
1650                                                struct mv_u3d_req, list);
1651                        list_del_init(&req->list);
1652                        curr_ep->processing = 0;
1653                }
1654                spin_unlock(&curr_ep->req_lock);
1655
1656                /* process the req queue until an uncomplete request */
1657                list_for_each_entry_safe(curr_req, temp_req,
1658                        &curr_ep->queue, queue) {
1659                        status = mv_u3d_process_ep_req(u3d, i, curr_req);
1660                        if (status)
1661                                break;
1662                        /* write back status to req */
1663                        curr_req->req.status = status;
1664
1665                        /* ep0 request completion */
1666                        if (ep_num == 0) {
1667                                mv_u3d_done(curr_ep, curr_req, 0);
1668                                break;
1669                        } else {
1670                                mv_u3d_done(curr_ep, curr_req, status);
1671                        }
1672                }
1673
1674                dev_dbg(u3d->dev, "call mv_u3d_start_queue from ep complete\n");
1675                mv_u3d_start_queue(curr_ep);
1676        }
1677}
1678
1679static irqreturn_t mv_u3d_irq(int irq, void *dev)
1680{
1681        struct mv_u3d *u3d = (struct mv_u3d *)dev;
1682        u32 status, intr;
1683        u32 bridgesetting;
1684        u32 trbunderrun;
1685
1686        spin_lock(&u3d->lock);
1687
1688        status = ioread32(&u3d->vuc_regs->intrcause);
1689        intr = ioread32(&u3d->vuc_regs->intrenable);
1690        status &= intr;
1691
1692        if (status == 0) {
1693                spin_unlock(&u3d->lock);
1694                dev_err(u3d->dev, "irq error!\n");
1695                return IRQ_NONE;
1696        }
1697
1698        if (status & MV_U3D_USBINT_VBUS_VALID) {
1699                bridgesetting = ioread32(&u3d->vuc_regs->bridgesetting);
1700                if (bridgesetting & MV_U3D_BRIDGE_SETTING_VBUS_VALID) {
1701                        /* write vbus valid bit of bridge setting to clear */
1702                        bridgesetting = MV_U3D_BRIDGE_SETTING_VBUS_VALID;
1703                        iowrite32(bridgesetting, &u3d->vuc_regs->bridgesetting);
1704                        dev_dbg(u3d->dev, "vbus valid\n");
1705
1706                        u3d->usb_state = USB_STATE_POWERED;
1707                        u3d->vbus_valid_detect = 0;
1708                        /* if external vbus detect is not supported,
1709                         * we handle it here.
1710                         */
1711                        if (!u3d->vbus) {
1712                                spin_unlock(&u3d->lock);
1713                                mv_u3d_vbus_session(&u3d->gadget, 1);
1714                                spin_lock(&u3d->lock);
1715                        }
1716                } else
1717                        dev_err(u3d->dev, "vbus bit is not set\n");
1718        }
1719
1720        /* RX data is already in the 16KB FIFO.*/
1721        if (status & MV_U3D_USBINT_UNDER_RUN) {
1722                trbunderrun = ioread32(&u3d->vuc_regs->trbunderrun);
1723                dev_err(u3d->dev, "under run, ep%d\n", trbunderrun);
1724                iowrite32(trbunderrun, &u3d->vuc_regs->trbunderrun);
1725                mv_u3d_irq_process_error(u3d);
1726        }
1727
1728        if (status & (MV_U3D_USBINT_RXDESC_ERR | MV_U3D_USBINT_TXDESC_ERR)) {
1729                /* write one to clear */
1730                iowrite32(status & (MV_U3D_USBINT_RXDESC_ERR
1731                        | MV_U3D_USBINT_TXDESC_ERR),
1732                        &u3d->vuc_regs->intrcause);
1733                dev_err(u3d->dev, "desc err 0x%x\n", status);
1734                mv_u3d_irq_process_error(u3d);
1735        }
1736
1737        if (status & MV_U3D_USBINT_LINK_CHG)
1738                mv_u3d_irq_process_link_change(u3d);
1739
1740        if (status & MV_U3D_USBINT_TX_COMPLETE)
1741                mv_u3d_irq_process_tr_complete(u3d);
1742
1743        if (status & MV_U3D_USBINT_RX_COMPLETE)
1744                mv_u3d_irq_process_tr_complete(u3d);
1745
1746        if (status & MV_U3D_USBINT_SETUP)
1747                mv_u3d_irq_process_setup(u3d);
1748
1749        spin_unlock(&u3d->lock);
1750        return IRQ_HANDLED;
1751}
1752
1753static int mv_u3d_remove(struct platform_device *dev)
1754{
1755        struct mv_u3d *u3d = platform_get_drvdata(dev);
1756
1757        BUG_ON(u3d == NULL);
1758
1759        usb_del_gadget_udc(&u3d->gadget);
1760
1761        /* free memory allocated in probe */
1762        if (u3d->trb_pool)
1763                dma_pool_destroy(u3d->trb_pool);
1764
1765        if (u3d->ep_context)
1766                dma_free_coherent(&dev->dev, u3d->ep_context_size,
1767                        u3d->ep_context, u3d->ep_context_dma);
1768
1769        kfree(u3d->eps);
1770
1771        if (u3d->irq)
1772                free_irq(u3d->irq, u3d);
1773
1774        if (u3d->cap_regs)
1775                iounmap(u3d->cap_regs);
1776        u3d->cap_regs = NULL;
1777
1778        kfree(u3d->status_req);
1779
1780        clk_put(u3d->clk);
1781
1782        kfree(u3d);
1783
1784        return 0;
1785}
1786
1787static int mv_u3d_probe(struct platform_device *dev)
1788{
1789        struct mv_u3d *u3d = NULL;
1790        struct mv_usb_platform_data *pdata = dev_get_platdata(&dev->dev);
1791        int retval = 0;
1792        struct resource *r;
1793        size_t size;
1794
1795        if (!dev_get_platdata(&dev->dev)) {
1796                dev_err(&dev->dev, "missing platform_data\n");
1797                retval = -ENODEV;
1798                goto err_pdata;
1799        }
1800
1801        u3d = kzalloc(sizeof(*u3d), GFP_KERNEL);
1802        if (!u3d) {
1803                retval = -ENOMEM;
1804                goto err_alloc_private;
1805        }
1806
1807        spin_lock_init(&u3d->lock);
1808
1809        platform_set_drvdata(dev, u3d);
1810
1811        u3d->dev = &dev->dev;
1812        u3d->vbus = pdata->vbus;
1813
1814        u3d->clk = clk_get(&dev->dev, NULL);
1815        if (IS_ERR(u3d->clk)) {
1816                retval = PTR_ERR(u3d->clk);
1817                goto err_get_clk;
1818        }
1819
1820        r = platform_get_resource_byname(dev, IORESOURCE_MEM, "capregs");
1821        if (!r) {
1822                dev_err(&dev->dev, "no I/O memory resource defined\n");
1823                retval = -ENODEV;
1824                goto err_get_cap_regs;
1825        }
1826
1827        u3d->cap_regs = (struct mv_u3d_cap_regs __iomem *)
1828                ioremap(r->start, resource_size(r));
1829        if (!u3d->cap_regs) {
1830                dev_err(&dev->dev, "failed to map I/O memory\n");
1831                retval = -EBUSY;
1832                goto err_map_cap_regs;
1833        } else {
1834                dev_dbg(&dev->dev, "cap_regs address: 0x%lx/0x%lx\n",
1835                        (unsigned long) r->start,
1836                        (unsigned long) u3d->cap_regs);
1837        }
1838
1839        /* we will access controller register, so enable the u3d controller */
1840        clk_enable(u3d->clk);
1841
1842        if (pdata->phy_init) {
1843                retval = pdata->phy_init(u3d->phy_regs);
1844                if (retval) {
1845                        dev_err(&dev->dev, "init phy error %d\n", retval);
1846                        goto err_u3d_enable;
1847                }
1848        }
1849
1850        u3d->op_regs = (struct mv_u3d_op_regs __iomem *)(u3d->cap_regs
1851                + MV_U3D_USB3_OP_REGS_OFFSET);
1852
1853        u3d->vuc_regs = (struct mv_u3d_vuc_regs __iomem *)(u3d->cap_regs
1854                + ioread32(&u3d->cap_regs->vuoff));
1855
1856        u3d->max_eps = 16;
1857
1858        /*
1859         * some platform will use usb to download image, it may not disconnect
1860         * usb gadget before loading kernel. So first stop u3d here.
1861         */
1862        mv_u3d_controller_stop(u3d);
1863        iowrite32(0xFFFFFFFF, &u3d->vuc_regs->intrcause);
1864
1865        if (pdata->phy_deinit)
1866                pdata->phy_deinit(u3d->phy_regs);
1867        clk_disable(u3d->clk);
1868
1869        size = u3d->max_eps * sizeof(struct mv_u3d_ep_context) * 2;
1870        size = (size + MV_U3D_EP_CONTEXT_ALIGNMENT - 1)
1871                & ~(MV_U3D_EP_CONTEXT_ALIGNMENT - 1);
1872        u3d->ep_context = dma_alloc_coherent(&dev->dev, size,
1873                                        &u3d->ep_context_dma, GFP_KERNEL);
1874        if (!u3d->ep_context) {
1875                dev_err(&dev->dev, "allocate ep context memory failed\n");
1876                retval = -ENOMEM;
1877                goto err_alloc_ep_context;
1878        }
1879        u3d->ep_context_size = size;
1880
1881        /* create TRB dma_pool resource */
1882        u3d->trb_pool = dma_pool_create("u3d_trb",
1883                        &dev->dev,
1884                        sizeof(struct mv_u3d_trb_hw),
1885                        MV_U3D_TRB_ALIGNMENT,
1886                        MV_U3D_DMA_BOUNDARY);
1887
1888        if (!u3d->trb_pool) {
1889                retval = -ENOMEM;
1890                goto err_alloc_trb_pool;
1891        }
1892
1893        size = u3d->max_eps * sizeof(struct mv_u3d_ep) * 2;
1894        u3d->eps = kzalloc(size, GFP_KERNEL);
1895        if (!u3d->eps) {
1896                retval = -ENOMEM;
1897                goto err_alloc_eps;
1898        }
1899
1900        /* initialize ep0 status request structure */
1901        u3d->status_req = kzalloc(sizeof(struct mv_u3d_req) + 8, GFP_KERNEL);
1902        if (!u3d->status_req) {
1903                retval = -ENOMEM;
1904                goto err_alloc_status_req;
1905        }
1906        INIT_LIST_HEAD(&u3d->status_req->queue);
1907
1908        /* allocate a small amount of memory to get valid address */
1909        u3d->status_req->req.buf = (char *)u3d->status_req
1910                                        + sizeof(struct mv_u3d_req);
1911        u3d->status_req->req.dma = virt_to_phys(u3d->status_req->req.buf);
1912
1913        u3d->resume_state = USB_STATE_NOTATTACHED;
1914        u3d->usb_state = USB_STATE_ATTACHED;
1915        u3d->ep0_dir = MV_U3D_EP_DIR_OUT;
1916        u3d->remote_wakeup = 0;
1917
1918        r = platform_get_resource(dev, IORESOURCE_IRQ, 0);
1919        if (!r) {
1920                dev_err(&dev->dev, "no IRQ resource defined\n");
1921                retval = -ENODEV;
1922                goto err_get_irq;
1923        }
1924        u3d->irq = r->start;
1925        if (request_irq(u3d->irq, mv_u3d_irq,
1926                IRQF_SHARED, driver_name, u3d)) {
1927                u3d->irq = 0;
1928                dev_err(&dev->dev, "Request irq %d for u3d failed\n",
1929                        u3d->irq);
1930                retval = -ENODEV;
1931                goto err_request_irq;
1932        }
1933
1934        /* initialize gadget structure */
1935        u3d->gadget.ops = &mv_u3d_ops;  /* usb_gadget_ops */
1936        u3d->gadget.ep0 = &u3d->eps[1].ep;      /* gadget ep0 */
1937        INIT_LIST_HEAD(&u3d->gadget.ep_list);   /* ep_list */
1938        u3d->gadget.speed = USB_SPEED_UNKNOWN;  /* speed */
1939
1940        /* the "gadget" abstracts/virtualizes the controller */
1941        u3d->gadget.name = driver_name;         /* gadget name */
1942
1943        mv_u3d_eps_init(u3d);
1944
1945        /* external vbus detection */
1946        if (u3d->vbus) {
1947                u3d->clock_gating = 1;
1948                dev_err(&dev->dev, "external vbus detection\n");
1949        }
1950
1951        if (!u3d->clock_gating)
1952                u3d->vbus_active = 1;
1953
1954        /* enable usb3 controller vbus detection */
1955        u3d->vbus_valid_detect = 1;
1956
1957        retval = usb_add_gadget_udc(&dev->dev, &u3d->gadget);
1958        if (retval)
1959                goto err_unregister;
1960
1961        dev_dbg(&dev->dev, "successful probe usb3 device %s clock gating.\n",
1962                u3d->clock_gating ? "with" : "without");
1963
1964        return 0;
1965
1966err_unregister:
1967        free_irq(u3d->irq, u3d);
1968err_request_irq:
1969err_get_irq:
1970        kfree(u3d->status_req);
1971err_alloc_status_req:
1972        kfree(u3d->eps);
1973err_alloc_eps:
1974        dma_pool_destroy(u3d->trb_pool);
1975err_alloc_trb_pool:
1976        dma_free_coherent(&dev->dev, u3d->ep_context_size,
1977                u3d->ep_context, u3d->ep_context_dma);
1978err_alloc_ep_context:
1979        if (pdata->phy_deinit)
1980                pdata->phy_deinit(u3d->phy_regs);
1981        clk_disable(u3d->clk);
1982err_u3d_enable:
1983        iounmap(u3d->cap_regs);
1984err_map_cap_regs:
1985err_get_cap_regs:
1986err_get_clk:
1987        clk_put(u3d->clk);
1988        kfree(u3d);
1989err_alloc_private:
1990err_pdata:
1991        return retval;
1992}
1993
1994#ifdef CONFIG_PM_SLEEP
1995static int mv_u3d_suspend(struct device *dev)
1996{
1997        struct mv_u3d *u3d = dev_get_drvdata(dev);
1998
1999        /*
2000         * only cable is unplugged, usb can suspend.
2001         * So do not care about clock_gating == 1, it is handled by
2002         * vbus session.
2003         */
2004        if (!u3d->clock_gating) {
2005                mv_u3d_controller_stop(u3d);
2006
2007                spin_lock_irq(&u3d->lock);
2008                /* stop all usb activities */
2009                mv_u3d_stop_activity(u3d, u3d->driver);
2010                spin_unlock_irq(&u3d->lock);
2011
2012                mv_u3d_disable(u3d);
2013        }
2014
2015        return 0;
2016}
2017
2018static int mv_u3d_resume(struct device *dev)
2019{
2020        struct mv_u3d *u3d = dev_get_drvdata(dev);
2021        int retval;
2022
2023        if (!u3d->clock_gating) {
2024                retval = mv_u3d_enable(u3d);
2025                if (retval)
2026                        return retval;
2027
2028                if (u3d->driver && u3d->softconnect) {
2029                        mv_u3d_controller_reset(u3d);
2030                        mv_u3d_ep0_reset(u3d);
2031                        mv_u3d_controller_start(u3d);
2032                }
2033        }
2034
2035        return 0;
2036}
2037#endif
2038
2039static SIMPLE_DEV_PM_OPS(mv_u3d_pm_ops, mv_u3d_suspend, mv_u3d_resume);
2040
2041static void mv_u3d_shutdown(struct platform_device *dev)
2042{
2043        struct mv_u3d *u3d = platform_get_drvdata(dev);
2044        u32 tmp;
2045
2046        tmp = ioread32(&u3d->op_regs->usbcmd);
2047        tmp &= ~MV_U3D_CMD_RUN_STOP;
2048        iowrite32(tmp, &u3d->op_regs->usbcmd);
2049}
2050
2051static struct platform_driver mv_u3d_driver = {
2052        .probe          = mv_u3d_probe,
2053        .remove         = mv_u3d_remove,
2054        .shutdown       = mv_u3d_shutdown,
2055        .driver         = {
2056                .owner  = THIS_MODULE,
2057                .name   = "mv-u3d",
2058                .pm     = &mv_u3d_pm_ops,
2059        },
2060};
2061
2062module_platform_driver(mv_u3d_driver);
2063MODULE_ALIAS("platform:mv-u3d");
2064MODULE_DESCRIPTION(DRIVER_DESC);
2065MODULE_AUTHOR("Yu Xu <yuxu@marvell.com>");
2066MODULE_LICENSE("GPL");
2067