1#ifndef LINUX_BCMA_DRIVER_PCI_H_
2#define LINUX_BCMA_DRIVER_PCI_H_
3
4#include <linux/types.h>
5
6struct pci_dev;
7
8
9#define BCMA_CORE_PCI_CTL 0x0000
10#define BCMA_CORE_PCI_CTL_RST_OE 0x00000001
11#define BCMA_CORE_PCI_CTL_RST 0x00000002
12#define BCMA_CORE_PCI_CTL_CLK_OE 0x00000004
13#define BCMA_CORE_PCI_CTL_CLK 0x00000008
14#define BCMA_CORE_PCI_ARBCTL 0x0010
15#define BCMA_CORE_PCI_ARBCTL_INTERN 0x00000001
16#define BCMA_CORE_PCI_ARBCTL_EXTERN 0x00000002
17#define BCMA_CORE_PCI_ARBCTL_PARKID 0x00000006
18#define BCMA_CORE_PCI_ARBCTL_PARKID_LAST 0x00000000
19#define BCMA_CORE_PCI_ARBCTL_PARKID_4710 0x00000002
20#define BCMA_CORE_PCI_ARBCTL_PARKID_EXT0 0x00000004
21#define BCMA_CORE_PCI_ARBCTL_PARKID_EXT1 0x00000006
22#define BCMA_CORE_PCI_ISTAT 0x0020
23#define BCMA_CORE_PCI_ISTAT_INTA 0x00000001
24#define BCMA_CORE_PCI_ISTAT_INTB 0x00000002
25#define BCMA_CORE_PCI_ISTAT_SERR 0x00000004
26#define BCMA_CORE_PCI_ISTAT_PERR 0x00000008
27#define BCMA_CORE_PCI_ISTAT_PME 0x00000010
28#define BCMA_CORE_PCI_IMASK 0x0024
29#define BCMA_CORE_PCI_IMASK_INTA 0x00000001
30#define BCMA_CORE_PCI_IMASK_INTB 0x00000002
31#define BCMA_CORE_PCI_IMASK_SERR 0x00000004
32#define BCMA_CORE_PCI_IMASK_PERR 0x00000008
33#define BCMA_CORE_PCI_IMASK_PME 0x00000010
34#define BCMA_CORE_PCI_MBOX 0x0028
35#define BCMA_CORE_PCI_MBOX_F0_0 0x00000100
36#define BCMA_CORE_PCI_MBOX_F0_1 0x00000200
37#define BCMA_CORE_PCI_MBOX_F1_0 0x00000400
38#define BCMA_CORE_PCI_MBOX_F1_1 0x00000800
39#define BCMA_CORE_PCI_MBOX_F2_0 0x00001000
40#define BCMA_CORE_PCI_MBOX_F2_1 0x00002000
41#define BCMA_CORE_PCI_MBOX_F3_0 0x00004000
42#define BCMA_CORE_PCI_MBOX_F3_1 0x00008000
43#define BCMA_CORE_PCI_BCAST_ADDR 0x0050
44#define BCMA_CORE_PCI_BCAST_ADDR_MASK 0x000000FF
45#define BCMA_CORE_PCI_BCAST_DATA 0x0054
46#define BCMA_CORE_PCI_GPIO_IN 0x0060
47#define BCMA_CORE_PCI_GPIO_OUT 0x0064
48#define BCMA_CORE_PCI_GPIO_ENABLE 0x0068
49#define BCMA_CORE_PCI_GPIO_CTL 0x006C
50#define BCMA_CORE_PCI_SBTOPCI0 0x0100
51#define BCMA_CORE_PCI_SBTOPCI0_MASK 0xFC000000
52#define BCMA_CORE_PCI_SBTOPCI1 0x0104
53#define BCMA_CORE_PCI_SBTOPCI1_MASK 0xFC000000
54#define BCMA_CORE_PCI_SBTOPCI2 0x0108
55#define BCMA_CORE_PCI_SBTOPCI2_MASK 0xC0000000
56#define BCMA_CORE_PCI_CONFIG_ADDR 0x0120
57#define BCMA_CORE_PCI_CONFIG_DATA 0x0124
58#define BCMA_CORE_PCI_MDIO_CONTROL 0x0128
59#define BCMA_CORE_PCI_MDIOCTL_DIVISOR_MASK 0x7f
60#define BCMA_CORE_PCI_MDIOCTL_DIVISOR_VAL 0x2
61#define BCMA_CORE_PCI_MDIOCTL_PREAM_EN 0x80
62#define BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE 0x100
63#define BCMA_CORE_PCI_MDIO_DATA 0x012c
64#define BCMA_CORE_PCI_MDIODATA_MASK 0x0000ffff
65#define BCMA_CORE_PCI_MDIODATA_TA 0x00020000
66#define BCMA_CORE_PCI_MDIODATA_REGADDR_SHF_OLD 18
67#define BCMA_CORE_PCI_MDIODATA_REGADDR_MASK_OLD 0x003c0000
68#define BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF_OLD 22
69#define BCMA_CORE_PCI_MDIODATA_DEVADDR_MASK_OLD 0x0fc00000
70#define BCMA_CORE_PCI_MDIODATA_REGADDR_SHF 18
71#define BCMA_CORE_PCI_MDIODATA_REGADDR_MASK 0x007c0000
72#define BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF 23
73#define BCMA_CORE_PCI_MDIODATA_DEVADDR_MASK 0x0f800000
74#define BCMA_CORE_PCI_MDIODATA_WRITE 0x10000000
75#define BCMA_CORE_PCI_MDIODATA_READ 0x20000000
76#define BCMA_CORE_PCI_MDIODATA_START 0x40000000
77#define BCMA_CORE_PCI_MDIODATA_DEV_ADDR 0x0
78#define BCMA_CORE_PCI_MDIODATA_BLK_ADDR 0x1F
79#define BCMA_CORE_PCI_MDIODATA_DEV_PLL 0x1d
80#define BCMA_CORE_PCI_MDIODATA_DEV_TX 0x1e
81#define BCMA_CORE_PCI_MDIODATA_DEV_RX 0x1f
82#define BCMA_CORE_PCI_PCIEIND_ADDR 0x0130
83#define BCMA_CORE_PCI_PCIEIND_DATA 0x0134
84#define BCMA_CORE_PCI_CLKREQENCTRL 0x0138
85#define BCMA_CORE_PCI_PCICFG0 0x0400
86#define BCMA_CORE_PCI_PCICFG1 0x0500
87#define BCMA_CORE_PCI_PCICFG2 0x0600
88#define BCMA_CORE_PCI_PCICFG3 0x0700
89#define BCMA_CORE_PCI_SPROM(wordoffset) (0x0800 + ((wordoffset) * 2))
90#define BCMA_CORE_PCI_SPROM_PI_OFFSET 0
91#define BCMA_CORE_PCI_SPROM_PI_MASK 0xf000
92#define BCMA_CORE_PCI_SPROM_PI_SHIFT 12
93#define BCMA_CORE_PCI_SPROM_MISC_CONFIG 5
94#define BCMA_CORE_PCI_SPROM_L23READY_EXIT_NOPERST 0x8000
95#define BCMA_CORE_PCI_SPROM_CLKREQ_OFFSET_REV5 20
96#define BCMA_CORE_PCI_SPROM_CLKREQ_ENB 0x0800
97
98
99#define BCMA_CORE_PCI_SBTOPCI_MEM 0x00000000
100#define BCMA_CORE_PCI_SBTOPCI_IO 0x00000001
101#define BCMA_CORE_PCI_SBTOPCI_CFG0 0x00000002
102#define BCMA_CORE_PCI_SBTOPCI_CFG1 0x00000003
103#define BCMA_CORE_PCI_SBTOPCI_PREF 0x00000004
104#define BCMA_CORE_PCI_SBTOPCI_BURST 0x00000008
105#define BCMA_CORE_PCI_SBTOPCI_MRM 0x00000020
106#define BCMA_CORE_PCI_SBTOPCI_RC 0x00000030
107#define BCMA_CORE_PCI_SBTOPCI_RC_READ 0x00000000
108#define BCMA_CORE_PCI_SBTOPCI_RC_READL 0x00000010
109#define BCMA_CORE_PCI_SBTOPCI_RC_READM 0x00000020
110
111
112#define BCMA_CORE_PCI_PLP_MODEREG 0x200
113#define BCMA_CORE_PCI_PLP_STATUSREG 0x204
114#define BCMA_CORE_PCI_PLP_POLARITYINV_STAT 0x10
115#define BCMA_CORE_PCI_PLP_LTSSMCTRLREG 0x208
116#define BCMA_CORE_PCI_PLP_LTLINKNUMREG 0x20c
117#define BCMA_CORE_PCI_PLP_LTLANENUMREG 0x210
118#define BCMA_CORE_PCI_PLP_LTNFTSREG 0x214
119#define BCMA_CORE_PCI_PLP_ATTNREG 0x218
120#define BCMA_CORE_PCI_PLP_ATTNMASKREG 0x21C
121#define BCMA_CORE_PCI_PLP_RXERRCTR 0x220
122#define BCMA_CORE_PCI_PLP_RXFRMERRCTR 0x224
123#define BCMA_CORE_PCI_PLP_RXERRTHRESHREG 0x228
124#define BCMA_CORE_PCI_PLP_TESTCTRLREG 0x22C
125#define BCMA_CORE_PCI_PLP_SERDESCTRLOVRDREG 0x230
126#define BCMA_CORE_PCI_PLP_TIMINGOVRDREG 0x234
127#define BCMA_CORE_PCI_PLP_RXTXSMDIAGREG 0x238
128#define BCMA_CORE_PCI_PLP_LTSSMDIAGREG 0x23C
129
130
131#define BCMA_CORE_PCI_DLLP_LCREG 0x100
132#define BCMA_CORE_PCI_DLLP_LSREG 0x104
133#define BCMA_CORE_PCI_DLLP_LAREG 0x108
134#define BCMA_CORE_PCI_DLLP_LSREG_LINKUP (1 << 16)
135#define BCMA_CORE_PCI_DLLP_LAMASKREG 0x10C
136#define BCMA_CORE_PCI_DLLP_NEXTTXSEQNUMREG 0x110
137#define BCMA_CORE_PCI_DLLP_ACKEDTXSEQNUMREG 0x114
138#define BCMA_CORE_PCI_DLLP_PURGEDTXSEQNUMREG 0x118
139#define BCMA_CORE_PCI_DLLP_RXSEQNUMREG 0x11C
140#define BCMA_CORE_PCI_DLLP_LRREG 0x120
141#define BCMA_CORE_PCI_DLLP_LACKTOREG 0x124
142#define BCMA_CORE_PCI_DLLP_PMTHRESHREG 0x128
143#define BCMA_CORE_PCI_ASPMTIMER_EXTEND 0x01000000
144#define BCMA_CORE_PCI_DLLP_RTRYWPREG 0x12C
145#define BCMA_CORE_PCI_DLLP_RTRYRPREG 0x130
146#define BCMA_CORE_PCI_DLLP_RTRYPPREG 0x134
147#define BCMA_CORE_PCI_DLLP_RTRRWREG 0x138
148#define BCMA_CORE_PCI_DLLP_ECTHRESHREG 0x13C
149#define BCMA_CORE_PCI_DLLP_TLPERRCTRREG 0x140
150#define BCMA_CORE_PCI_DLLP_ERRCTRREG 0x144
151#define BCMA_CORE_PCI_DLLP_NAKRXCTRREG 0x148
152#define BCMA_CORE_PCI_DLLP_TESTREG 0x14C
153#define BCMA_CORE_PCI_DLLP_PKTBIST 0x150
154#define BCMA_CORE_PCI_DLLP_PCIE11 0x154
155
156
157#define BCMA_CORE_PCI_SERDES_RX_CTRL 1
158#define BCMA_CORE_PCI_SERDES_RX_CTRL_FORCE 0x80
159#define BCMA_CORE_PCI_SERDES_RX_CTRL_POLARITY 0x40
160#define BCMA_CORE_PCI_SERDES_RX_TIMER1 2
161#define BCMA_CORE_PCI_SERDES_RX_CDR 6
162#define BCMA_CORE_PCI_SERDES_RX_CDRBW 7
163
164
165#define BCMA_CORE_PCI_SERDES_PLL_CTRL 1
166#define BCMA_CORE_PCI_PLL_CTRL_FREQDET_EN 0x4000
167
168
169#define BCMA_CORE_PCI_BFL_NOPCI 0x00000400
170
171
172#define BCMA_CORE_PCI_CFG_BUS_SHIFT 24
173#define BCMA_CORE_PCI_CFG_SLOT_SHIFT 19
174#define BCMA_CORE_PCI_CFG_FUN_SHIFT 16
175#define BCMA_CORE_PCI_CFG_OFF_SHIFT 0
176
177#define BCMA_CORE_PCI_CFG_BUS_MASK 0xff
178#define BCMA_CORE_PCI_CFG_SLOT_MASK 0x1f
179#define BCMA_CORE_PCI_CFG_FUN_MASK 7
180#define BCMA_CORE_PCI_CFG_OFF_MASK 0xfff
181
182#define BCMA_CORE_PCI_CFG_DEVCTRL 0xd8
183
184#define BCMA_CORE_PCI_
185
186
187#define BCMA_CORE_PCI_MDIO_IEEE0 0x000
188#define BCMA_CORE_PCI_MDIO_IEEE1 0x001
189#define BCMA_CORE_PCI_MDIO_BLK0 0x800
190#define BCMA_CORE_PCI_MDIO_BLK1 0x801
191#define BCMA_CORE_PCI_MDIO_BLK1_MGMT0 0x16
192#define BCMA_CORE_PCI_MDIO_BLK1_MGMT1 0x17
193#define BCMA_CORE_PCI_MDIO_BLK1_MGMT2 0x18
194#define BCMA_CORE_PCI_MDIO_BLK1_MGMT3 0x19
195#define BCMA_CORE_PCI_MDIO_BLK1_MGMT4 0x1A
196#define BCMA_CORE_PCI_MDIO_BLK2 0x802
197#define BCMA_CORE_PCI_MDIO_BLK3 0x803
198#define BCMA_CORE_PCI_MDIO_BLK4 0x804
199#define BCMA_CORE_PCI_MDIO_TXPLL 0x808
200#define BCMA_CORE_PCI_MDIO_TXCTRL0 0x820
201#define BCMA_CORE_PCI_MDIO_SERDESID 0x831
202#define BCMA_CORE_PCI_MDIO_RXCTRL0 0x840
203
204
205#define BCMA_CORE_PCI_RC_CRS_VISIBILITY 0x0001
206
207struct bcma_drv_pci;
208struct bcma_bus;
209
210#ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE
211struct bcma_drv_pci_host {
212 struct bcma_drv_pci *pdev;
213
214 u32 host_cfg_addr;
215 spinlock_t cfgspace_lock;
216
217 struct pci_controller pci_controller;
218 struct pci_ops pci_ops;
219 struct resource mem_resource;
220 struct resource io_resource;
221};
222#endif
223
224struct bcma_drv_pci {
225 struct bcma_device *core;
226 u8 setup_done:1;
227 u8 hostmode:1;
228
229#ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE
230 struct bcma_drv_pci_host *host_controller;
231#endif
232};
233
234
235#define pcicore_read16(pc, offset) bcma_read16((pc)->core, offset)
236#define pcicore_read32(pc, offset) bcma_read32((pc)->core, offset)
237#define pcicore_write16(pc, offset, val) bcma_write16((pc)->core, offset, val)
238#define pcicore_write32(pc, offset, val) bcma_write32((pc)->core, offset, val)
239
240extern void bcma_core_pci_init(struct bcma_drv_pci *pc);
241extern int bcma_core_pci_irq_ctl(struct bcma_drv_pci *pc,
242 struct bcma_device *core, bool enable);
243extern void bcma_core_pci_up(struct bcma_bus *bus);
244extern void bcma_core_pci_down(struct bcma_bus *bus);
245extern void bcma_core_pci_power_save(struct bcma_bus *bus, bool up);
246
247extern int bcma_core_pci_pcibios_map_irq(const struct pci_dev *dev);
248extern int bcma_core_pci_plat_dev_init(struct pci_dev *dev);
249
250#endif
251