1/* 2 * lm49453.h - LM49453 ALSA Soc Audio drive 3 * 4 * Copyright (c) 2012 Texas Instruments, Inc 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; version 2 of the License. 9 * 10 */ 11 12#ifndef _LM49453_H 13#define _LM49453_H 14 15#include <linux/bitops.h> 16 17/* LM49453_P0 register space for page0 */ 18#define LM49453_P0_PMC_SETUP_REG 0x00 19#define LM49453_P0_PLL_CLK_SEL1_REG 0x01 20#define LM49453_P0_PLL_CLK_SEL2_REG 0x02 21#define LM49453_P0_PMC_CLK_DIV_REG 0x03 22#define LM49453_P0_HSDET_CLK_DIV_REG 0x04 23#define LM49453_P0_DMIC_CLK_DIV_REG 0x05 24#define LM49453_P0_ADC_CLK_DIV_REG 0x06 25#define LM49453_P0_DAC_OT_CLK_DIV_REG 0x07 26#define LM49453_P0_PLL_HF_M_REG 0x08 27#define LM49453_P0_PLL_LF_M_REG 0x09 28#define LM49453_P0_PLL_NL_REG 0x0A 29#define LM49453_P0_PLL_N_MODL_REG 0x0B 30#define LM49453_P0_PLL_N_MODH_REG 0x0C 31#define LM49453_P0_PLL_P1_REG 0x0D 32#define LM49453_P0_PLL_P2_REG 0x0E 33#define LM49453_P0_FLL_REF_FREQL_REG 0x0F 34#define LM49453_P0_FLL_REF_FREQH_REG 0x10 35#define LM49453_P0_VCO_TARGETLL_REG 0x11 36#define LM49453_P0_VCO_TARGETLH_REG 0x12 37#define LM49453_P0_VCO_TARGETHL_REG 0x13 38#define LM49453_P0_VCO_TARGETHH_REG 0x14 39#define LM49453_P0_PLL_CONFIG_REG 0x15 40#define LM49453_P0_DAC_CLK_SEL_REG 0x16 41#define LM49453_P0_DAC_HP_CLK_DIV_REG 0x17 42 43/* Analog Mixer Input Stages */ 44#define LM49453_P0_MICL_REG 0x20 45#define LM49453_P0_MICR_REG 0x21 46#define LM49453_P0_EP_REG 0x24 47#define LM49453_P0_DIS_PKVL_FB_REG 0x25 48 49/* Analog Mixer Output Stages */ 50#define LM49453_P0_ANALOG_MIXER_ADC_REG 0x2E 51 52/*ADC or DAC */ 53#define LM49453_P0_ADC_DSP_REG 0x30 54#define LM49453_P0_DAC_DSP_REG 0x31 55 56/* EFFECTS ENABLES */ 57#define LM49453_P0_ADC_FX_ENABLES_REG 0x33 58 59/* GPIO */ 60#define LM49453_P0_GPIO1_REG 0x38 61#define LM49453_P0_GPIO2_REG 0x39 62#define LM49453_P0_GPIO3_REG 0x3A 63#define LM49453_P0_HAP_CTL_REG 0x3B 64#define LM49453_P0_HAP_FREQ_PROG_LEFTL_REG 0x3C 65#define LM49453_P0_HAP_FREQ_PROG_LEFTH_REG 0x3D 66#define LM49453_P0_HAP_FREQ_PROG_RIGHTL_REG 0x3E 67#define LM49453_P0_HAP_FREQ_PROG_RIGHTH_REG 0x3F 68 69/* DIGITAL MIXER */ 70#define LM49453_P0_DMIX_CLK_SEL_REG 0x40 71#define LM49453_P0_PORT1_RX_LVL1_REG 0x41 72#define LM49453_P0_PORT1_RX_LVL2_REG 0x42 73#define LM49453_P0_PORT2_RX_LVL_REG 0x43 74#define LM49453_P0_PORT1_TX1_REG 0x44 75#define LM49453_P0_PORT1_TX2_REG 0x45 76#define LM49453_P0_PORT1_TX3_REG 0x46 77#define LM49453_P0_PORT1_TX4_REG 0x47 78#define LM49453_P0_PORT1_TX5_REG 0x48 79#define LM49453_P0_PORT1_TX6_REG 0x49 80#define LM49453_P0_PORT1_TX7_REG 0x4A 81#define LM49453_P0_PORT1_TX8_REG 0x4B 82#define LM49453_P0_PORT2_TX1_REG 0x4C 83#define LM49453_P0_PORT2_TX2_REG 0x4D 84#define LM49453_P0_STN_SEL_REG 0x4F 85#define LM49453_P0_DACHPL1_REG 0x50 86#define LM49453_P0_DACHPL2_REG 0x51 87#define LM49453_P0_DACHPR1_REG 0x52 88#define LM49453_P0_DACHPR2_REG 0x53 89#define LM49453_P0_DACLOL1_REG 0x54 90#define LM49453_P0_DACLOL2_REG 0x55 91#define LM49453_P0_DACLOR1_REG 0x56 92#define LM49453_P0_DACLOR2_REG 0x57 93#define LM49453_P0_DACLSL1_REG 0x58 94#define LM49453_P0_DACLSL2_REG 0x59 95#define LM49453_P0_DACLSR1_REG 0x5A 96#define LM49453_P0_DACLSR2_REG 0x5B 97#define LM49453_P0_DACHAL1_REG 0x5C 98#define LM49453_P0_DACHAL2_REG 0x5D 99#define LM49453_P0_DACHAR1_REG 0x5E 100#define LM49453_P0_DACHAR2_REG 0x5F 101 102/* AUDIO PORT 1 (TDM) */ 103#define LM49453_P0_AUDIO_PORT1_BASIC_REG 0x60 104#define LM49453_P0_AUDIO_PORT1_CLK_GEN1_REG 0x61 105#define LM49453_P0_AUDIO_PORT1_CLK_GEN2_REG 0x62 106#define LM49453_P0_AUDIO_PORT1_CLK_GEN3_REG 0x63 107#define LM49453_P0_AUDIO_PORT1_SYNC_RATE_REG 0x64 108#define LM49453_P0_AUDIO_PORT1_SYNC_SDO_SETUP_REG 0x65 109#define LM49453_P0_AUDIO_PORT1_DATA_WIDTH_REG 0x66 110#define LM49453_P0_AUDIO_PORT1_RX_MSB_REG 0x67 111#define LM49453_P0_AUDIO_PORT1_TX_MSB_REG 0x68 112#define LM49453_P0_AUDIO_PORT1_TDM_CHANNELS_REG 0x69 113 114/* AUDIO PORT 2 */ 115#define LM49453_P0_AUDIO_PORT2_BASIC_REG 0x6A 116#define LM49453_P0_AUDIO_PORT2_CLK_GEN1_REG 0x6B 117#define LM49453_P0_AUDIO_PORT2_CLK_GEN2_REG 0x6C 118#define LM49453_P0_AUDIO_PORT2_SYNC_GEN_REG 0x6D 119#define LM49453_P0_AUDIO_PORT2_DATA_WIDTH_REG 0x6E 120#define LM49453_P0_AUDIO_PORT2_RX_MODE_REG 0x6F 121#define LM49453_P0_AUDIO_PORT2_TX_MODE_REG 0x70 122 123/* SAMPLE RATE */ 124#define LM49453_P0_PORT1_SR_LSB_REG 0x79 125#define LM49453_P0_PORT1_SR_MSB_REG 0x7A 126#define LM49453_P0_PORT2_SR_LSB_REG 0x7B 127#define LM49453_P0_PORT2_SR_MSB_REG 0x7C 128 129/* EFFECTS - HPFs */ 130#define LM49453_P0_HPF_REG 0x80 131 132/* EFFECTS ADC ALC */ 133#define LM49453_P0_ADC_ALC1_REG 0x82 134#define LM49453_P0_ADC_ALC2_REG 0x83 135#define LM49453_P0_ADC_ALC3_REG 0x84 136#define LM49453_P0_ADC_ALC4_REG 0x85 137#define LM49453_P0_ADC_ALC5_REG 0x86 138#define LM49453_P0_ADC_ALC6_REG 0x87 139#define LM49453_P0_ADC_ALC7_REG 0x88 140#define LM49453_P0_ADC_ALC8_REG 0x89 141#define LM49453_P0_DMIC1_LEVELL_REG 0x8A 142#define LM49453_P0_DMIC1_LEVELR_REG 0x8B 143#define LM49453_P0_DMIC2_LEVELL_REG 0x8C 144#define LM49453_P0_DMIC2_LEVELR_REG 0x8D 145#define LM49453_P0_ADC_LEVELL_REG 0x8E 146#define LM49453_P0_ADC_LEVELR_REG 0x8F 147#define LM49453_P0_DAC_HP_LEVELL_REG 0x90 148#define LM49453_P0_DAC_HP_LEVELR_REG 0x91 149#define LM49453_P0_DAC_LO_LEVELL_REG 0x92 150#define LM49453_P0_DAC_LO_LEVELR_REG 0x93 151#define LM49453_P0_DAC_LS_LEVELL_REG 0x94 152#define LM49453_P0_DAC_LS_LEVELR_REG 0x95 153#define LM49453_P0_DAC_HA_LEVELL_REG 0x96 154#define LM49453_P0_DAC_HA_LEVELR_REG 0x97 155#define LM49453_P0_SOFT_MUTE_REG 0x98 156#define LM49453_P0_DMIC_MUTE_CFG_REG 0x99 157#define LM49453_P0_ADC_MUTE_CFG_REG 0x9A 158#define LM49453_P0_DAC_MUTE_CFG_REG 0x9B 159 160/*DIGITAL MIC1 */ 161#define LM49453_P0_DIGITAL_MIC1_CONFIG_REG 0xB0 162#define LM49453_P0_DIGITAL_MIC1_DATA_DELAYL_REG 0xB1 163#define LM49453_P0_DIGITAL_MIC1_DATA_DELAYR_REG 0xB2 164 165/*DIGITAL MIC2 */ 166#define LM49453_P0_DIGITAL_MIC2_CONFIG_REG 0xB3 167#define LM49453_P0_DIGITAL_MIC2_DATA_DELAYL_REG 0xB4 168#define LM49453_P0_DIGITAL_MIC2_DATA_DELAYR_REG 0xB5 169 170/* ADC DECIMATOR */ 171#define LM49453_P0_ADC_DECIMATOR_REG 0xB6 172 173/* DAC CONFIGURE */ 174#define LM49453_P0_DAC_CONFIG_REG 0xB7 175 176/* SIDETONE */ 177#define LM49453_P0_STN_VOL_ADCL_REG 0xB8 178#define LM49453_P0_STN_VOL_ADCR_REG 0xB9 179#define LM49453_P0_STN_VOL_DMIC1L_REG 0xBA 180#define LM49453_P0_STN_VOL_DMIC1R_REG 0xBB 181#define LM49453_P0_STN_VOL_DMIC2L_REG 0xBC 182#define LM49453_P0_STN_VOL_DMIC2R_REG 0xBD 183 184/* ADC/DAC CLIPPING MONITORS (Read Only/Write to Clear) */ 185#define LM49453_P0_ADC_DEC_CLIP_REG 0xC2 186#define LM49453_P0_ADC_HPF_CLIP_REG 0xC3 187#define LM49453_P0_ADC_LVL_CLIP_REG 0xC4 188#define LM49453_P0_DAC_LVL_CLIP_REG 0xC5 189 190/* ADC ALC EFFECT MONITORS (Read Only) */ 191#define LM49453_P0_ADC_LVLMONL_REG 0xC8 192#define LM49453_P0_ADC_LVLMONR_REG 0xC9 193#define LM49453_P0_ADC_ALCMONL_REG 0xCA 194#define LM49453_P0_ADC_ALCMONR_REG 0xCB 195#define LM49453_P0_ADC_MUTED_REG 0xCC 196#define LM49453_P0_DAC_MUTED_REG 0xCD 197 198/* HEADSET DETECT */ 199#define LM49453_P0_HSD_PPB_LONG_CNT_LIMITL_REG 0xD0 200#define LM49453_P0_HSD_PPB_LONG_CNT_LIMITR_REG 0xD1 201#define LM49453_P0_HSD_PIN3_4_EX_LOOP_CNT_LIMITL_REG 0xD2 202#define LM49453_P0_HSD_PIN3_4_EX_LOOP_CNT_LIMITH_REG 0xD3 203#define LM49453_P0_HSD_TIMEOUT1_REG 0xD4 204#define LM49453_P0_HSD_TIMEOUT2_REG 0xD5 205#define LM49453_P0_HSD_TIMEOUT3_REG 0xD6 206#define LM49453_P0_HSD_PIN3_4_CFG_REG 0xD7 207#define LM49453_P0_HSD_IRQ1_REG 0xD8 208#define LM49453_P0_HSD_IRQ2_REG 0xD9 209#define LM49453_P0_HSD_IRQ3_REG 0xDA 210#define LM49453_P0_HSD_IRQ4_REG 0xDB 211#define LM49453_P0_HSD_IRQ_MASK1_REG 0xDC 212#define LM49453_P0_HSD_IRQ_MASK2_REG 0xDD 213#define LM49453_P0_HSD_IRQ_MASK3_REG 0xDE 214#define LM49453_P0_HSD_R_HPLL_REG 0xE0 215#define LM49453_P0_HSD_R_HPLH_REG 0xE1 216#define LM49453_P0_HSD_R_HPLU_REG 0xE2 217#define LM49453_P0_HSD_R_HPRL_REG 0xE3 218#define LM49453_P0_HSD_R_HPRH_REG 0xE4 219#define LM49453_P0_HSD_R_HPRU_REG 0xE5 220#define LM49453_P0_HSD_VEL_L_FINALL_REG 0xE6 221#define LM49453_P0_HSD_VEL_L_FINALH_REG 0xE7 222#define LM49453_P0_HSD_VEL_L_FINALU_REG 0xE8 223#define LM49453_P0_HSD_RO_FINALL_REG 0xE9 224#define LM49453_P0_HSD_RO_FINALH_REG 0xEA 225#define LM49453_P0_HSD_RO_FINALU_REG 0xEB 226#define LM49453_P0_HSD_VMIC_BIAS_FINALL_REG 0xEC 227#define LM49453_P0_HSD_VMIC_BIAS_FINALH_REG 0xED 228#define LM49453_P0_HSD_VMIC_BIAS_FINALU_REG 0xEE 229#define LM49453_P0_HSD_PIN_CONFIG_REG 0xEF 230#define LM49453_P0_HSD_PLUG_DETECT_BB_IRQ_STATUS1_REG 0xF1 231#define LM49453_P0_HSD_PLUG_DETECT_BB_IRQ_STATUS2_REG 0xF2 232#define LM49453_P0_HSD_PLUG_DETECT_BB_IRQ_STATUS3_REG 0xF3 233#define LM49453_P0_HSD_PLUG_DETECT_BB_IRQ_STATEL_REG 0xF4 234#define LM49453_P0_HSD_PLUG_DETECT_BB_IRQ_STATEH_REG 0xF5 235 236/* I/O PULLDOWN CONFIG */ 237#define LM49453_P0_PULL_CONFIG1_REG 0xF8 238#define LM49453_P0_PULL_CONFIG2_REG 0xF9 239#define LM49453_P0_PULL_CONFIG3_REG 0xFA 240 241/* RESET */ 242#define LM49453_P0_RESET_REG 0xFE 243 244/* PAGE */ 245#define LM49453_PAGE_REG 0xFF 246 247#define LM49453_MAX_REGISTER (0xFF+1) 248 249/* LM49453_P0_PMC_SETUP_REG (0x00h) */ 250#define LM49453_PMC_SETUP_CHIP_EN (BIT(1)|BIT(0)) 251#define LM49453_PMC_SETUP_PLL_EN BIT(2) 252#define LM49453_PMC_SETUP_PLL_P2_EN BIT(3) 253#define LM49453_PMC_SETUP_PLL_FLL BIT(4) 254#define LM49453_PMC_SETUP_MCLK_OVER BIT(5) 255#define LM49453_PMC_SETUP_RTC_CLK_OVER BIT(6) 256#define LM49453_PMC_SETUP_CHIP_ACTIVE BIT(7) 257 258/* Chip Enable bits */ 259#define LM49453_CHIP_EN_SHUTDOWN 0x00 260#define LM49453_CHIP_EN 0x01 261#define LM49453_CHIP_EN_HSD_DETECT 0x02 262#define LM49453_CHIP_EN_INVALID_HSD 0x03 263 264/* LM49453_P0_PLL_CLK_SEL1_REG (0x01h) */ 265#define LM49453_CLK_SEL1_MCLK_SEL 0x11 266#define LM49453_CLK_SEL1_RTC_SEL 0x11 267#define LM49453_CLK_SEL1_PORT1_SEL 0x10 268#define LM49453_CLK_SEL1_PORT2_SEL 0x11 269 270/* LM49453_P0_PLL_CLK_SEL2_REG (0x02h) */ 271#define LM49453_CLK_SEL2_ADC_CLK_SEL 0x38 272 273/* LM49453_P0_FLL_REF_FREQL_REG (0x0F) */ 274#define LM49453_FLL_REF_FREQ_VAL 0x8ca0001 275 276/* LM49453_P0_VCO_TARGETLL_REG (0x11) */ 277#define LM49453_VCO_TARGET_VAL 0x8ca0001 278 279/* LM49453_P0_ADC_DSP_REG (0x30h) */ 280#define LM49453_ADC_DSP_ADC_MUTEL BIT(0) 281#define LM49453_ADC_DSP_ADC_MUTER BIT(1) 282#define LM49453_ADC_DSP_DMIC1_MUTEL BIT(2) 283#define LM49453_ADC_DSP_DMIC1_MUTER BIT(3) 284#define LM49453_ADC_DSP_DMIC2_MUTEL BIT(4) 285#define LM49453_ADC_DSP_DMIC2_MUTER BIT(5) 286#define LM49453_ADC_DSP_MUTE_ALL 0x3F 287 288/* LM49453_P0_DAC_DSP_REG (0x31h) */ 289#define LM49453_DAC_DSP_MUTE_ALL 0xFF 290 291/* LM49453_P0_AUDIO_PORT1_BASIC_REG (0x60h) */ 292#define LM49453_AUDIO_PORT1_BASIC_FMT_MASK (BIT(4)|BIT(3)) 293#define LM49453_AUDIO_PORT1_BASIC_CLK_MS BIT(3) 294#define LM49453_AUDIO_PORT1_BASIC_SYNC_MS BIT(4) 295 296/* LM49453_P0_RESET_REG (0xFEh) */ 297#define LM49453_RESET_REG_RST BIT(0) 298 299/* Page select register bits (0xFF) */ 300#define LM49453_PAGE0_SELECT 0x0 301#define LM49453_PAGE1_SELECT 0x1 302 303/* LM49453_P0_HSD_PIN3_4_CFG_REG (Jack Pin config - 0xD7) */ 304#define LM49453_JACK_DISABLE 0x00 305#define LM49453_JACK_CONFIG1 0x01 306#define LM49453_JACK_CONFIG2 0x02 307#define LM49453_JACK_CONFIG3 0x03 308#define LM49453_JACK_CONFIG4 0x04 309#define LM49453_JACK_CONFIG5 0x05 310 311/* Page 1 REGISTERS */ 312 313/* SIDETONE */ 314#define LM49453_P1_SIDETONE_SA0L_REG 0x80 315#define LM49453_P1_SIDETONE_SA0H_REG 0x81 316#define LM49453_P1_SIDETONE_SAB0U_REG 0x82 317#define LM49453_P1_SIDETONE_SB0L_REG 0x83 318#define LM49453_P1_SIDETONE_SB0H_REG 0x84 319#define LM49453_P1_SIDETONE_SH0L_REG 0x85 320#define LM49453_P1_SIDETONE_SH0H_REG 0x86 321#define LM49453_P1_SIDETONE_SH0U_REG 0x87 322#define LM49453_P1_SIDETONE_SA1L_REG 0x88 323#define LM49453_P1_SIDETONE_SA1H_REG 0x89 324#define LM49453_P1_SIDETONE_SAB1U_REG 0x8A 325#define LM49453_P1_SIDETONE_SB1L_REG 0x8B 326#define LM49453_P1_SIDETONE_SB1H_REG 0x8C 327#define LM49453_P1_SIDETONE_SH1L_REG 0x8D 328#define LM49453_P1_SIDETONE_SH1H_REG 0x8E 329#define LM49453_P1_SIDETONE_SH1U_REG 0x8F 330#define LM49453_P1_SIDETONE_SA2L_REG 0x90 331#define LM49453_P1_SIDETONE_SA2H_REG 0x91 332#define LM49453_P1_SIDETONE_SAB2U_REG 0x92 333#define LM49453_P1_SIDETONE_SB2L_REG 0x93 334#define LM49453_P1_SIDETONE_SB2H_REG 0x94 335#define LM49453_P1_SIDETONE_SH2L_REG 0x95 336#define LM49453_P1_SIDETONE_SH2H_REG 0x96 337#define LM49453_P1_SIDETONE_SH2U_REG 0x97 338#define LM49453_P1_SIDETONE_SA3L_REG 0x98 339#define LM49453_P1_SIDETONE_SA3H_REG 0x99 340#define LM49453_P1_SIDETONE_SAB3U_REG 0x9A 341#define LM49453_P1_SIDETONE_SB3L_REG 0x9B 342#define LM49453_P1_SIDETONE_SB3H_REG 0x9C 343#define LM49453_P1_SIDETONE_SH3L_REG 0x9D 344#define LM49453_P1_SIDETONE_SH3H_REG 0x9E 345#define LM49453_P1_SIDETONE_SH3U_REG 0x9F 346#define LM49453_P1_SIDETONE_SA4L_REG 0xA0 347#define LM49453_P1_SIDETONE_SA4H_REG 0xA1 348#define LM49453_P1_SIDETONE_SAB4U_REG 0xA2 349#define LM49453_P1_SIDETONE_SB4L_REG 0xA3 350#define LM49453_P1_SIDETONE_SB4H_REG 0xA4 351#define LM49453_P1_SIDETONE_SH4L_REG 0xA5 352#define LM49453_P1_SIDETONE_SH4H_REG 0xA6 353#define LM49453_P1_SIDETONE_SH4U_REG 0xA7 354#define LM49453_P1_SIDETONE_SA5L_REG 0xA8 355#define LM49453_P1_SIDETONE_SA5H_REG 0xA9 356#define LM49453_P1_SIDETONE_SAB5U_REG 0xAA 357#define LM49453_P1_SIDETONE_SB5L_REG 0xAB 358#define LM49453_P1_SIDETONE_SB5H_REG 0xAC 359#define LM49453_P1_SIDETONE_SH5L_REG 0xAD 360#define LM49453_P1_SIDETONE_SH5H_REG 0xAE 361#define LM49453_P1_SIDETONE_SH5U_REG 0xAF 362 363/* CHARGE PUMP CONFIG */ 364#define LM49453_P1_CP_CONFIG1_REG 0xB0 365#define LM49453_P1_CP_CONFIG2_REG 0xB1 366#define LM49453_P1_CP_CONFIG3_REG 0xB2 367#define LM49453_P1_CP_CONFIG4_REG 0xB3 368#define LM49453_P1_CP_LA_VTH1L_REG 0xB4 369#define LM49453_P1_CP_LA_VTH1M_REG 0xB5 370#define LM49453_P1_CP_LA_VTH2L_REG 0xB6 371#define LM49453_P1_CP_LA_VTH2M_REG 0xB7 372#define LM49453_P1_CP_LA_VTH3L_REG 0xB8 373#define LM49453_P1_CP_LA_VTH3H_REG 0xB9 374#define LM49453_P1_CP_CLK_DIV_REG 0xBA 375 376/* DAC */ 377#define LM49453_P1_DAC_CHOP_REG 0xC0 378 379#define LM49453_CLK_SRC_MCLK 1 380#endif 381