1/* 2 * TI DaVinci Audio definitions 3 */ 4#ifndef __ASM_ARCH_DAVINCI_ASP_H 5#define __ASM_ARCH_DAVINCI_ASP_H 6 7/* Bases of dm644x and dm355 register banks */ 8#define DAVINCI_ASP0_BASE 0x01E02000 9#define DAVINCI_ASP1_BASE 0x01E04000 10 11/* Bases of dm365 register banks */ 12#define DAVINCI_DM365_ASP0_BASE 0x01D02000 13 14/* Bases of dm646x register banks */ 15#define DAVINCI_DM646X_MCASP0_REG_BASE 0x01D01000 16#define DAVINCI_DM646X_MCASP1_REG_BASE 0x01D01800 17 18/* Bases of da850/da830 McASP0 register banks */ 19#define DAVINCI_DA8XX_MCASP0_REG_BASE 0x01D00000 20 21/* Bases of da830 McASP1 register banks */ 22#define DAVINCI_DA830_MCASP1_REG_BASE 0x01D04000 23 24/* EDMA channels of dm644x and dm355 */ 25#define DAVINCI_DMA_ASP0_TX 2 26#define DAVINCI_DMA_ASP0_RX 3 27#define DAVINCI_DMA_ASP1_TX 8 28#define DAVINCI_DMA_ASP1_RX 9 29 30/* EDMA channels of dm646x */ 31#define DAVINCI_DM646X_DMA_MCASP0_AXEVT0 6 32#define DAVINCI_DM646X_DMA_MCASP0_AREVT0 9 33#define DAVINCI_DM646X_DMA_MCASP1_AXEVT1 12 34 35/* EDMA channels of da850/da830 McASP0 */ 36#define DAVINCI_DA8XX_DMA_MCASP0_AREVT 0 37#define DAVINCI_DA8XX_DMA_MCASP0_AXEVT 1 38 39/* EDMA channels of da830 McASP1 */ 40#define DAVINCI_DA830_DMA_MCASP1_AREVT 2 41#define DAVINCI_DA830_DMA_MCASP1_AXEVT 3 42 43/* Interrupts */ 44#define DAVINCI_ASP0_RX_INT IRQ_MBRINT 45#define DAVINCI_ASP0_TX_INT IRQ_MBXINT 46#define DAVINCI_ASP1_RX_INT IRQ_MBRINT 47#define DAVINCI_ASP1_TX_INT IRQ_MBXINT 48 49#endif /* __ASM_ARCH_DAVINCI_ASP_H */ 50