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13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/module.h>
16
17#include <asm/mipsregs.h>
18#include <asm/mach-ralink/ralink_regs.h>
19#include <asm/mach-ralink/mt7620.h>
20#include <asm/mach-ralink/pinmux.h>
21
22#include "common.h"
23
24
25#define PMU0_CFG 0x88
26#define PMU_SW_SET BIT(28)
27#define A_DCDC_EN BIT(24)
28#define A_SSC_PERI BIT(19)
29#define A_SSC_GEN BIT(18)
30#define A_SSC_M 0x3
31#define A_SSC_S 16
32#define A_DLY_M 0x7
33#define A_DLY_S 8
34#define A_VTUNE_M 0xff
35
36
37#define PMU1_CFG 0x8C
38#define DIG_SW_SEL BIT(25)
39
40
41enum mt762x_soc_type mt762x_soc;
42
43
44static int dram_type;
45
46static struct rt2880_pmx_func i2c_grp[] = { FUNC("i2c", 0, 1, 2) };
47static struct rt2880_pmx_func spi_grp[] = { FUNC("spi", 0, 3, 4) };
48static struct rt2880_pmx_func uartlite_grp[] = { FUNC("uartlite", 0, 15, 2) };
49static struct rt2880_pmx_func mdio_grp[] = { FUNC("mdio", 0, 22, 2) };
50static struct rt2880_pmx_func rgmii1_grp[] = { FUNC("rgmii1", 0, 24, 12) };
51static struct rt2880_pmx_func refclk_grp[] = { FUNC("spi refclk", 0, 37, 3) };
52static struct rt2880_pmx_func ephy_grp[] = { FUNC("ephy", 0, 40, 5) };
53static struct rt2880_pmx_func rgmii2_grp[] = { FUNC("rgmii2", 0, 60, 12) };
54static struct rt2880_pmx_func wled_grp[] = { FUNC("wled", 0, 72, 1) };
55static struct rt2880_pmx_func pa_grp[] = { FUNC("pa", 0, 18, 4) };
56static struct rt2880_pmx_func uartf_grp[] = {
57 FUNC("uartf", MT7620_GPIO_MODE_UARTF, 7, 8),
58 FUNC("pcm uartf", MT7620_GPIO_MODE_PCM_UARTF, 7, 8),
59 FUNC("pcm i2s", MT7620_GPIO_MODE_PCM_I2S, 7, 8),
60 FUNC("i2s uartf", MT7620_GPIO_MODE_I2S_UARTF, 7, 8),
61 FUNC("pcm gpio", MT7620_GPIO_MODE_PCM_GPIO, 11, 4),
62 FUNC("gpio uartf", MT7620_GPIO_MODE_GPIO_UARTF, 7, 4),
63 FUNC("gpio i2s", MT7620_GPIO_MODE_GPIO_I2S, 7, 4),
64};
65static struct rt2880_pmx_func wdt_grp[] = {
66 FUNC("wdt rst", 0, 17, 1),
67 FUNC("wdt refclk", 0, 17, 1),
68 };
69static struct rt2880_pmx_func pcie_rst_grp[] = {
70 FUNC("pcie rst", MT7620_GPIO_MODE_PCIE_RST, 36, 1),
71 FUNC("pcie refclk", MT7620_GPIO_MODE_PCIE_REF, 36, 1)
72};
73static struct rt2880_pmx_func nd_sd_grp[] = {
74 FUNC("nand", MT7620_GPIO_MODE_NAND, 45, 15),
75 FUNC("sd", MT7620_GPIO_MODE_SD, 45, 15)
76};
77
78static struct rt2880_pmx_group mt7620a_pinmux_data[] = {
79 GRP("i2c", i2c_grp, 1, MT7620_GPIO_MODE_I2C),
80 GRP("uartf", uartf_grp, MT7620_GPIO_MODE_UART0_MASK,
81 MT7620_GPIO_MODE_UART0_SHIFT),
82 GRP("spi", spi_grp, 1, MT7620_GPIO_MODE_SPI),
83 GRP("uartlite", uartlite_grp, 1, MT7620_GPIO_MODE_UART1),
84 GRP_G("wdt", wdt_grp, MT7620_GPIO_MODE_WDT_MASK,
85 MT7620_GPIO_MODE_WDT_GPIO, MT7620_GPIO_MODE_WDT_SHIFT),
86 GRP("mdio", mdio_grp, 1, MT7620_GPIO_MODE_MDIO),
87 GRP("rgmii1", rgmii1_grp, 1, MT7620_GPIO_MODE_RGMII1),
88 GRP("spi refclk", refclk_grp, 1, MT7620_GPIO_MODE_SPI_REF_CLK),
89 GRP_G("pcie", pcie_rst_grp, MT7620_GPIO_MODE_PCIE_MASK,
90 MT7620_GPIO_MODE_PCIE_GPIO, MT7620_GPIO_MODE_PCIE_SHIFT),
91 GRP_G("nd_sd", nd_sd_grp, MT7620_GPIO_MODE_ND_SD_MASK,
92 MT7620_GPIO_MODE_ND_SD_GPIO, MT7620_GPIO_MODE_ND_SD_SHIFT),
93 GRP("rgmii2", rgmii2_grp, 1, MT7620_GPIO_MODE_RGMII2),
94 GRP("wled", wled_grp, 1, MT7620_GPIO_MODE_WLED),
95 GRP("ephy", ephy_grp, 1, MT7620_GPIO_MODE_EPHY),
96 GRP("pa", pa_grp, 1, MT7620_GPIO_MODE_PA),
97 { 0 }
98};
99
100static struct rt2880_pmx_func pwm1_grp_mt7628[] = {
101 FUNC("sdcx", 3, 19, 1),
102 FUNC("utif", 2, 19, 1),
103 FUNC("gpio", 1, 19, 1),
104 FUNC("pwm", 0, 19, 1),
105};
106
107static struct rt2880_pmx_func pwm0_grp_mt7628[] = {
108 FUNC("sdcx", 3, 18, 1),
109 FUNC("utif", 2, 18, 1),
110 FUNC("gpio", 1, 18, 1),
111 FUNC("pwm", 0, 18, 1),
112};
113
114static struct rt2880_pmx_func uart2_grp_mt7628[] = {
115 FUNC("sdcx", 3, 20, 2),
116 FUNC("pwm", 2, 20, 2),
117 FUNC("gpio", 1, 20, 2),
118 FUNC("uart", 0, 20, 2),
119};
120
121static struct rt2880_pmx_func uart1_grp_mt7628[] = {
122 FUNC("sdcx", 3, 45, 2),
123 FUNC("pwm", 2, 45, 2),
124 FUNC("gpio", 1, 45, 2),
125 FUNC("uart", 0, 45, 2),
126};
127
128static struct rt2880_pmx_func i2c_grp_mt7628[] = {
129 FUNC("-", 3, 4, 2),
130 FUNC("debug", 2, 4, 2),
131 FUNC("gpio", 1, 4, 2),
132 FUNC("i2c", 0, 4, 2),
133};
134
135static struct rt2880_pmx_func refclk_grp_mt7628[] = { FUNC("reclk", 0, 36, 1) };
136static struct rt2880_pmx_func perst_grp_mt7628[] = { FUNC("perst", 0, 37, 1) };
137static struct rt2880_pmx_func wdt_grp_mt7628[] = { FUNC("wdt", 0, 15, 38) };
138static struct rt2880_pmx_func spi_grp_mt7628[] = { FUNC("spi", 0, 7, 4) };
139
140static struct rt2880_pmx_func sd_mode_grp_mt7628[] = {
141 FUNC("jtag", 3, 22, 8),
142 FUNC("utif", 2, 22, 8),
143 FUNC("gpio", 1, 22, 8),
144 FUNC("sdcx", 0, 22, 8),
145};
146
147static struct rt2880_pmx_func uart0_grp_mt7628[] = {
148 FUNC("-", 3, 12, 2),
149 FUNC("-", 2, 12, 2),
150 FUNC("gpio", 1, 12, 2),
151 FUNC("uart", 0, 12, 2),
152};
153
154static struct rt2880_pmx_func i2s_grp_mt7628[] = {
155 FUNC("antenna", 3, 0, 4),
156 FUNC("pcm", 2, 0, 4),
157 FUNC("gpio", 1, 0, 4),
158 FUNC("i2s", 0, 0, 4),
159};
160
161static struct rt2880_pmx_func spi_cs1_grp_mt7628[] = {
162 FUNC("-", 3, 6, 1),
163 FUNC("refclk", 2, 6, 1),
164 FUNC("gpio", 1, 6, 1),
165 FUNC("spi", 0, 6, 1),
166};
167
168static struct rt2880_pmx_func spis_grp_mt7628[] = {
169 FUNC("pwm", 3, 14, 4),
170 FUNC("util", 2, 14, 4),
171 FUNC("gpio", 1, 14, 4),
172 FUNC("spis", 0, 14, 4),
173};
174
175static struct rt2880_pmx_func gpio_grp_mt7628[] = {
176 FUNC("pcie", 3, 11, 1),
177 FUNC("refclk", 2, 11, 1),
178 FUNC("gpio", 1, 11, 1),
179 FUNC("gpio", 0, 11, 1),
180};
181
182#define MT7628_GPIO_MODE_MASK 0x3
183
184#define MT7628_GPIO_MODE_PWM1 30
185#define MT7628_GPIO_MODE_PWM0 28
186#define MT7628_GPIO_MODE_UART2 26
187#define MT7628_GPIO_MODE_UART1 24
188#define MT7628_GPIO_MODE_I2C 20
189#define MT7628_GPIO_MODE_REFCLK 18
190#define MT7628_GPIO_MODE_PERST 16
191#define MT7628_GPIO_MODE_WDT 14
192#define MT7628_GPIO_MODE_SPI 12
193#define MT7628_GPIO_MODE_SDMODE 10
194#define MT7628_GPIO_MODE_UART0 8
195#define MT7628_GPIO_MODE_I2S 6
196#define MT7628_GPIO_MODE_CS1 4
197#define MT7628_GPIO_MODE_SPIS 2
198#define MT7628_GPIO_MODE_GPIO 0
199
200static struct rt2880_pmx_group mt7628an_pinmux_data[] = {
201 GRP_G("pmw1", pwm1_grp_mt7628, MT7628_GPIO_MODE_MASK,
202 1, MT7628_GPIO_MODE_PWM1),
203 GRP_G("pmw1", pwm0_grp_mt7628, MT7628_GPIO_MODE_MASK,
204 1, MT7628_GPIO_MODE_PWM0),
205 GRP_G("uart2", uart2_grp_mt7628, MT7628_GPIO_MODE_MASK,
206 1, MT7628_GPIO_MODE_UART2),
207 GRP_G("uart1", uart1_grp_mt7628, MT7628_GPIO_MODE_MASK,
208 1, MT7628_GPIO_MODE_UART1),
209 GRP_G("i2c", i2c_grp_mt7628, MT7628_GPIO_MODE_MASK,
210 1, MT7628_GPIO_MODE_I2C),
211 GRP("refclk", refclk_grp_mt7628, 1, MT7628_GPIO_MODE_REFCLK),
212 GRP("perst", perst_grp_mt7628, 1, MT7628_GPIO_MODE_PERST),
213 GRP("wdt", wdt_grp_mt7628, 1, MT7628_GPIO_MODE_WDT),
214 GRP("spi", spi_grp_mt7628, 1, MT7628_GPIO_MODE_SPI),
215 GRP_G("sdmode", sd_mode_grp_mt7628, MT7628_GPIO_MODE_MASK,
216 1, MT7628_GPIO_MODE_SDMODE),
217 GRP_G("uart0", uart0_grp_mt7628, MT7628_GPIO_MODE_MASK,
218 1, MT7628_GPIO_MODE_UART0),
219 GRP_G("i2s", i2s_grp_mt7628, MT7628_GPIO_MODE_MASK,
220 1, MT7628_GPIO_MODE_I2S),
221 GRP_G("spi cs1", spi_cs1_grp_mt7628, MT7628_GPIO_MODE_MASK,
222 1, MT7628_GPIO_MODE_CS1),
223 GRP_G("spis", spis_grp_mt7628, MT7628_GPIO_MODE_MASK,
224 1, MT7628_GPIO_MODE_SPIS),
225 GRP_G("gpio", gpio_grp_mt7628, MT7628_GPIO_MODE_MASK,
226 1, MT7628_GPIO_MODE_GPIO),
227 { 0 }
228};
229
230static __init u32
231mt7620_calc_rate(u32 ref_rate, u32 mul, u32 div)
232{
233 u64 t;
234
235 t = ref_rate;
236 t *= mul;
237 do_div(t, div);
238
239 return t;
240}
241
242#define MHZ(x) ((x) * 1000 * 1000)
243
244static __init unsigned long
245mt7620_get_xtal_rate(void)
246{
247 u32 reg;
248
249 reg = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG0);
250 if (reg & SYSCFG0_XTAL_FREQ_SEL)
251 return MHZ(40);
252
253 return MHZ(20);
254}
255
256static __init unsigned long
257mt7620_get_periph_rate(unsigned long xtal_rate)
258{
259 u32 reg;
260
261 reg = rt_sysc_r32(SYSC_REG_CLKCFG0);
262 if (reg & CLKCFG0_PERI_CLK_SEL)
263 return xtal_rate;
264
265 return MHZ(40);
266}
267
268static const u32 mt7620_clk_divider[] __initconst = { 2, 3, 4, 8 };
269
270static __init unsigned long
271mt7620_get_cpu_pll_rate(unsigned long xtal_rate)
272{
273 u32 reg;
274 u32 mul;
275 u32 div;
276
277 reg = rt_sysc_r32(SYSC_REG_CPLL_CONFIG0);
278 if (reg & CPLL_CFG0_BYPASS_REF_CLK)
279 return xtal_rate;
280
281 if ((reg & CPLL_CFG0_SW_CFG) == 0)
282 return MHZ(600);
283
284 mul = (reg >> CPLL_CFG0_PLL_MULT_RATIO_SHIFT) &
285 CPLL_CFG0_PLL_MULT_RATIO_MASK;
286 mul += 24;
287 if (reg & CPLL_CFG0_LC_CURFCK)
288 mul *= 2;
289
290 div = (reg >> CPLL_CFG0_PLL_DIV_RATIO_SHIFT) &
291 CPLL_CFG0_PLL_DIV_RATIO_MASK;
292
293 WARN_ON(div >= ARRAY_SIZE(mt7620_clk_divider));
294
295 return mt7620_calc_rate(xtal_rate, mul, mt7620_clk_divider[div]);
296}
297
298static __init unsigned long
299mt7620_get_pll_rate(unsigned long xtal_rate, unsigned long cpu_pll_rate)
300{
301 u32 reg;
302
303 reg = rt_sysc_r32(SYSC_REG_CPLL_CONFIG1);
304 if (reg & CPLL_CFG1_CPU_AUX1)
305 return xtal_rate;
306
307 if (reg & CPLL_CFG1_CPU_AUX0)
308 return MHZ(480);
309
310 return cpu_pll_rate;
311}
312
313static __init unsigned long
314mt7620_get_cpu_rate(unsigned long pll_rate)
315{
316 u32 reg;
317 u32 mul;
318 u32 div;
319
320 reg = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG);
321
322 mul = reg & CPU_SYS_CLKCFG_CPU_FFRAC_MASK;
323 div = (reg >> CPU_SYS_CLKCFG_CPU_FDIV_SHIFT) &
324 CPU_SYS_CLKCFG_CPU_FDIV_MASK;
325
326 return mt7620_calc_rate(pll_rate, mul, div);
327}
328
329static const u32 mt7620_ocp_dividers[16] __initconst = {
330 [CPU_SYS_CLKCFG_OCP_RATIO_2] = 2,
331 [CPU_SYS_CLKCFG_OCP_RATIO_3] = 3,
332 [CPU_SYS_CLKCFG_OCP_RATIO_4] = 4,
333 [CPU_SYS_CLKCFG_OCP_RATIO_5] = 5,
334 [CPU_SYS_CLKCFG_OCP_RATIO_10] = 10,
335};
336
337static __init unsigned long
338mt7620_get_dram_rate(unsigned long pll_rate)
339{
340 if (dram_type == SYSCFG0_DRAM_TYPE_SDRAM)
341 return pll_rate / 4;
342
343 return pll_rate / 3;
344}
345
346static __init unsigned long
347mt7620_get_sys_rate(unsigned long cpu_rate)
348{
349 u32 reg;
350 u32 ocp_ratio;
351 u32 div;
352
353 reg = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG);
354
355 ocp_ratio = (reg >> CPU_SYS_CLKCFG_OCP_RATIO_SHIFT) &
356 CPU_SYS_CLKCFG_OCP_RATIO_MASK;
357
358 if (WARN_ON(ocp_ratio >= ARRAY_SIZE(mt7620_ocp_dividers)))
359 return cpu_rate;
360
361 div = mt7620_ocp_dividers[ocp_ratio];
362 if (WARN(!div, "invalid divider for OCP ratio %u", ocp_ratio))
363 return cpu_rate;
364
365 return cpu_rate / div;
366}
367
368void __init ralink_clk_init(void)
369{
370 unsigned long xtal_rate;
371 unsigned long cpu_pll_rate;
372 unsigned long pll_rate;
373 unsigned long cpu_rate;
374 unsigned long sys_rate;
375 unsigned long dram_rate;
376 unsigned long periph_rate;
377
378 xtal_rate = mt7620_get_xtal_rate();
379
380#define RFMT(label) label ":%lu.%03luMHz "
381#define RINT(x) ((x) / 1000000)
382#define RFRAC(x) (((x) / 1000) % 1000)
383
384 if (mt762x_soc == MT762X_SOC_MT7628AN) {
385 if (xtal_rate == MHZ(40))
386 cpu_rate = MHZ(580);
387 else
388 cpu_rate = MHZ(575);
389 dram_rate = sys_rate = cpu_rate / 3;
390 periph_rate = MHZ(40);
391
392 ralink_clk_add("10000d00.uartlite", periph_rate);
393 ralink_clk_add("10000e00.uartlite", periph_rate);
394 } else {
395 cpu_pll_rate = mt7620_get_cpu_pll_rate(xtal_rate);
396 pll_rate = mt7620_get_pll_rate(xtal_rate, cpu_pll_rate);
397
398 cpu_rate = mt7620_get_cpu_rate(pll_rate);
399 dram_rate = mt7620_get_dram_rate(pll_rate);
400 sys_rate = mt7620_get_sys_rate(cpu_rate);
401 periph_rate = mt7620_get_periph_rate(xtal_rate);
402
403 pr_debug(RFMT("XTAL") RFMT("CPU_PLL") RFMT("PLL"),
404 RINT(xtal_rate), RFRAC(xtal_rate),
405 RINT(cpu_pll_rate), RFRAC(cpu_pll_rate),
406 RINT(pll_rate), RFRAC(pll_rate));
407
408 ralink_clk_add("10000500.uart", periph_rate);
409 }
410
411 pr_debug(RFMT("CPU") RFMT("DRAM") RFMT("SYS") RFMT("PERIPH"),
412 RINT(cpu_rate), RFRAC(cpu_rate),
413 RINT(dram_rate), RFRAC(dram_rate),
414 RINT(sys_rate), RFRAC(sys_rate),
415 RINT(periph_rate), RFRAC(periph_rate));
416#undef RFRAC
417#undef RINT
418#undef RFMT
419
420 ralink_clk_add("cpu", cpu_rate);
421 ralink_clk_add("10000100.timer", periph_rate);
422 ralink_clk_add("10000120.watchdog", periph_rate);
423 ralink_clk_add("10000b00.spi", sys_rate);
424 ralink_clk_add("10000c00.uartlite", periph_rate);
425 ralink_clk_add("10180000.wmac", xtal_rate);
426}
427
428void __init ralink_of_remap(void)
429{
430 rt_sysc_membase = plat_of_remap_node("ralink,mt7620a-sysc");
431 rt_memc_membase = plat_of_remap_node("ralink,mt7620a-memc");
432
433 if (!rt_sysc_membase || !rt_memc_membase)
434 panic("Failed to remap core resources");
435}
436
437static __init void
438mt7620_dram_init(struct ralink_soc_info *soc_info)
439{
440 switch (dram_type) {
441 case SYSCFG0_DRAM_TYPE_SDRAM:
442 pr_info("Board has SDRAM\n");
443 soc_info->mem_size_min = MT7620_SDRAM_SIZE_MIN;
444 soc_info->mem_size_max = MT7620_SDRAM_SIZE_MAX;
445 break;
446
447 case SYSCFG0_DRAM_TYPE_DDR1:
448 pr_info("Board has DDR1\n");
449 soc_info->mem_size_min = MT7620_DDR1_SIZE_MIN;
450 soc_info->mem_size_max = MT7620_DDR1_SIZE_MAX;
451 break;
452
453 case SYSCFG0_DRAM_TYPE_DDR2:
454 pr_info("Board has DDR2\n");
455 soc_info->mem_size_min = MT7620_DDR2_SIZE_MIN;
456 soc_info->mem_size_max = MT7620_DDR2_SIZE_MAX;
457 break;
458 default:
459 BUG();
460 }
461}
462
463static __init void
464mt7628_dram_init(struct ralink_soc_info *soc_info)
465{
466 switch (dram_type) {
467 case SYSCFG0_DRAM_TYPE_DDR1_MT7628:
468 pr_info("Board has DDR1\n");
469 soc_info->mem_size_min = MT7620_DDR1_SIZE_MIN;
470 soc_info->mem_size_max = MT7620_DDR1_SIZE_MAX;
471 break;
472
473 case SYSCFG0_DRAM_TYPE_DDR2_MT7628:
474 pr_info("Board has DDR2\n");
475 soc_info->mem_size_min = MT7620_DDR2_SIZE_MIN;
476 soc_info->mem_size_max = MT7620_DDR2_SIZE_MAX;
477 break;
478 default:
479 BUG();
480 }
481}
482
483void prom_soc_init(struct ralink_soc_info *soc_info)
484{
485 void __iomem *sysc = (void __iomem *) KSEG1ADDR(MT7620_SYSC_BASE);
486 unsigned char *name = NULL;
487 u32 n0;
488 u32 n1;
489 u32 rev;
490 u32 cfg0;
491 u32 pmu0;
492 u32 pmu1;
493 u32 bga;
494
495 n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
496 n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
497 rev = __raw_readl(sysc + SYSC_REG_CHIP_REV);
498 bga = (rev >> CHIP_REV_PKG_SHIFT) & CHIP_REV_PKG_MASK;
499
500 if (n0 == MT7620_CHIP_NAME0 && n1 == MT7620_CHIP_NAME1) {
501 if (bga) {
502 mt762x_soc = MT762X_SOC_MT7620A;
503 name = "MT7620A";
504 soc_info->compatible = "ralink,mt7620a-soc";
505 } else {
506 mt762x_soc = MT762X_SOC_MT7620N;
507 name = "MT7620N";
508 soc_info->compatible = "ralink,mt7620n-soc";
509#ifdef CONFIG_PCI
510 panic("mt7620n is only supported for non pci kernels");
511#endif
512 }
513 } else if (n0 == MT7620_CHIP_NAME0 && n1 == MT7628_CHIP_NAME1) {
514 mt762x_soc = MT762X_SOC_MT7628AN;
515 name = "MT7628AN";
516 soc_info->compatible = "ralink,mt7628an-soc";
517 } else {
518 panic("mt762x: unknown SoC, n0:%08x n1:%08x\n", n0, n1);
519 }
520
521 snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
522 "Ralink %s ver:%u eco:%u",
523 name,
524 (rev >> CHIP_REV_VER_SHIFT) & CHIP_REV_VER_MASK,
525 (rev & CHIP_REV_ECO_MASK));
526
527 cfg0 = __raw_readl(sysc + SYSC_REG_SYSTEM_CONFIG0);
528 dram_type = (cfg0 >> SYSCFG0_DRAM_TYPE_SHIFT) & SYSCFG0_DRAM_TYPE_MASK;
529
530 soc_info->mem_base = MT7620_DRAM_BASE;
531 if (mt762x_soc == MT762X_SOC_MT7628AN)
532 mt7628_dram_init(soc_info);
533 else
534 mt7620_dram_init(soc_info);
535
536 pmu0 = __raw_readl(sysc + PMU0_CFG);
537 pmu1 = __raw_readl(sysc + PMU1_CFG);
538
539 pr_info("Analog PMU set to %s control\n",
540 (pmu0 & PMU_SW_SET) ? ("sw") : ("hw"));
541 pr_info("Digital PMU set to %s control\n",
542 (pmu1 & DIG_SW_SEL) ? ("sw") : ("hw"));
543
544 if (mt762x_soc == MT762X_SOC_MT7628AN)
545 rt2880_pinmux_data = mt7628an_pinmux_data;
546 else
547 rt2880_pinmux_data = mt7620a_pinmux_data;
548}
549
