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17#include <linux/errno.h>
18#include <linux/module.h>
19#include <linux/sched.h>
20#include <linux/kernel.h>
21#include <linux/param.h>
22#include <linux/string.h>
23#include <linux/mm.h>
24#include <linux/interrupt.h>
25#include <linux/time.h>
26#include <linux/rtc.h>
27#include <linux/rtc/m48t59.h>
28#include <linux/timex.h>
29#include <linux/clocksource.h>
30#include <linux/clockchips.h>
31#include <linux/init.h>
32#include <linux/pci.h>
33#include <linux/ioport.h>
34#include <linux/profile.h>
35#include <linux/of.h>
36#include <linux/of_device.h>
37#include <linux/platform_device.h>
38
39#include <asm/mc146818rtc.h>
40#include <asm/oplib.h>
41#include <asm/timex.h>
42#include <asm/timer.h>
43#include <asm/irq.h>
44#include <asm/io.h>
45#include <asm/idprom.h>
46#include <asm/page.h>
47#include <asm/pcic.h>
48#include <asm/irq_regs.h>
49#include <asm/setup.h>
50
51#include "kernel.h"
52#include "irq.h"
53
54static __cacheline_aligned_in_smp DEFINE_SEQLOCK(timer_cs_lock);
55static __volatile__ u64 timer_cs_internal_counter = 0;
56static char timer_cs_enabled = 0;
57
58static struct clock_event_device timer_ce;
59static char timer_ce_enabled = 0;
60
61#ifdef CONFIG_SMP
62DEFINE_PER_CPU(struct clock_event_device, sparc32_clockevent);
63#endif
64
65DEFINE_SPINLOCK(rtc_lock);
66EXPORT_SYMBOL(rtc_lock);
67
68static int set_rtc_mmss(unsigned long);
69
70unsigned long profile_pc(struct pt_regs *regs)
71{
72 extern char __copy_user_begin[], __copy_user_end[];
73 extern char __bzero_begin[], __bzero_end[];
74
75 unsigned long pc = regs->pc;
76
77 if (in_lock_functions(pc) ||
78 (pc >= (unsigned long) __copy_user_begin &&
79 pc < (unsigned long) __copy_user_end) ||
80 (pc >= (unsigned long) __bzero_begin &&
81 pc < (unsigned long) __bzero_end))
82 pc = regs->u_regs[UREG_RETPC];
83 return pc;
84}
85
86EXPORT_SYMBOL(profile_pc);
87
88volatile u32 __iomem *master_l10_counter;
89
90int update_persistent_clock(struct timespec now)
91{
92 return set_rtc_mmss(now.tv_sec);
93}
94
95irqreturn_t notrace timer_interrupt(int dummy, void *dev_id)
96{
97 if (timer_cs_enabled) {
98 write_seqlock(&timer_cs_lock);
99 timer_cs_internal_counter++;
100 sparc_config.clear_clock_irq();
101 write_sequnlock(&timer_cs_lock);
102 } else {
103 sparc_config.clear_clock_irq();
104 }
105
106 if (timer_ce_enabled)
107 timer_ce.event_handler(&timer_ce);
108
109 return IRQ_HANDLED;
110}
111
112static void timer_ce_set_mode(enum clock_event_mode mode,
113 struct clock_event_device *evt)
114{
115 switch (mode) {
116 case CLOCK_EVT_MODE_PERIODIC:
117 case CLOCK_EVT_MODE_RESUME:
118 timer_ce_enabled = 1;
119 break;
120 case CLOCK_EVT_MODE_SHUTDOWN:
121 timer_ce_enabled = 0;
122 break;
123 default:
124 break;
125 }
126 smp_mb();
127}
128
129static __init void setup_timer_ce(void)
130{
131 struct clock_event_device *ce = &timer_ce;
132
133 BUG_ON(smp_processor_id() != boot_cpu_id);
134
135 ce->name = "timer_ce";
136 ce->rating = 100;
137 ce->features = CLOCK_EVT_FEAT_PERIODIC;
138 ce->set_mode = timer_ce_set_mode;
139 ce->cpumask = cpu_possible_mask;
140 ce->shift = 32;
141 ce->mult = div_sc(sparc_config.clock_rate, NSEC_PER_SEC,
142 ce->shift);
143 clockevents_register_device(ce);
144}
145
146static unsigned int sbus_cycles_offset(void)
147{
148 u32 val, offset;
149
150 val = sbus_readl(master_l10_counter);
151 offset = (val >> TIMER_VALUE_SHIFT) & TIMER_VALUE_MASK;
152
153
154 if (val & TIMER_LIMIT_BIT)
155 offset += sparc_config.cs_period;
156
157 return offset;
158}
159
160static cycle_t timer_cs_read(struct clocksource *cs)
161{
162 unsigned int seq, offset;
163 u64 cycles;
164
165 do {
166 seq = read_seqbegin(&timer_cs_lock);
167
168 cycles = timer_cs_internal_counter;
169 offset = sparc_config.get_cycles_offset();
170 } while (read_seqretry(&timer_cs_lock, seq));
171
172
173 cycles *= sparc_config.cs_period;
174 cycles += offset;
175
176 return cycles;
177}
178
179static struct clocksource timer_cs = {
180 .name = "timer_cs",
181 .rating = 100,
182 .read = timer_cs_read,
183 .mask = CLOCKSOURCE_MASK(64),
184 .shift = 2,
185 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
186};
187
188static __init int setup_timer_cs(void)
189{
190 timer_cs_enabled = 1;
191 timer_cs.mult = clocksource_hz2mult(sparc_config.clock_rate,
192 timer_cs.shift);
193
194 return clocksource_register(&timer_cs);
195}
196
197#ifdef CONFIG_SMP
198static void percpu_ce_setup(enum clock_event_mode mode,
199 struct clock_event_device *evt)
200{
201 int cpu = __first_cpu(evt->cpumask);
202
203 switch (mode) {
204 case CLOCK_EVT_MODE_PERIODIC:
205 sparc_config.load_profile_irq(cpu,
206 SBUS_CLOCK_RATE / HZ);
207 break;
208 case CLOCK_EVT_MODE_ONESHOT:
209 case CLOCK_EVT_MODE_SHUTDOWN:
210 case CLOCK_EVT_MODE_UNUSED:
211 sparc_config.load_profile_irq(cpu, 0);
212 break;
213 default:
214 break;
215 }
216}
217
218static int percpu_ce_set_next_event(unsigned long delta,
219 struct clock_event_device *evt)
220{
221 int cpu = __first_cpu(evt->cpumask);
222 unsigned int next = (unsigned int)delta;
223
224 sparc_config.load_profile_irq(cpu, next);
225 return 0;
226}
227
228void register_percpu_ce(int cpu)
229{
230 struct clock_event_device *ce = &per_cpu(sparc32_clockevent, cpu);
231 unsigned int features = CLOCK_EVT_FEAT_PERIODIC;
232
233 if (sparc_config.features & FEAT_L14_ONESHOT)
234 features |= CLOCK_EVT_FEAT_ONESHOT;
235
236 ce->name = "percpu_ce";
237 ce->rating = 200;
238 ce->features = features;
239 ce->set_mode = percpu_ce_setup;
240 ce->set_next_event = percpu_ce_set_next_event;
241 ce->cpumask = cpumask_of(cpu);
242 ce->shift = 32;
243 ce->mult = div_sc(sparc_config.clock_rate, NSEC_PER_SEC,
244 ce->shift);
245 ce->max_delta_ns = clockevent_delta2ns(sparc_config.clock_rate, ce);
246 ce->min_delta_ns = clockevent_delta2ns(100, ce);
247
248 clockevents_register_device(ce);
249}
250#endif
251
252static unsigned char mostek_read_byte(struct device *dev, u32 ofs)
253{
254 struct platform_device *pdev = to_platform_device(dev);
255 struct m48t59_plat_data *pdata = pdev->dev.platform_data;
256
257 return readb(pdata->ioaddr + ofs);
258}
259
260static void mostek_write_byte(struct device *dev, u32 ofs, u8 val)
261{
262 struct platform_device *pdev = to_platform_device(dev);
263 struct m48t59_plat_data *pdata = pdev->dev.platform_data;
264
265 writeb(val, pdata->ioaddr + ofs);
266}
267
268static struct m48t59_plat_data m48t59_data = {
269 .read_byte = mostek_read_byte,
270 .write_byte = mostek_write_byte,
271};
272
273
274static struct platform_device m48t59_rtc = {
275 .name = "rtc-m48t59",
276 .id = 0,
277 .num_resources = 1,
278 .dev = {
279 .platform_data = &m48t59_data,
280 },
281};
282
283static int clock_probe(struct platform_device *op)
284{
285 struct device_node *dp = op->dev.of_node;
286 const char *model = of_get_property(dp, "model", NULL);
287
288 if (!model)
289 return -ENODEV;
290
291
292 if (!of_find_property(dp, "address", NULL))
293 return -ENODEV;
294
295 m48t59_rtc.resource = &op->resource[0];
296 if (!strcmp(model, "mk48t02")) {
297
298 m48t59_data.ioaddr = of_ioremap(&op->resource[0], 0,
299 2048, "rtc-m48t59");
300 m48t59_data.type = M48T59RTC_TYPE_M48T02;
301 } else if (!strcmp(model, "mk48t08")) {
302 m48t59_data.ioaddr = of_ioremap(&op->resource[0], 0,
303 8192, "rtc-m48t59");
304 m48t59_data.type = M48T59RTC_TYPE_M48T08;
305 } else
306 return -ENODEV;
307
308 if (platform_device_register(&m48t59_rtc) < 0)
309 printk(KERN_ERR "Registering RTC device failed\n");
310
311 return 0;
312}
313
314static struct of_device_id clock_match[] = {
315 {
316 .name = "eeprom",
317 },
318 {},
319};
320
321static struct platform_driver clock_driver = {
322 .probe = clock_probe,
323 .driver = {
324 .name = "rtc",
325 .of_match_table = clock_match,
326 },
327};
328
329
330
331static int __init clock_init(void)
332{
333 return platform_driver_register(&clock_driver);
334}
335
336
337
338
339fs_initcall(clock_init);
340
341static void __init sparc32_late_time_init(void)
342{
343 if (sparc_config.features & FEAT_L10_CLOCKEVENT)
344 setup_timer_ce();
345 if (sparc_config.features & FEAT_L10_CLOCKSOURCE)
346 setup_timer_cs();
347#ifdef CONFIG_SMP
348 register_percpu_ce(smp_processor_id());
349#endif
350}
351
352static void __init sbus_time_init(void)
353{
354 sparc_config.get_cycles_offset = sbus_cycles_offset;
355 sparc_config.init_timers();
356}
357
358void __init time_init(void)
359{
360 sparc_config.features = 0;
361 late_time_init = sparc32_late_time_init;
362
363 if (pcic_present())
364 pci_time_init();
365 else
366 sbus_time_init();
367}
368
369
370static int set_rtc_mmss(unsigned long secs)
371{
372 struct rtc_device *rtc = rtc_class_open("rtc0");
373 int err = -1;
374
375 if (rtc) {
376 err = rtc_set_mmss(rtc, secs);
377 rtc_class_close(rtc);
378 }
379
380 return err;
381}
382
