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11#ifndef _XTENSA_TLB_H
12#define _XTENSA_TLB_H
13
14#include <asm/cache.h>
15#include <asm/page.h>
16
17#if (DCACHE_WAY_SIZE <= PAGE_SIZE)
18
19
20
21# define tlb_start_vma(tlb,vma) do { } while (0)
22# define tlb_end_vma(tlb,vma) do { } while (0)
23
24#else
25
26# define tlb_start_vma(tlb, vma) \
27 do { \
28 if (!tlb->fullmm) \
29 flush_cache_range(vma, vma->vm_start, vma->vm_end); \
30 } while(0)
31
32# define tlb_end_vma(tlb, vma) \
33 do { \
34 if (!tlb->fullmm) \
35 flush_tlb_range(vma, vma->vm_start, vma->vm_end); \
36 } while(0)
37
38#endif
39
40#define __tlb_remove_tlb_entry(tlb,pte,addr) do { } while (0)
41#define tlb_flush(tlb) flush_tlb_mm((tlb)->mm)
42
43#include <asm-generic/tlb.h>
44
45#define __pte_free_tlb(tlb, pte, address) pte_free((tlb)->mm, pte)
46
47#endif
48