1#ifndef _FORE200E_H
2#define _FORE200E_H
3
4#ifdef __KERNEL__
5
6
7
8#define SMALL_BUFFER_SIZE 384
9#define LARGE_BUFFER_SIZE 4032
10
11
12#define RBD_BLK_SIZE 32
13
14
15#define MAX_PDU_SIZE 65535
16
17
18#define BUFFER_S1_SIZE SMALL_BUFFER_SIZE
19#define BUFFER_L1_SIZE LARGE_BUFFER_SIZE
20
21#define BUFFER_S2_SIZE SMALL_BUFFER_SIZE
22#define BUFFER_L2_SIZE LARGE_BUFFER_SIZE
23
24#define BUFFER_S1_NBR (RBD_BLK_SIZE * 6)
25#define BUFFER_L1_NBR (RBD_BLK_SIZE * 4)
26
27#define BUFFER_S2_NBR (RBD_BLK_SIZE * 6)
28#define BUFFER_L2_NBR (RBD_BLK_SIZE * 4)
29
30
31#define QUEUE_SIZE_CMD 16
32#define QUEUE_SIZE_RX 64
33#define QUEUE_SIZE_TX 256
34#define QUEUE_SIZE_BS 32
35
36#define FORE200E_VPI_BITS 0
37#define FORE200E_VCI_BITS 10
38#define NBR_CONNECT (1 << (FORE200E_VPI_BITS + FORE200E_VCI_BITS))
39
40
41#define TSD_FIXED 2
42#define TSD_EXTENSION 0
43#define TSD_NBR (TSD_FIXED + TSD_EXTENSION)
44
45
46
47
48
49
50
51#define RSD_REQUIRED (((MAX_PDU_SIZE - SMALL_BUFFER_SIZE + LARGE_BUFFER_SIZE) / LARGE_BUFFER_SIZE) + 1)
52
53#define RSD_FIXED 3
54
55
56
57
58
59
60#define RSD_EXTENSION ((RSD_REQUIRED - RSD_FIXED) + 1)
61#define RSD_NBR (RSD_FIXED + RSD_EXTENSION)
62
63
64#define FORE200E_DEV(d) ((struct fore200e*)((d)->dev_data))
65#define FORE200E_VCC(d) ((struct fore200e_vcc*)((d)->dev_data))
66
67
68
69#if defined(__LITTLE_ENDIAN_BITFIELD)
70#define BITFIELD2(b1, b2) b1; b2;
71#define BITFIELD3(b1, b2, b3) b1; b2; b3;
72#define BITFIELD4(b1, b2, b3, b4) b1; b2; b3; b4;
73#define BITFIELD5(b1, b2, b3, b4, b5) b1; b2; b3; b4; b5;
74#define BITFIELD6(b1, b2, b3, b4, b5, b6) b1; b2; b3; b4; b5; b6;
75#elif defined(__BIG_ENDIAN_BITFIELD)
76#define BITFIELD2(b1, b2) b2; b1;
77#define BITFIELD3(b1, b2, b3) b3; b2; b1;
78#define BITFIELD4(b1, b2, b3, b4) b4; b3; b2; b1;
79#define BITFIELD5(b1, b2, b3, b4, b5) b5; b4; b3; b2; b1;
80#define BITFIELD6(b1, b2, b3, b4, b5, b6) b6; b5; b4; b3; b2; b1;
81#else
82#error unknown bitfield endianess
83#endif
84
85
86
87
88typedef struct atm_header {
89 BITFIELD5(
90 u32 clp : 1,
91 u32 plt : 3,
92 u32 vci : 16,
93 u32 vpi : 8,
94 u32 gfc : 4
95 )
96} atm_header_t;
97
98
99
100
101typedef enum fore200e_aal {
102 FORE200E_AAL0 = 0,
103 FORE200E_AAL34 = 4,
104 FORE200E_AAL5 = 5,
105} fore200e_aal_t;
106
107
108
109
110typedef struct tpd_spec {
111 BITFIELD4(
112 u32 length : 16,
113 u32 nseg : 8,
114 enum fore200e_aal aal : 4,
115 u32 intr : 4
116 )
117} tpd_spec_t;
118
119
120
121
122typedef struct tpd_rate
123{
124 BITFIELD2(
125 u32 idle_cells : 16,
126 u32 data_cells : 16
127 )
128} tpd_rate_t;
129
130
131
132
133typedef struct tsd {
134 u32 buffer;
135 u32 length;
136} tsd_t;
137
138
139
140
141typedef struct tpd {
142 struct atm_header atm_header;
143 struct tpd_spec spec;
144 struct tpd_rate rate;
145 u32 pad;
146 struct tsd tsd[ TSD_NBR ];
147} tpd_t;
148
149
150
151
152typedef struct rsd {
153 u32 handle;
154 u32 length;
155} rsd_t;
156
157
158
159
160typedef struct rpd {
161 struct atm_header atm_header;
162 u32 nseg;
163 struct rsd rsd[ RSD_NBR ];
164} rpd_t;
165
166
167
168
169typedef enum buffer_scheme {
170 BUFFER_SCHEME_ONE,
171 BUFFER_SCHEME_TWO,
172 BUFFER_SCHEME_NBR
173} buffer_scheme_t;
174
175
176
177
178typedef enum buffer_magn {
179 BUFFER_MAGN_SMALL,
180 BUFFER_MAGN_LARGE,
181 BUFFER_MAGN_NBR
182} buffer_magn_t;
183
184
185
186
187typedef struct rbd {
188 u32 handle;
189 u32 buffer_haddr;
190} rbd_t;
191
192
193
194
195typedef struct rbd_block {
196 struct rbd rbd[ RBD_BLK_SIZE ];
197} rbd_block_t;
198
199
200
201
202typedef struct tpd_haddr {
203 BITFIELD3(
204 u32 size : 4,
205 u32 pad : 1,
206 u32 haddr : 27
207 )
208} tpd_haddr_t;
209
210#define TPD_HADDR_SHIFT 5
211
212
213
214typedef struct cp_txq_entry {
215 struct tpd_haddr tpd_haddr;
216 u32 status_haddr;
217} cp_txq_entry_t;
218
219
220
221
222typedef struct cp_rxq_entry {
223 u32 rpd_haddr;
224 u32 status_haddr;
225} cp_rxq_entry_t;
226
227
228
229
230typedef struct cp_bsq_entry {
231 u32 rbd_block_haddr;
232 u32 status_haddr;
233} cp_bsq_entry_t;
234
235
236
237
238typedef volatile enum status {
239 STATUS_PENDING = (1<<0),
240 STATUS_COMPLETE = (1<<1),
241 STATUS_FREE = (1<<2),
242 STATUS_ERROR = (1<<3)
243} status_t;
244
245
246
247
248typedef enum opcode {
249 OPCODE_INITIALIZE = 1,
250 OPCODE_ACTIVATE_VCIN,
251 OPCODE_ACTIVATE_VCOUT,
252 OPCODE_DEACTIVATE_VCIN,
253 OPCODE_DEACTIVATE_VCOUT,
254 OPCODE_GET_STATS,
255 OPCODE_SET_OC3,
256 OPCODE_GET_OC3,
257 OPCODE_RESET_STATS,
258 OPCODE_GET_PROM,
259 OPCODE_SET_VPI_BITS,
260
261
262 OPCODE_REQUEST_INTR = (1<<7)
263} opcode_t;
264
265
266
267
268typedef struct vpvc {
269 BITFIELD3(
270 u32 vci : 16,
271 u32 vpi : 8,
272 u32 pad : 8
273 )
274} vpvc_t;
275
276
277
278
279typedef struct activate_opcode {
280 BITFIELD4(
281 enum opcode opcode : 8,
282 enum fore200e_aal aal : 8,
283 enum buffer_scheme scheme : 8,
284 u32 pad : 8
285 )
286} activate_opcode_t;
287
288
289
290
291typedef struct activate_block {
292 struct activate_opcode opcode;
293 struct vpvc vpvc;
294 u32 mtu;
295
296} activate_block_t;
297
298
299
300
301typedef struct deactivate_opcode {
302 BITFIELD2(
303 enum opcode opcode : 8,
304 u32 pad : 24
305 )
306} deactivate_opcode_t;
307
308
309
310
311typedef struct deactivate_block {
312 struct deactivate_opcode opcode;
313 struct vpvc vpvc;
314} deactivate_block_t;
315
316
317
318
319typedef struct oc3_regs {
320 u32 reg[ 128 ];
321
322
323} oc3_regs_t;
324
325
326
327
328typedef struct oc3_opcode {
329 BITFIELD4(
330 enum opcode opcode : 8,
331 u32 reg : 8,
332 u32 value : 8,
333 u32 mask : 8
334
335
336 )
337} oc3_opcode_t;
338
339
340
341
342typedef struct oc3_block {
343 struct oc3_opcode opcode;
344 u32 regs_haddr;
345} oc3_block_t;
346
347
348
349
350typedef struct stats_phy {
351 __be32 crc_header_errors;
352 __be32 framing_errors;
353 __be32 pad[ 2 ];
354} stats_phy_t;
355
356
357
358
359typedef struct stats_oc3 {
360 __be32 section_bip8_errors;
361 __be32 path_bip8_errors;
362 __be32 line_bip24_errors;
363 __be32 line_febe_errors;
364 __be32 path_febe_errors;
365 __be32 corr_hcs_errors;
366 __be32 ucorr_hcs_errors;
367 __be32 pad[ 1 ];
368} stats_oc3_t;
369
370
371
372
373typedef struct stats_atm {
374 __be32 cells_transmitted;
375 __be32 cells_received;
376 __be32 vpi_bad_range;
377 __be32 vpi_no_conn;
378 __be32 vci_bad_range;
379 __be32 vci_no_conn;
380 __be32 pad[ 2 ];
381} stats_atm_t;
382
383
384
385typedef struct stats_aal0 {
386 __be32 cells_transmitted;
387 __be32 cells_received;
388 __be32 cells_dropped;
389 __be32 pad[ 1 ];
390} stats_aal0_t;
391
392
393
394
395typedef struct stats_aal34 {
396 __be32 cells_transmitted;
397 __be32 cells_received;
398 __be32 cells_crc_errors;
399 __be32 cells_protocol_errors;
400 __be32 cells_dropped;
401 __be32 cspdus_transmitted;
402 __be32 cspdus_received;
403 __be32 cspdus_protocol_errors;
404 __be32 cspdus_dropped;
405 __be32 pad[ 3 ];
406} stats_aal34_t;
407
408
409
410
411typedef struct stats_aal5 {
412 __be32 cells_transmitted;
413 __be32 cells_received;
414 __be32 cells_dropped;
415 __be32 congestion_experienced;
416 __be32 cspdus_transmitted;
417 __be32 cspdus_received;
418 __be32 cspdus_crc_errors;
419 __be32 cspdus_protocol_errors;
420 __be32 cspdus_dropped;
421 __be32 pad[ 3 ];
422} stats_aal5_t;
423
424
425
426
427typedef struct stats_aux {
428 __be32 small_b1_failed;
429 __be32 large_b1_failed;
430 __be32 small_b2_failed;
431 __be32 large_b2_failed;
432 __be32 rpd_alloc_failed;
433 __be32 receive_carrier;
434 __be32 pad[ 2 ];
435} stats_aux_t;
436
437
438
439
440typedef struct stats {
441 struct stats_phy phy;
442 struct stats_oc3 oc3;
443 struct stats_atm atm;
444 struct stats_aal0 aal0;
445 struct stats_aal34 aal34;
446 struct stats_aal5 aal5;
447 struct stats_aux aux;
448} stats_t;
449
450
451
452
453typedef struct stats_opcode {
454 BITFIELD2(
455 enum opcode opcode : 8,
456 u32 pad : 24
457 )
458} stats_opcode_t;
459
460
461
462
463typedef struct stats_block {
464 struct stats_opcode opcode;
465 u32 stats_haddr;
466} stats_block_t;
467
468
469
470
471typedef struct prom_data {
472 u32 hw_revision;
473 u32 serial_number;
474 u8 mac_addr[ 8 ];
475} prom_data_t;
476
477
478
479
480typedef struct prom_opcode {
481 BITFIELD2(
482 enum opcode opcode : 8,
483 u32 pad : 24
484 )
485} prom_opcode_t;
486
487
488
489
490typedef struct prom_block {
491 struct prom_opcode opcode;
492 u32 prom_haddr;
493} prom_block_t;
494
495
496
497
498typedef union cmd {
499 enum opcode opcode;
500 struct activate_block activate_block;
501 struct deactivate_block deactivate_block;
502 struct stats_block stats_block;
503 struct prom_block prom_block;
504 struct oc3_block oc3_block;
505 u32 pad[ 4 ];
506} cmd_t;
507
508
509
510
511typedef struct cp_cmdq_entry {
512 union cmd cmd;
513 u32 status_haddr;
514 u32 pad[ 3 ];
515} cp_cmdq_entry_t;
516
517
518
519
520typedef struct host_txq_entry {
521 struct cp_txq_entry __iomem *cp_entry;
522 enum status* status;
523 struct tpd* tpd;
524 u32 tpd_dma;
525 struct sk_buff* skb;
526 void* data;
527 unsigned long incarn;
528 struct fore200e_vc_map* vc_map;
529
530} host_txq_entry_t;
531
532
533
534
535typedef struct host_rxq_entry {
536 struct cp_rxq_entry __iomem *cp_entry;
537 enum status* status;
538 struct rpd* rpd;
539 u32 rpd_dma;
540} host_rxq_entry_t;
541
542
543
544
545typedef struct host_bsq_entry {
546 struct cp_bsq_entry __iomem *cp_entry;
547 enum status* status;
548 struct rbd_block* rbd_block;
549 u32 rbd_block_dma;
550} host_bsq_entry_t;
551
552
553
554
555typedef struct host_cmdq_entry {
556 struct cp_cmdq_entry __iomem *cp_entry;
557 enum status *status;
558} host_cmdq_entry_t;
559
560
561
562
563typedef struct chunk {
564 void* alloc_addr;
565 void* align_addr;
566 dma_addr_t dma_addr;
567 int direction;
568 u32 alloc_size;
569 u32 align_size;
570} chunk_t;
571
572#define dma_size align_size
573
574
575
576
577typedef struct buffer {
578 struct buffer* next;
579 enum buffer_scheme scheme;
580 enum buffer_magn magn;
581 struct chunk data;
582#ifdef FORE200E_BSQ_DEBUG
583 unsigned long index;
584 int supplied;
585#endif
586} buffer_t;
587
588
589#if (BITS_PER_LONG == 32)
590#define FORE200E_BUF2HDL(buffer) ((u32)(buffer))
591#define FORE200E_HDL2BUF(handle) ((struct buffer*)(handle))
592#else
593#define FORE200E_BUF2HDL(buffer) ((u32)((u64)(buffer)))
594#define FORE200E_HDL2BUF(handle) ((struct buffer*)(((u64)(handle)) | PAGE_OFFSET))
595#endif
596
597
598
599
600typedef struct host_cmdq {
601 struct host_cmdq_entry host_entry[ QUEUE_SIZE_CMD ];
602 int head;
603 struct chunk status;
604} host_cmdq_t;
605
606
607
608
609typedef struct host_txq {
610 struct host_txq_entry host_entry[ QUEUE_SIZE_TX ];
611 int head;
612 int tail;
613 struct chunk tpd;
614 struct chunk status;
615 int txing;
616} host_txq_t;
617
618
619
620
621typedef struct host_rxq {
622 struct host_rxq_entry host_entry[ QUEUE_SIZE_RX ];
623 int head;
624 struct chunk rpd;
625 struct chunk status;
626} host_rxq_t;
627
628
629
630
631typedef struct host_bsq {
632 struct host_bsq_entry host_entry[ QUEUE_SIZE_BS ];
633 int head;
634 struct chunk rbd_block;
635 struct chunk status;
636 struct buffer* buffer;
637 struct buffer* freebuf;
638 volatile int freebuf_count;
639} host_bsq_t;
640
641
642
643
644typedef struct fw_header {
645 __le32 magic;
646 __le32 version;
647 __le32 load_offset;
648 __le32 start_offset;
649} fw_header_t;
650
651#define FW_HEADER_MAGIC 0x65726f66
652
653
654
655
656typedef struct bs_spec {
657 u32 queue_length;
658 u32 buffer_size;
659 u32 pool_size;
660 u32 supply_blksize;
661
662} bs_spec_t;
663
664
665
666
667typedef struct init_block {
668 enum opcode opcode;
669 enum status status;
670 u32 receive_threshold;
671 u32 num_connect;
672 u32 cmd_queue_len;
673 u32 tx_queue_len;
674 u32 rx_queue_len;
675 u32 rsd_extension;
676 u32 tsd_extension;
677 u32 conless_vpvc;
678 u32 pad[ 2 ];
679 struct bs_spec bs_spec[ BUFFER_SCHEME_NBR ][ BUFFER_MAGN_NBR ];
680} init_block_t;
681
682
683typedef enum media_type {
684 MEDIA_TYPE_CAT5_UTP = 0x06,
685 MEDIA_TYPE_MM_OC3_ST = 0x16,
686 MEDIA_TYPE_MM_OC3_SC = 0x26,
687 MEDIA_TYPE_SM_OC3_ST = 0x36,
688 MEDIA_TYPE_SM_OC3_SC = 0x46
689} media_type_t;
690
691#define FORE200E_MEDIA_INDEX(media_type) ((media_type)>>4)
692
693
694
695
696typedef struct cp_queues {
697 u32 cp_cmdq;
698 u32 cp_txq;
699 u32 cp_rxq;
700 u32 cp_bsq[ BUFFER_SCHEME_NBR ][ BUFFER_MAGN_NBR ];
701 u32 imask;
702 u32 istat;
703 u32 heap_base;
704 u32 heap_size;
705 u32 hlogger;
706 u32 heartbeat;
707 u32 fw_release;
708 u32 mon960_release;
709 u32 tq_plen;
710
711 struct init_block init;
712 enum media_type media_type;
713 u32 oc3_revision;
714} cp_queues_t;
715
716
717
718
719typedef enum boot_status {
720 BSTAT_COLD_START = (u32) 0xc01dc01d,
721 BSTAT_SELFTEST_OK = (u32) 0x02201958,
722 BSTAT_SELFTEST_FAIL = (u32) 0xadbadbad,
723 BSTAT_CP_RUNNING = (u32) 0xce11feed,
724 BSTAT_MON_TOO_BIG = (u32) 0x10aded00
725} boot_status_t;
726
727
728
729
730typedef struct soft_uart {
731 u32 send;
732 u32 recv;
733} soft_uart_t;
734
735#define FORE200E_CP_MONITOR_UART_FREE 0x00000000
736#define FORE200E_CP_MONITOR_UART_AVAIL 0x01000000
737
738
739
740
741typedef struct cp_monitor {
742 struct soft_uart soft_uart;
743 enum boot_status bstat;
744 u32 app_base;
745 u32 mon_version;
746} cp_monitor_t;
747
748
749
750
751typedef enum fore200e_state {
752 FORE200E_STATE_BLANK,
753 FORE200E_STATE_REGISTER,
754 FORE200E_STATE_CONFIGURE,
755 FORE200E_STATE_MAP,
756 FORE200E_STATE_RESET,
757 FORE200E_STATE_START_FW,
758 FORE200E_STATE_INITIALIZE,
759 FORE200E_STATE_INIT_CMDQ,
760 FORE200E_STATE_INIT_TXQ,
761 FORE200E_STATE_INIT_RXQ,
762 FORE200E_STATE_INIT_BSQ,
763 FORE200E_STATE_ALLOC_BUF,
764 FORE200E_STATE_IRQ,
765 FORE200E_STATE_COMPLETE
766} fore200e_state;
767
768
769
770
771typedef struct fore200e_pca_regs {
772 volatile u32 __iomem * hcr;
773 volatile u32 __iomem * imr;
774 volatile u32 __iomem * psr;
775} fore200e_pca_regs_t;
776
777
778
779
780typedef struct fore200e_sba_regs {
781 u32 __iomem *hcr;
782 u32 __iomem *bsr;
783 u32 __iomem *isr;
784} fore200e_sba_regs_t;
785
786
787
788
789typedef union fore200e_regs {
790 struct fore200e_pca_regs pca;
791 struct fore200e_sba_regs sba;
792} fore200e_regs;
793
794
795struct fore200e;
796
797
798
799typedef struct fore200e_bus {
800 char* model_name;
801 char* proc_name;
802 int descr_alignment;
803 int buffer_alignment;
804 int status_alignment;
805 u32 (*read)(volatile u32 __iomem *);
806 void (*write)(u32, volatile u32 __iomem *);
807 u32 (*dma_map)(struct fore200e*, void*, int, int);
808 void (*dma_unmap)(struct fore200e*, u32, int, int);
809 void (*dma_sync_for_cpu)(struct fore200e*, u32, int, int);
810 void (*dma_sync_for_device)(struct fore200e*, u32, int, int);
811 int (*dma_chunk_alloc)(struct fore200e*, struct chunk*, int, int, int);
812 void (*dma_chunk_free)(struct fore200e*, struct chunk*);
813 int (*configure)(struct fore200e*);
814 int (*map)(struct fore200e*);
815 void (*reset)(struct fore200e*);
816 int (*prom_read)(struct fore200e*, struct prom_data*);
817 void (*unmap)(struct fore200e*);
818 void (*irq_enable)(struct fore200e*);
819 int (*irq_check)(struct fore200e*);
820 void (*irq_ack)(struct fore200e*);
821 int (*proc_read)(struct fore200e*, char*);
822} fore200e_bus_t;
823
824
825
826typedef struct fore200e_vc_map {
827 struct atm_vcc* vcc;
828 unsigned long incarn;
829} fore200e_vc_map_t;
830
831#define FORE200E_VC_MAP(fore200e, vpi, vci) \
832 (& (fore200e)->vc_map[ ((vpi) << FORE200E_VCI_BITS) | (vci) ])
833
834
835
836
837typedef struct fore200e {
838 struct list_head entry;
839 const struct fore200e_bus* bus;
840 union fore200e_regs regs;
841 struct atm_dev* atm_dev;
842
843 enum fore200e_state state;
844
845 char name[16];
846 void* bus_dev;
847 int irq;
848 unsigned long phys_base;
849 void __iomem * virt_base;
850
851 unsigned char esi[ ESI_LEN ];
852
853 struct cp_monitor __iomem * cp_monitor;
854 struct cp_queues __iomem * cp_queues;
855 struct host_cmdq host_cmdq;
856 struct host_txq host_txq;
857 struct host_rxq host_rxq;
858
859 struct host_bsq host_bsq[ BUFFER_SCHEME_NBR ][ BUFFER_MAGN_NBR ];
860
861 u32 available_cell_rate;
862
863 int loop_mode;
864
865 struct stats* stats;
866
867 struct mutex rate_mtx;
868 spinlock_t q_lock;
869#ifdef FORE200E_USE_TASKLET
870 struct tasklet_struct tx_tasklet;
871 struct tasklet_struct rx_tasklet;
872#endif
873 unsigned long tx_sat;
874
875 unsigned long incarn_count;
876 struct fore200e_vc_map vc_map[ NBR_CONNECT ];
877} fore200e_t;
878
879
880
881
882typedef struct fore200e_vcc {
883 enum buffer_scheme scheme;
884 struct tpd_rate rate;
885 int rx_min_pdu;
886 int rx_max_pdu;
887 int tx_min_pdu;
888 int tx_max_pdu;
889 unsigned long tx_pdu;
890 unsigned long rx_pdu;
891} fore200e_vcc_t;
892
893
894
895
896
897#define FORE200E_CP_MONITOR_OFFSET 0x00000400
898#define FORE200E_CP_QUEUES_OFFSET 0x00004d40
899
900
901
902
903#define PCA200E_IOSPACE_LENGTH 0x00200000
904
905#define PCA200E_HCR_OFFSET 0x00100000
906#define PCA200E_IMR_OFFSET 0x00100004
907#define PCA200E_PSR_OFFSET 0x00100008
908
909
910
911
912#define PCA200E_HCR_RESET (1<<0)
913#define PCA200E_HCR_HOLD_LOCK (1<<1)
914#define PCA200E_HCR_I960FAIL (1<<2)
915#define PCA200E_HCR_INTRB (1<<2)
916#define PCA200E_HCR_HOLD_ACK (1<<3)
917#define PCA200E_HCR_INTRA (1<<3)
918#define PCA200E_HCR_OUTFULL (1<<4)
919#define PCA200E_HCR_CLRINTR (1<<4)
920#define PCA200E_HCR_ESPHOLD (1<<5)
921#define PCA200E_HCR_INFULL (1<<6)
922#define PCA200E_HCR_TESTMODE (1<<7)
923
924
925
926
927#define PCA200E_PCI_LATENCY 0x40
928#define PCA200E_PCI_MASTER_CTRL 0x41
929#define PCA200E_PCI_THRESHOLD 0x42
930
931
932
933#define PCA200E_CTRL_DIS_CACHE_RD (1<<0)
934#define PCA200E_CTRL_DIS_WRT_INVAL (1<<1)
935#define PCA200E_CTRL_2_CACHE_WRT_INVAL (1<<2)
936#define PCA200E_CTRL_IGN_LAT_TIMER (1<<3)
937#define PCA200E_CTRL_ENA_CONT_REQ_MODE (1<<4)
938#define PCA200E_CTRL_LARGE_PCI_BURSTS (1<<5)
939#define PCA200E_CTRL_CONVERT_ENDIAN (1<<6)
940
941
942
943#define SBA200E_PROM_NAME "FORE,sba-200e"
944
945
946
947
948#define SBA200E_HCR_LENGTH 4
949#define SBA200E_BSR_LENGTH 4
950#define SBA200E_ISR_LENGTH 4
951#define SBA200E_RAM_LENGTH 0x40000
952
953
954
955
956#define SBA200E_BSR_BURST4 0x04
957#define SBA200E_BSR_BURST8 0x08
958#define SBA200E_BSR_BURST16 0x10
959
960
961
962
963#define SBA200E_HCR_RESET (1<<0)
964#define SBA200E_HCR_HOLD_LOCK (1<<1)
965#define SBA200E_HCR_I960FAIL (1<<2)
966#define SBA200E_HCR_I960SETINTR (1<<2)
967#define SBA200E_HCR_OUTFULL (1<<3)
968#define SBA200E_HCR_INTR_CLR (1<<3)
969#define SBA200E_HCR_INTR_ENA (1<<4)
970#define SBA200E_HCR_ESPHOLD (1<<5)
971#define SBA200E_HCR_INFULL (1<<6)
972#define SBA200E_HCR_TESTMODE (1<<7)
973#define SBA200E_HCR_INTR_REQ (1<<8)
974
975#define SBA200E_HCR_STICKY (SBA200E_HCR_RESET | SBA200E_HCR_HOLD_LOCK | SBA200E_HCR_INTR_ENA)
976
977
978#endif
979#endif
980