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14#ifndef __DMA_FSLDMA_H
15#define __DMA_FSLDMA_H
16
17#include <linux/device.h>
18#include <linux/dmapool.h>
19#include <linux/dmaengine.h>
20
21
22
23
24#define FSL_DMA_MR_CS 0x00000001
25#define FSL_DMA_MR_CC 0x00000002
26#define FSL_DMA_MR_CA 0x00000008
27#define FSL_DMA_MR_EIE 0x00000040
28#define FSL_DMA_MR_XFE 0x00000020
29#define FSL_DMA_MR_EOLNIE 0x00000100
30#define FSL_DMA_MR_EOLSIE 0x00000080
31#define FSL_DMA_MR_EOSIE 0x00000200
32#define FSL_DMA_MR_CDSM 0x00000010
33#define FSL_DMA_MR_CTM 0x00000004
34#define FSL_DMA_MR_EMP_EN 0x00200000
35#define FSL_DMA_MR_EMS_EN 0x00040000
36#define FSL_DMA_MR_DAHE 0x00002000
37#define FSL_DMA_MR_SAHE 0x00001000
38
39
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41
42
43
44#define FSL_DMA_MR_BWC 0x0A000000
45
46
47#define FSL_DMA_MR_EOTIE 0x00000080
48#define FSL_DMA_MR_PRC_RM 0x00000800
49
50#define FSL_DMA_SR_CH 0x00000020
51#define FSL_DMA_SR_PE 0x00000010
52#define FSL_DMA_SR_CB 0x00000004
53#define FSL_DMA_SR_TE 0x00000080
54#define FSL_DMA_SR_EOSI 0x00000002
55#define FSL_DMA_SR_EOLSI 0x00000001
56#define FSL_DMA_SR_EOCDI 0x00000001
57#define FSL_DMA_SR_EOLNI 0x00000008
58
59#define FSL_DMA_SATR_SBPATMU 0x20000000
60#define FSL_DMA_SATR_STRANSINT_RIO 0x00c00000
61#define FSL_DMA_SATR_SREADTYPE_SNOOP_READ 0x00050000
62#define FSL_DMA_SATR_SREADTYPE_BP_IORH 0x00020000
63#define FSL_DMA_SATR_SREADTYPE_BP_NREAD 0x00040000
64#define FSL_DMA_SATR_SREADTYPE_BP_MREAD 0x00070000
65
66#define FSL_DMA_DATR_DBPATMU 0x20000000
67#define FSL_DMA_DATR_DTRANSINT_RIO 0x00c00000
68#define FSL_DMA_DATR_DWRITETYPE_SNOOP_WRITE 0x00050000
69#define FSL_DMA_DATR_DWRITETYPE_BP_FLUSH 0x00010000
70
71#define FSL_DMA_EOL ((u64)0x1)
72#define FSL_DMA_SNEN ((u64)0x10)
73#define FSL_DMA_EOSIE 0x8
74#define FSL_DMA_NLDA_MASK (~(u64)0x1f)
75
76#define FSL_DMA_BCR_MAX_CNT 0x03ffffffu
77
78#define FSL_DMA_DGSR_TE 0x80
79#define FSL_DMA_DGSR_CH 0x20
80#define FSL_DMA_DGSR_PE 0x10
81#define FSL_DMA_DGSR_EOLNI 0x08
82#define FSL_DMA_DGSR_CB 0x04
83#define FSL_DMA_DGSR_EOSI 0x02
84#define FSL_DMA_DGSR_EOLSI 0x01
85
86typedef u64 __bitwise v64;
87typedef u32 __bitwise v32;
88
89struct fsl_dma_ld_hw {
90 v64 src_addr;
91 v64 dst_addr;
92 v64 next_ln_addr;
93 v32 count;
94 v32 reserve;
95} __attribute__((aligned(32)));
96
97struct fsl_desc_sw {
98 struct fsl_dma_ld_hw hw;
99 struct list_head node;
100 struct list_head tx_list;
101 struct dma_async_tx_descriptor async_tx;
102} __attribute__((aligned(32)));
103
104struct fsldma_chan_regs {
105 u32 mr;
106 u32 sr;
107 u64 cdar;
108 u64 sar;
109 u64 dar;
110 u32 bcr;
111 u64 ndar;
112};
113
114struct fsldma_chan;
115#define FSL_DMA_MAX_CHANS_PER_DEVICE 8
116
117struct fsldma_device {
118 void __iomem *regs;
119 struct device *dev;
120 struct dma_device common;
121 struct fsldma_chan *chan[FSL_DMA_MAX_CHANS_PER_DEVICE];
122 u32 feature;
123 int irq;
124};
125
126
127#define FSL_DMA_LITTLE_ENDIAN 0x00000000
128#define FSL_DMA_BIG_ENDIAN 0x00000001
129
130#define FSL_DMA_IP_MASK 0x00000ff0
131#define FSL_DMA_IP_85XX 0x00000010
132#define FSL_DMA_IP_83XX 0x00000020
133
134#define FSL_DMA_CHAN_PAUSE_EXT 0x00001000
135#define FSL_DMA_CHAN_START_EXT 0x00002000
136
137#ifdef CONFIG_PM
138struct fsldma_chan_regs_save {
139 u32 mr;
140};
141
142enum fsldma_pm_state {
143 RUNNING = 0,
144 SUSPENDED,
145};
146#endif
147
148struct fsldma_chan {
149 char name[8];
150 struct fsldma_chan_regs __iomem *regs;
151 spinlock_t desc_lock;
152
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155
156 struct list_head ld_pending;
157
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160 struct list_head ld_running;
161
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165
166 struct list_head ld_completed;
167 struct dma_chan common;
168 struct dma_pool *desc_pool;
169 struct device *dev;
170 int irq;
171 int id;
172 struct tasklet_struct tasklet;
173 u32 feature;
174 bool idle;
175#ifdef CONFIG_PM
176 struct fsldma_chan_regs_save regs_save;
177 enum fsldma_pm_state pm_state;
178#endif
179
180 void (*toggle_ext_pause)(struct fsldma_chan *fsl_chan, int enable);
181 void (*toggle_ext_start)(struct fsldma_chan *fsl_chan, int enable);
182 void (*set_src_loop_size)(struct fsldma_chan *fsl_chan, int size);
183 void (*set_dst_loop_size)(struct fsldma_chan *fsl_chan, int size);
184 void (*set_request_count)(struct fsldma_chan *fsl_chan, int size);
185};
186
187#define to_fsl_chan(chan) container_of(chan, struct fsldma_chan, common)
188#define to_fsl_desc(lh) container_of(lh, struct fsl_desc_sw, node)
189#define tx_to_fsl_desc(tx) container_of(tx, struct fsl_desc_sw, async_tx)
190
191#ifndef __powerpc64__
192static u64 in_be64(const u64 __iomem *addr)
193{
194 return ((u64)in_be32((u32 __iomem *)addr) << 32) |
195 (in_be32((u32 __iomem *)addr + 1));
196}
197
198static void out_be64(u64 __iomem *addr, u64 val)
199{
200 out_be32((u32 __iomem *)addr, val >> 32);
201 out_be32((u32 __iomem *)addr + 1, (u32)val);
202}
203
204
205static u64 in_le64(const u64 __iomem *addr)
206{
207 return ((u64)in_le32((u32 __iomem *)addr + 1) << 32) |
208 (in_le32((u32 __iomem *)addr));
209}
210
211static void out_le64(u64 __iomem *addr, u64 val)
212{
213 out_le32((u32 __iomem *)addr + 1, val >> 32);
214 out_le32((u32 __iomem *)addr, (u32)val);
215}
216#endif
217
218#define DMA_IN(fsl_chan, addr, width) \
219 (((fsl_chan)->feature & FSL_DMA_BIG_ENDIAN) ? \
220 in_be##width(addr) : in_le##width(addr))
221#define DMA_OUT(fsl_chan, addr, val, width) \
222 (((fsl_chan)->feature & FSL_DMA_BIG_ENDIAN) ? \
223 out_be##width(addr, val) : out_le##width(addr, val))
224
225#define DMA_TO_CPU(fsl_chan, d, width) \
226 (((fsl_chan)->feature & FSL_DMA_BIG_ENDIAN) ? \
227 be##width##_to_cpu((__force __be##width)(v##width)d) : \
228 le##width##_to_cpu((__force __le##width)(v##width)d))
229#define CPU_TO_DMA(fsl_chan, c, width) \
230 (((fsl_chan)->feature & FSL_DMA_BIG_ENDIAN) ? \
231 (__force v##width)cpu_to_be##width(c) : \
232 (__force v##width)cpu_to_le##width(c))
233
234#endif
235
