linux/drivers/gpu/drm/gma500/psb_intel_display.c
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   1/*
   2 * Copyright © 2006-2011 Intel Corporation
   3 *
   4 * This program is free software; you can redistribute it and/or modify it
   5 * under the terms and conditions of the GNU General Public License,
   6 * version 2, as published by the Free Software Foundation.
   7 *
   8 * This program is distributed in the hope it will be useful, but WITHOUT
   9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11 * more details.
  12 *
  13 * You should have received a copy of the GNU General Public License along with
  14 * this program; if not, write to the Free Software Foundation, Inc.,
  15 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  16 *
  17 * Authors:
  18 *      Eric Anholt <eric@anholt.net>
  19 */
  20
  21#include <linux/i2c.h>
  22
  23#include <drm/drmP.h>
  24#include <drm/drm_plane_helper.h>
  25#include "framebuffer.h"
  26#include "psb_drv.h"
  27#include "psb_intel_drv.h"
  28#include "psb_intel_reg.h"
  29#include "gma_display.h"
  30#include "power.h"
  31
  32#define INTEL_LIMIT_I9XX_SDVO_DAC   0
  33#define INTEL_LIMIT_I9XX_LVDS       1
  34
  35static const struct gma_limit_t psb_intel_limits[] = {
  36        {                       /* INTEL_LIMIT_I9XX_SDVO_DAC */
  37         .dot = {.min = 20000, .max = 400000},
  38         .vco = {.min = 1400000, .max = 2800000},
  39         .n = {.min = 1, .max = 6},
  40         .m = {.min = 70, .max = 120},
  41         .m1 = {.min = 8, .max = 18},
  42         .m2 = {.min = 3, .max = 7},
  43         .p = {.min = 5, .max = 80},
  44         .p1 = {.min = 1, .max = 8},
  45         .p2 = {.dot_limit = 200000, .p2_slow = 10, .p2_fast = 5},
  46         .find_pll = gma_find_best_pll,
  47         },
  48        {                       /* INTEL_LIMIT_I9XX_LVDS */
  49         .dot = {.min = 20000, .max = 400000},
  50         .vco = {.min = 1400000, .max = 2800000},
  51         .n = {.min = 1, .max = 6},
  52         .m = {.min = 70, .max = 120},
  53         .m1 = {.min = 8, .max = 18},
  54         .m2 = {.min = 3, .max = 7},
  55         .p = {.min = 7, .max = 98},
  56         .p1 = {.min = 1, .max = 8},
  57         /* The single-channel range is 25-112Mhz, and dual-channel
  58          * is 80-224Mhz.  Prefer single channel as much as possible.
  59          */
  60         .p2 = {.dot_limit = 112000, .p2_slow = 14, .p2_fast = 7},
  61         .find_pll = gma_find_best_pll,
  62         },
  63};
  64
  65static const struct gma_limit_t *psb_intel_limit(struct drm_crtc *crtc,
  66                                                 int refclk)
  67{
  68        const struct gma_limit_t *limit;
  69
  70        if (gma_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
  71                limit = &psb_intel_limits[INTEL_LIMIT_I9XX_LVDS];
  72        else
  73                limit = &psb_intel_limits[INTEL_LIMIT_I9XX_SDVO_DAC];
  74        return limit;
  75}
  76
  77static void psb_intel_clock(int refclk, struct gma_clock_t *clock)
  78{
  79        clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
  80        clock->p = clock->p1 * clock->p2;
  81        clock->vco = refclk * clock->m / (clock->n + 2);
  82        clock->dot = clock->vco / clock->p;
  83}
  84
  85/**
  86 * Return the pipe currently connected to the panel fitter,
  87 * or -1 if the panel fitter is not present or not in use
  88 */
  89static int psb_intel_panel_fitter_pipe(struct drm_device *dev)
  90{
  91        u32 pfit_control;
  92
  93        pfit_control = REG_READ(PFIT_CONTROL);
  94
  95        /* See if the panel fitter is in use */
  96        if ((pfit_control & PFIT_ENABLE) == 0)
  97                return -1;
  98        /* Must be on PIPE 1 for PSB */
  99        return 1;
 100}
 101
 102static int psb_intel_crtc_mode_set(struct drm_crtc *crtc,
 103                               struct drm_display_mode *mode,
 104                               struct drm_display_mode *adjusted_mode,
 105                               int x, int y,
 106                               struct drm_framebuffer *old_fb)
 107{
 108        struct drm_device *dev = crtc->dev;
 109        struct drm_psb_private *dev_priv = dev->dev_private;
 110        struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
 111        struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
 112        int pipe = gma_crtc->pipe;
 113        const struct psb_offset *map = &dev_priv->regmap[pipe];
 114        int refclk;
 115        struct gma_clock_t clock;
 116        u32 dpll = 0, fp = 0, dspcntr, pipeconf;
 117        bool ok, is_sdvo = false;
 118        bool is_lvds = false, is_tv = false;
 119        struct drm_mode_config *mode_config = &dev->mode_config;
 120        struct drm_connector *connector;
 121        const struct gma_limit_t *limit;
 122
 123        /* No scan out no play */
 124        if (crtc->primary->fb == NULL) {
 125                crtc_funcs->mode_set_base(crtc, x, y, old_fb);
 126                return 0;
 127        }
 128
 129        list_for_each_entry(connector, &mode_config->connector_list, head) {
 130                struct gma_encoder *gma_encoder = gma_attached_encoder(connector);
 131
 132                if (!connector->encoder
 133                    || connector->encoder->crtc != crtc)
 134                        continue;
 135
 136                switch (gma_encoder->type) {
 137                case INTEL_OUTPUT_LVDS:
 138                        is_lvds = true;
 139                        break;
 140                case INTEL_OUTPUT_SDVO:
 141                        is_sdvo = true;
 142                        break;
 143                case INTEL_OUTPUT_TVOUT:
 144                        is_tv = true;
 145                        break;
 146                }
 147        }
 148
 149        refclk = 96000;
 150
 151        limit = gma_crtc->clock_funcs->limit(crtc, refclk);
 152
 153        ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk,
 154                                 &clock);
 155        if (!ok) {
 156                DRM_ERROR("Couldn't find PLL settings for mode! target: %d, actual: %d",
 157                          adjusted_mode->clock, clock.dot);
 158                return 0;
 159        }
 160
 161        fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
 162
 163        dpll = DPLL_VGA_MODE_DIS;
 164        if (is_lvds) {
 165                dpll |= DPLLB_MODE_LVDS;
 166                dpll |= DPLL_DVO_HIGH_SPEED;
 167        } else
 168                dpll |= DPLLB_MODE_DAC_SERIAL;
 169        if (is_sdvo) {
 170                int sdvo_pixel_multiply =
 171                            adjusted_mode->clock / mode->clock;
 172                dpll |= DPLL_DVO_HIGH_SPEED;
 173                dpll |=
 174                    (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
 175        }
 176
 177        /* compute bitmask from p1 value */
 178        dpll |= (1 << (clock.p1 - 1)) << 16;
 179        switch (clock.p2) {
 180        case 5:
 181                dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
 182                break;
 183        case 7:
 184                dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
 185                break;
 186        case 10:
 187                dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
 188                break;
 189        case 14:
 190                dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
 191                break;
 192        }
 193
 194        if (is_tv) {
 195                /* XXX: just matching BIOS for now */
 196/*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
 197                dpll |= 3;
 198        }
 199        dpll |= PLL_REF_INPUT_DREFCLK;
 200
 201        /* setup pipeconf */
 202        pipeconf = REG_READ(map->conf);
 203
 204        /* Set up the display plane register */
 205        dspcntr = DISPPLANE_GAMMA_ENABLE;
 206
 207        if (pipe == 0)
 208                dspcntr |= DISPPLANE_SEL_PIPE_A;
 209        else
 210                dspcntr |= DISPPLANE_SEL_PIPE_B;
 211
 212        dspcntr |= DISPLAY_PLANE_ENABLE;
 213        pipeconf |= PIPEACONF_ENABLE;
 214        dpll |= DPLL_VCO_ENABLE;
 215
 216
 217        /* Disable the panel fitter if it was on our pipe */
 218        if (psb_intel_panel_fitter_pipe(dev) == pipe)
 219                REG_WRITE(PFIT_CONTROL, 0);
 220
 221        drm_mode_debug_printmodeline(mode);
 222
 223        if (dpll & DPLL_VCO_ENABLE) {
 224                REG_WRITE(map->fp0, fp);
 225                REG_WRITE(map->dpll, dpll & ~DPLL_VCO_ENABLE);
 226                REG_READ(map->dpll);
 227                udelay(150);
 228        }
 229
 230        /* The LVDS pin pair needs to be on before the DPLLs are enabled.
 231         * This is an exception to the general rule that mode_set doesn't turn
 232         * things on.
 233         */
 234        if (is_lvds) {
 235                u32 lvds = REG_READ(LVDS);
 236
 237                lvds &= ~LVDS_PIPEB_SELECT;
 238                if (pipe == 1)
 239                        lvds |= LVDS_PIPEB_SELECT;
 240
 241                lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
 242                /* Set the B0-B3 data pairs corresponding to
 243                 * whether we're going to
 244                 * set the DPLLs for dual-channel mode or not.
 245                 */
 246                lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
 247                if (clock.p2 == 7)
 248                        lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
 249
 250                /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
 251                 * appropriately here, but we need to look more
 252                 * thoroughly into how panels behave in the two modes.
 253                 */
 254
 255                REG_WRITE(LVDS, lvds);
 256                REG_READ(LVDS);
 257        }
 258
 259        REG_WRITE(map->fp0, fp);
 260        REG_WRITE(map->dpll, dpll);
 261        REG_READ(map->dpll);
 262        /* Wait for the clocks to stabilize. */
 263        udelay(150);
 264
 265        /* write it again -- the BIOS does, after all */
 266        REG_WRITE(map->dpll, dpll);
 267
 268        REG_READ(map->dpll);
 269        /* Wait for the clocks to stabilize. */
 270        udelay(150);
 271
 272        REG_WRITE(map->htotal, (adjusted_mode->crtc_hdisplay - 1) |
 273                  ((adjusted_mode->crtc_htotal - 1) << 16));
 274        REG_WRITE(map->hblank, (adjusted_mode->crtc_hblank_start - 1) |
 275                  ((adjusted_mode->crtc_hblank_end - 1) << 16));
 276        REG_WRITE(map->hsync, (adjusted_mode->crtc_hsync_start - 1) |
 277                  ((adjusted_mode->crtc_hsync_end - 1) << 16));
 278        REG_WRITE(map->vtotal, (adjusted_mode->crtc_vdisplay - 1) |
 279                  ((adjusted_mode->crtc_vtotal - 1) << 16));
 280        REG_WRITE(map->vblank, (adjusted_mode->crtc_vblank_start - 1) |
 281                  ((adjusted_mode->crtc_vblank_end - 1) << 16));
 282        REG_WRITE(map->vsync, (adjusted_mode->crtc_vsync_start - 1) |
 283                  ((adjusted_mode->crtc_vsync_end - 1) << 16));
 284        /* pipesrc and dspsize control the size that is scaled from,
 285         * which should always be the user's requested size.
 286         */
 287        REG_WRITE(map->size,
 288                  ((mode->vdisplay - 1) << 16) | (mode->hdisplay - 1));
 289        REG_WRITE(map->pos, 0);
 290        REG_WRITE(map->src,
 291                  ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
 292        REG_WRITE(map->conf, pipeconf);
 293        REG_READ(map->conf);
 294
 295        gma_wait_for_vblank(dev);
 296
 297        REG_WRITE(map->cntr, dspcntr);
 298
 299        /* Flush the plane changes */
 300        crtc_funcs->mode_set_base(crtc, x, y, old_fb);
 301
 302        gma_wait_for_vblank(dev);
 303
 304        return 0;
 305}
 306
 307/* Returns the clock of the currently programmed mode of the given pipe. */
 308static int psb_intel_crtc_clock_get(struct drm_device *dev,
 309                                struct drm_crtc *crtc)
 310{
 311        struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
 312        struct drm_psb_private *dev_priv = dev->dev_private;
 313        int pipe = gma_crtc->pipe;
 314        const struct psb_offset *map = &dev_priv->regmap[pipe];
 315        u32 dpll;
 316        u32 fp;
 317        struct gma_clock_t clock;
 318        bool is_lvds;
 319        struct psb_pipe *p = &dev_priv->regs.pipe[pipe];
 320
 321        if (gma_power_begin(dev, false)) {
 322                dpll = REG_READ(map->dpll);
 323                if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
 324                        fp = REG_READ(map->fp0);
 325                else
 326                        fp = REG_READ(map->fp1);
 327                is_lvds = (pipe == 1) && (REG_READ(LVDS) & LVDS_PORT_EN);
 328                gma_power_end(dev);
 329        } else {
 330                dpll = p->dpll;
 331
 332                if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
 333                        fp = p->fp0;
 334                else
 335                        fp = p->fp1;
 336
 337                is_lvds = (pipe == 1) && (dev_priv->regs.psb.saveLVDS &
 338                                                                LVDS_PORT_EN);
 339        }
 340
 341        clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
 342        clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
 343        clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
 344
 345        if (is_lvds) {
 346                clock.p1 =
 347                    ffs((dpll &
 348                         DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
 349                        DPLL_FPA01_P1_POST_DIV_SHIFT);
 350                clock.p2 = 14;
 351
 352                if ((dpll & PLL_REF_INPUT_MASK) ==
 353                    PLLB_REF_INPUT_SPREADSPECTRUMIN) {
 354                        /* XXX: might not be 66MHz */
 355                        psb_intel_clock(66000, &clock);
 356                } else
 357                        psb_intel_clock(48000, &clock);
 358        } else {
 359                if (dpll & PLL_P1_DIVIDE_BY_TWO)
 360                        clock.p1 = 2;
 361                else {
 362                        clock.p1 =
 363                            ((dpll &
 364                              DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
 365                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
 366                }
 367                if (dpll & PLL_P2_DIVIDE_BY_4)
 368                        clock.p2 = 4;
 369                else
 370                        clock.p2 = 2;
 371
 372                psb_intel_clock(48000, &clock);
 373        }
 374
 375        /* XXX: It would be nice to validate the clocks, but we can't reuse
 376         * i830PllIsValid() because it relies on the xf86_config connector
 377         * configuration being accurate, which it isn't necessarily.
 378         */
 379
 380        return clock.dot;
 381}
 382
 383/** Returns the currently programmed mode of the given pipe. */
 384struct drm_display_mode *psb_intel_crtc_mode_get(struct drm_device *dev,
 385                                             struct drm_crtc *crtc)
 386{
 387        struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
 388        int pipe = gma_crtc->pipe;
 389        struct drm_display_mode *mode;
 390        int htot;
 391        int hsync;
 392        int vtot;
 393        int vsync;
 394        struct drm_psb_private *dev_priv = dev->dev_private;
 395        struct psb_pipe *p = &dev_priv->regs.pipe[pipe];
 396        const struct psb_offset *map = &dev_priv->regmap[pipe];
 397
 398        if (gma_power_begin(dev, false)) {
 399                htot = REG_READ(map->htotal);
 400                hsync = REG_READ(map->hsync);
 401                vtot = REG_READ(map->vtotal);
 402                vsync = REG_READ(map->vsync);
 403                gma_power_end(dev);
 404        } else {
 405                htot = p->htotal;
 406                hsync = p->hsync;
 407                vtot = p->vtotal;
 408                vsync = p->vsync;
 409        }
 410
 411        mode = kzalloc(sizeof(*mode), GFP_KERNEL);
 412        if (!mode)
 413                return NULL;
 414
 415        mode->clock = psb_intel_crtc_clock_get(dev, crtc);
 416        mode->hdisplay = (htot & 0xffff) + 1;
 417        mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
 418        mode->hsync_start = (hsync & 0xffff) + 1;
 419        mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
 420        mode->vdisplay = (vtot & 0xffff) + 1;
 421        mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
 422        mode->vsync_start = (vsync & 0xffff) + 1;
 423        mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
 424
 425        drm_mode_set_name(mode);
 426        drm_mode_set_crtcinfo(mode, 0);
 427
 428        return mode;
 429}
 430
 431const struct drm_crtc_helper_funcs psb_intel_helper_funcs = {
 432        .dpms = gma_crtc_dpms,
 433        .mode_fixup = gma_crtc_mode_fixup,
 434        .mode_set = psb_intel_crtc_mode_set,
 435        .mode_set_base = gma_pipe_set_base,
 436        .prepare = gma_crtc_prepare,
 437        .commit = gma_crtc_commit,
 438        .disable = gma_crtc_disable,
 439};
 440
 441const struct drm_crtc_funcs psb_intel_crtc_funcs = {
 442        .save = gma_crtc_save,
 443        .restore = gma_crtc_restore,
 444        .cursor_set = gma_crtc_cursor_set,
 445        .cursor_move = gma_crtc_cursor_move,
 446        .gamma_set = gma_crtc_gamma_set,
 447        .set_config = gma_crtc_set_config,
 448        .destroy = gma_crtc_destroy,
 449};
 450
 451const struct gma_clock_funcs psb_clock_funcs = {
 452        .clock = psb_intel_clock,
 453        .limit = psb_intel_limit,
 454        .pll_is_valid = gma_pll_is_valid,
 455};
 456
 457/*
 458 * Set the default value of cursor control and base register
 459 * to zero. This is a workaround for h/w defect on Oaktrail
 460 */
 461static void psb_intel_cursor_init(struct drm_device *dev,
 462                                  struct gma_crtc *gma_crtc)
 463{
 464        struct drm_psb_private *dev_priv = dev->dev_private;
 465        u32 control[3] = { CURACNTR, CURBCNTR, CURCCNTR };
 466        u32 base[3] = { CURABASE, CURBBASE, CURCBASE };
 467        struct gtt_range *cursor_gt;
 468
 469        if (dev_priv->ops->cursor_needs_phys) {
 470                /* Allocate 4 pages of stolen mem for a hardware cursor. That
 471                 * is enough for the 64 x 64 ARGB cursors we support.
 472                 */
 473                cursor_gt = psb_gtt_alloc_range(dev, 4 * PAGE_SIZE, "cursor", 1,
 474                                                PAGE_SIZE);
 475                if (!cursor_gt) {
 476                        gma_crtc->cursor_gt = NULL;
 477                        goto out;
 478                }
 479                gma_crtc->cursor_gt = cursor_gt;
 480                gma_crtc->cursor_addr = dev_priv->stolen_base +
 481                                                        cursor_gt->offset;
 482        } else {
 483                gma_crtc->cursor_gt = NULL;
 484        }
 485
 486out:
 487        REG_WRITE(control[gma_crtc->pipe], 0);
 488        REG_WRITE(base[gma_crtc->pipe], 0);
 489}
 490
 491void psb_intel_crtc_init(struct drm_device *dev, int pipe,
 492                     struct psb_intel_mode_device *mode_dev)
 493{
 494        struct drm_psb_private *dev_priv = dev->dev_private;
 495        struct gma_crtc *gma_crtc;
 496        int i;
 497        uint16_t *r_base, *g_base, *b_base;
 498
 499        /* We allocate a extra array of drm_connector pointers
 500         * for fbdev after the crtc */
 501        gma_crtc = kzalloc(sizeof(struct gma_crtc) +
 502                        (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)),
 503                        GFP_KERNEL);
 504        if (gma_crtc == NULL)
 505                return;
 506
 507        gma_crtc->crtc_state =
 508                kzalloc(sizeof(struct psb_intel_crtc_state), GFP_KERNEL);
 509        if (!gma_crtc->crtc_state) {
 510                dev_err(dev->dev, "Crtc state error: No memory\n");
 511                kfree(gma_crtc);
 512                return;
 513        }
 514
 515        /* Set the CRTC operations from the chip specific data */
 516        drm_crtc_init(dev, &gma_crtc->base, dev_priv->ops->crtc_funcs);
 517
 518        /* Set the CRTC clock functions from chip specific data */
 519        gma_crtc->clock_funcs = dev_priv->ops->clock_funcs;
 520
 521        drm_mode_crtc_set_gamma_size(&gma_crtc->base, 256);
 522        gma_crtc->pipe = pipe;
 523        gma_crtc->plane = pipe;
 524
 525        r_base = gma_crtc->base.gamma_store;
 526        g_base = r_base + 256;
 527        b_base = g_base + 256;
 528        for (i = 0; i < 256; i++) {
 529                gma_crtc->lut_r[i] = i;
 530                gma_crtc->lut_g[i] = i;
 531                gma_crtc->lut_b[i] = i;
 532                r_base[i] = i << 8;
 533                g_base[i] = i << 8;
 534                b_base[i] = i << 8;
 535
 536                gma_crtc->lut_adj[i] = 0;
 537        }
 538
 539        gma_crtc->mode_dev = mode_dev;
 540        gma_crtc->cursor_addr = 0;
 541
 542        drm_crtc_helper_add(&gma_crtc->base,
 543                                                dev_priv->ops->crtc_helper);
 544
 545        /* Setup the array of drm_connector pointer array */
 546        gma_crtc->mode_set.crtc = &gma_crtc->base;
 547        BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
 548               dev_priv->plane_to_crtc_mapping[gma_crtc->plane] != NULL);
 549        dev_priv->plane_to_crtc_mapping[gma_crtc->plane] = &gma_crtc->base;
 550        dev_priv->pipe_to_crtc_mapping[gma_crtc->pipe] = &gma_crtc->base;
 551        gma_crtc->mode_set.connectors = (struct drm_connector **)(gma_crtc + 1);
 552        gma_crtc->mode_set.num_connectors = 0;
 553        psb_intel_cursor_init(dev, gma_crtc);
 554
 555        /* Set to true so that the pipe is forced off on initial config. */
 556        gma_crtc->active = true;
 557}
 558
 559struct drm_crtc *psb_intel_get_crtc_from_pipe(struct drm_device *dev, int pipe)
 560{
 561        struct drm_crtc *crtc = NULL;
 562
 563        list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
 564                struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
 565                if (gma_crtc->pipe == pipe)
 566                        break;
 567        }
 568        return crtc;
 569}
 570
 571int gma_connector_clones(struct drm_device *dev, int type_mask)
 572{
 573        int index_mask = 0;
 574        struct drm_connector *connector;
 575        int entry = 0;
 576
 577        list_for_each_entry(connector, &dev->mode_config.connector_list,
 578                            head) {
 579                struct gma_encoder *gma_encoder = gma_attached_encoder(connector);
 580                if (type_mask & (1 << gma_encoder->type))
 581                        index_mask |= (1 << entry);
 582                entry++;
 583        }
 584        return index_mask;
 585}
 586