LXR linux/drivers/gpu/drm/msm/mdp/mdp5/mdp5

   1/*
   2 * Copyright (C) 2013 Red Hat
   3 * Author: Rob Clark <robdclark@gmail.com>
   4 *
   5 * This program is free software; you can redistribute it and/or modify it
   6 * under the terms of the GNU General Public License version 2 as published by
   7 * the Free Software Foundation.
   8 *
   9 * This program is distributed in the hope that it will be useful, but WITHOUT
  10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12 * more details.
  13 *
  14 * You should have received a copy of the GNU General Public License along with
  15 * this program.  If not, see <http://www.gnu.org/licenses/>.
  16 */
  17
  18#ifndef __MDP5_KMS_H__
  19#define __MDP5_KMS_H__
  20
  21#include "msm_drv.h"
  22#include "msm_kms.h"
  23#include "mdp/mdp_kms.h"
  24#include "mdp5_cfg.h"   /* must be included before mdp5.xml.h */
  25#include "mdp5.xml.h"
  26#include "mdp5_ctl.h"
  27#include "mdp5_smp.h"
  28
  29struct mdp5_kms {
  30        struct mdp_kms base;
  31
  32        struct drm_device *dev;
  33
  34        struct mdp5_cfg_handler *cfg;
  35
  36        /* mapper-id used to request GEM buffer mapped for scanout: */
  37        int id;
  38        struct msm_mmu *mmu;
  39
  40        struct mdp5_smp *smp;
  41        struct mdp5_ctl_manager *ctlm;
  42
  43        /* io/register spaces: */
  44        void __iomem *mmio, *vbif;
  45
  46        struct regulator *vdd;
  47
  48        struct clk *axi_clk;
  49        struct clk *ahb_clk;
  50        struct clk *src_clk;
  51        struct clk *core_clk;
  52        struct clk *lut_clk;
  53        struct clk *vsync_clk;
  54
  55        /*
  56         * lock to protect access to global resources: ie., following register:
  57         *      - REG_MDP5_DISP_INTF_SEL
  58         */
  59        spinlock_t resource_lock;
  60
  61        struct mdp_irq error_handler;
  62
  63        struct {
  64                volatile unsigned long enabled_mask;
  65                struct irq_domain *domain;
  66        } irqcontroller;
  67};
  68#define to_mdp5_kms(x) container_of(x, struct mdp5_kms, base)
  69
  70struct mdp5_plane_state {
  71        struct drm_plane_state base;
  72
  73        /* "virtual" zpos.. we calculate actual mixer-stage at runtime
  74         * by sorting the attached planes by zpos and then assigning
  75         * mixer stage lowest to highest.  Private planes get default
  76         * zpos of zero, and public planes a unique value that is
  77         * greater than zero.  This way, things work out if a naive
  78         * userspace assigns planes to a crtc without setting zpos.
  79         */
  80        int zpos;
  81
  82        /* the actual mixer stage, calculated in crtc->atomic_check()
  83         * NOTE: this should move to mdp5_crtc_state, when that exists
  84         */
  85        enum mdp_mixer_stage_id stage;
  86
  87        /* some additional transactional status to help us know in the
  88         * apply path whether we need to update SMP allocation, and
  89         * whether current update is still pending:
  90         */
  91        bool mode_changed : 1;
  92        bool pending : 1;
  93};
  94#define to_mdp5_plane_state(x) \
  95                container_of(x, struct mdp5_plane_state, base)
  96
  97static inline void mdp5_write(struct mdp5_kms *mdp5_kms, u32 reg, u32 data)
  98{
  99        msm_writel(data, mdp5_kms->mmio + reg);
 100}
 101
 102static inline u32 mdp5_read(struct mdp5_kms *mdp5_kms, u32 reg)
 103{
 104        return msm_readl(mdp5_kms->mmio + reg);
 105}
 106
 107static inline const char *pipe2name(enum mdp5_pipe pipe)
 108{
 109        static const char *names[] = {
 110#define NAME(n) [SSPP_ ## n] = #n
 111                NAME(VIG0), NAME(VIG1), NAME(VIG2),
 112                NAME(RGB0), NAME(RGB1), NAME(RGB2),
 113                NAME(DMA0), NAME(DMA1),
 114                NAME(VIG3), NAME(RGB3),
 115#undef NAME
 116        };
 117        return names[pipe];
 118}
 119
 120static inline int pipe2nclients(enum mdp5_pipe pipe)
 121{
 122        switch (pipe) {
 123        case SSPP_RGB0:
 124        case SSPP_RGB1:
 125        case SSPP_RGB2:
 126        case SSPP_RGB3:
 127                return 1;
 128        default:
 129                return 3;
 130        }
 131}
 132
 133static inline uint32_t intf2err(int intf)
 134{
 135        switch (intf) {
 136        case 0:  return MDP5_IRQ_INTF0_UNDER_RUN;
 137        case 1:  return MDP5_IRQ_INTF1_UNDER_RUN;
 138        case 2:  return MDP5_IRQ_INTF2_UNDER_RUN;
 139        case 3:  return MDP5_IRQ_INTF3_UNDER_RUN;
 140        default: return 0;
 141        }
 142}
 143
 144static inline uint32_t intf2vblank(int intf)
 145{
 146        switch (intf) {
 147        case 0:  return MDP5_IRQ_INTF0_VSYNC;
 148        case 1:  return MDP5_IRQ_INTF1_VSYNC;
 149        case 2:  return MDP5_IRQ_INTF2_VSYNC;
 150        case 3:  return MDP5_IRQ_INTF3_VSYNC;
 151        default: return 0;
 152        }
 153}
 154
 155int mdp5_disable(struct mdp5_kms *mdp5_kms);
 156int mdp5_enable(struct mdp5_kms *mdp5_kms);
 157
 158void mdp5_set_irqmask(struct mdp_kms *mdp_kms, uint32_t irqmask);
 159void mdp5_irq_preinstall(struct msm_kms *kms);
 160int mdp5_irq_postinstall(struct msm_kms *kms);
 161void mdp5_irq_uninstall(struct msm_kms *kms);
 162irqreturn_t mdp5_irq(struct msm_kms *kms);
 163int mdp5_enable_vblank(struct msm_kms *kms, struct drm_crtc *crtc);
 164void mdp5_disable_vblank(struct msm_kms *kms, struct drm_crtc *crtc);
 165int mdp5_irq_domain_init(struct mdp5_kms *mdp5_kms);
 166void mdp5_irq_domain_fini(struct mdp5_kms *mdp5_kms);
 167
 168static inline
 169uint32_t mdp5_get_formats(enum mdp5_pipe pipe, uint32_t *pixel_formats,
 170                uint32_t max_formats)
 171{
 172        /* TODO when we have YUV, we need to filter supported formats
 173         * based on pipe id..
 174         */
 175        return mdp_get_formats(pixel_formats, max_formats);
 176}
 177
 178void mdp5_plane_install_properties(struct drm_plane *plane,
 179                struct drm_mode_object *obj);
 180uint32_t mdp5_plane_get_flush(struct drm_plane *plane);
 181void mdp5_plane_complete_flip(struct drm_plane *plane);
 182enum mdp5_pipe mdp5_plane_pipe(struct drm_plane *plane);
 183struct drm_plane *mdp5_plane_init(struct drm_device *dev,
 184                enum mdp5_pipe pipe, bool private_plane, uint32_t reg_offset);
 185
 186uint32_t mdp5_crtc_vblank(struct drm_crtc *crtc);
 187
 188int mdp5_crtc_get_lm(struct drm_crtc *crtc);
 189void mdp5_crtc_cancel_pending_flip(struct drm_crtc *crtc, struct drm_file *file);
 190void mdp5_crtc_set_intf(struct drm_crtc *crtc, int intf,
 191                enum mdp5_intf intf_id);
 192struct drm_crtc *mdp5_crtc_init(struct drm_device *dev,
 193                struct drm_plane *plane, int id);
 194
 195struct drm_encoder *mdp5_encoder_init(struct drm_device *dev, int intf,
 196                enum mdp5_intf intf_id);
 197
 198#endif /* __MDP5_KMS_H__ */
 199