LXR linux/drivers/gpu/drm/nouveau/core/engine/disp/nv84.c

   1/*
   2 * Copyright 2012 Red Hat Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 * Authors: Ben Skeggs
  23 */
  24
  25#include <engine/software.h>
  26#include <engine/disp.h>
  27
  28#include <nvif/class.h>
  29
  30#include "nv50.h"
  31
  32/*******************************************************************************
  33 * EVO master channel object
  34 ******************************************************************************/
  35
  36const struct nv50_disp_mthd_list
  37nv84_disp_core_mthd_dac = {
  38        .mthd = 0x0080,
  39        .addr = 0x000008,
  40        .data = {
  41                { 0x0400, 0x610b58 },
  42                { 0x0404, 0x610bdc },
  43                { 0x0420, 0x610bc4 },
  44                {}
  45        }
  46};
  47
  48const struct nv50_disp_mthd_list
  49nv84_disp_core_mthd_head = {
  50        .mthd = 0x0400,
  51        .addr = 0x000540,
  52        .data = {
  53                { 0x0800, 0x610ad8 },
  54                { 0x0804, 0x610ad0 },
  55                { 0x0808, 0x610a48 },
  56                { 0x080c, 0x610a78 },
  57                { 0x0810, 0x610ac0 },
  58                { 0x0814, 0x610af8 },
  59                { 0x0818, 0x610b00 },
  60                { 0x081c, 0x610ae8 },
  61                { 0x0820, 0x610af0 },
  62                { 0x0824, 0x610b08 },
  63                { 0x0828, 0x610b10 },
  64                { 0x082c, 0x610a68 },
  65                { 0x0830, 0x610a60 },
  66                { 0x0834, 0x000000 },
  67                { 0x0838, 0x610a40 },
  68                { 0x0840, 0x610a24 },
  69                { 0x0844, 0x610a2c },
  70                { 0x0848, 0x610aa8 },
  71                { 0x084c, 0x610ab0 },
  72                { 0x085c, 0x610c5c },
  73                { 0x0860, 0x610a84 },
  74                { 0x0864, 0x610a90 },
  75                { 0x0868, 0x610b18 },
  76                { 0x086c, 0x610b20 },
  77                { 0x0870, 0x610ac8 },
  78                { 0x0874, 0x610a38 },
  79                { 0x0878, 0x610c50 },
  80                { 0x0880, 0x610a58 },
  81                { 0x0884, 0x610a9c },
  82                { 0x089c, 0x610c68 },
  83                { 0x08a0, 0x610a70 },
  84                { 0x08a4, 0x610a50 },
  85                { 0x08a8, 0x610ae0 },
  86                { 0x08c0, 0x610b28 },
  87                { 0x08c4, 0x610b30 },
  88                { 0x08c8, 0x610b40 },
  89                { 0x08d4, 0x610b38 },
  90                { 0x08d8, 0x610b48 },
  91                { 0x08dc, 0x610b50 },
  92                { 0x0900, 0x610a18 },
  93                { 0x0904, 0x610ab8 },
  94                { 0x0910, 0x610c70 },
  95                { 0x0914, 0x610c78 },
  96                {}
  97        }
  98};
  99
 100const struct nv50_disp_mthd_chan
 101nv84_disp_core_mthd_chan = {
 102        .name = "Core",
 103        .addr = 0x000000,
 104        .data = {
 105                { "Global", 1, &nv50_disp_core_mthd_base },
 106                {    "DAC", 3, &nv84_disp_core_mthd_dac  },
 107                {    "SOR", 2, &nv50_disp_core_mthd_sor  },
 108                {   "PIOR", 3, &nv50_disp_core_mthd_pior },
 109                {   "HEAD", 2, &nv84_disp_core_mthd_head },
 110                {}
 111        }
 112};
 113
 114/*******************************************************************************
 115 * EVO sync channel objects
 116 ******************************************************************************/
 117
 118static const struct nv50_disp_mthd_list
 119nv84_disp_base_mthd_base = {
 120        .mthd = 0x0000,
 121        .addr = 0x000000,
 122        .data = {
 123                { 0x0080, 0x000000 },
 124                { 0x0084, 0x0008c4 },
 125                { 0x0088, 0x0008d0 },
 126                { 0x008c, 0x0008dc },
 127                { 0x0090, 0x0008e4 },
 128                { 0x0094, 0x610884 },
 129                { 0x00a0, 0x6108a0 },
 130                { 0x00a4, 0x610878 },
 131                { 0x00c0, 0x61086c },
 132                { 0x00c4, 0x610800 },
 133                { 0x00c8, 0x61080c },
 134                { 0x00cc, 0x610818 },
 135                { 0x00e0, 0x610858 },
 136                { 0x00e4, 0x610860 },
 137                { 0x00e8, 0x6108ac },
 138                { 0x00ec, 0x6108b4 },
 139                { 0x00fc, 0x610824 },
 140                { 0x0100, 0x610894 },
 141                { 0x0104, 0x61082c },
 142                { 0x0110, 0x6108bc },
 143                { 0x0114, 0x61088c },
 144                {}
 145        }
 146};
 147
 148const struct nv50_disp_mthd_chan
 149nv84_disp_base_mthd_chan = {
 150        .name = "Base",
 151        .addr = 0x000540,
 152        .data = {
 153                { "Global", 1, &nv84_disp_base_mthd_base },
 154                {  "Image", 2, &nv50_disp_base_mthd_image },
 155                {}
 156        }
 157};
 158
 159/*******************************************************************************
 160 * EVO overlay channel objects
 161 ******************************************************************************/
 162
 163static const struct nv50_disp_mthd_list
 164nv84_disp_ovly_mthd_base = {
 165        .mthd = 0x0000,
 166        .addr = 0x000000,
 167        .data = {
 168                { 0x0080, 0x000000 },
 169                { 0x0084, 0x6109a0 },
 170                { 0x0088, 0x6109c0 },
 171                { 0x008c, 0x6109c8 },
 172                { 0x0090, 0x6109b4 },
 173                { 0x0094, 0x610970 },
 174                { 0x00a0, 0x610998 },
 175                { 0x00a4, 0x610964 },
 176                { 0x00c0, 0x610958 },
 177                { 0x00e0, 0x6109a8 },
 178                { 0x00e4, 0x6109d0 },
 179                { 0x00e8, 0x6109d8 },
 180                { 0x0100, 0x61094c },
 181                { 0x0104, 0x610984 },
 182                { 0x0108, 0x61098c },
 183                { 0x0800, 0x6109f8 },
 184                { 0x0808, 0x610a08 },
 185                { 0x080c, 0x610a10 },
 186                { 0x0810, 0x610a00 },
 187                {}
 188        }
 189};
 190
 191const struct nv50_disp_mthd_chan
 192nv84_disp_ovly_mthd_chan = {
 193        .name = "Overlay",
 194        .addr = 0x000540,
 195        .data = {
 196                { "Global", 1, &nv84_disp_ovly_mthd_base },
 197                {}
 198        }
 199};
 200
 201/*******************************************************************************
 202 * Base display object
 203 ******************************************************************************/
 204
 205static struct nouveau_oclass
 206nv84_disp_sclass[] = {
 207        { G82_DISP_CORE_CHANNEL_DMA, &nv50_disp_core_ofuncs.base },
 208        { G82_DISP_BASE_CHANNEL_DMA, &nv50_disp_base_ofuncs.base },
 209        { G82_DISP_OVERLAY_CHANNEL_DMA, &nv50_disp_ovly_ofuncs.base },
 210        { G82_DISP_OVERLAY, &nv50_disp_oimm_ofuncs.base },
 211        { G82_DISP_CURSOR, &nv50_disp_curs_ofuncs.base },
 212        {}
 213};
 214
 215static struct nouveau_oclass
 216nv84_disp_main_oclass[] = {
 217        { G82_DISP, &nv50_disp_main_ofuncs },
 218        {}
 219};
 220
 221/*******************************************************************************
 222 * Display engine implementation
 223 ******************************************************************************/
 224
 225static int
 226nv84_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
 227               struct nouveau_oclass *oclass, void *data, u32 size,
 228               struct nouveau_object **pobject)
 229{
 230        struct nv50_disp_priv *priv;
 231        int ret;
 232
 233        ret = nouveau_disp_create(parent, engine, oclass, 2, "PDISP",
 234                                  "display", &priv);
 235        *pobject = nv_object(priv);
 236        if (ret)
 237                return ret;
 238
 239        ret = nvkm_event_init(&nv50_disp_chan_uevent, 1, 9, &priv->uevent);
 240        if (ret)
 241                return ret;
 242
 243        nv_engine(priv)->sclass = nv84_disp_main_oclass;
 244        nv_engine(priv)->cclass = &nv50_disp_cclass;
 245        nv_subdev(priv)->intr = nv50_disp_intr;
 246        INIT_WORK(&priv->supervisor, nv50_disp_intr_supervisor);
 247        priv->sclass = nv84_disp_sclass;
 248        priv->head.nr = 2;
 249        priv->dac.nr = 3;
 250        priv->sor.nr = 2;
 251        priv->pior.nr = 3;
 252        priv->dac.power = nv50_dac_power;
 253        priv->dac.sense = nv50_dac_sense;
 254        priv->sor.power = nv50_sor_power;
 255        priv->sor.hdmi = nv84_hdmi_ctrl;
 256        priv->pior.power = nv50_pior_power;
 257        return 0;
 258}
 259
 260struct nouveau_oclass *
 261nv84_disp_oclass = &(struct nv50_disp_impl) {
 262        .base.base.handle = NV_ENGINE(DISP, 0x82),
 263        .base.base.ofuncs = &(struct nouveau_ofuncs) {
 264                .ctor = nv84_disp_ctor,
 265                .dtor = _nouveau_disp_dtor,
 266                .init = _nouveau_disp_init,
 267                .fini = _nouveau_disp_fini,
 268        },
 269        .base.vblank = &nv50_disp_vblank_func,
 270        .base.outp =  nv50_disp_outp_sclass,
 271        .mthd.core = &nv84_disp_core_mthd_chan,
 272        .mthd.base = &nv84_disp_base_mthd_chan,
 273        .mthd.ovly = &nv84_disp_ovly_mthd_chan,
 274        .mthd.prev = 0x000004,
 275        .head.scanoutpos = nv50_disp_main_scanoutpos,
 276}.base.base;
 277